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本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。
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: y. {- \2 e. s, o如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。0 t6 R4 t1 g% U& z3 e
5 I$ j" ?5 D4 O( Y1 P# l6 z e2 xThe 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The: B) i& J0 ^; O v: H3 @& F' r7 C
configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
* e" m3 j# `1 X( ?& _8 q7 r% ]in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To5 Y l, ^ c/ E5 x3 p
support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,* m! I" w( x6 J+ b2 F
the following is required:
( ]2 u( D* u: }% Q( n* Z$ r* W• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
( X! Z3 q! S# x) l8 P7 V+ Hor Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15. h a" J/ a% M7 B
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for: U% d7 r) \: }" r5 [: N
1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V) D9 A! `: C6 p) A2 j6 \
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
0 P. A' d5 F, ~! v8 j" {- I& `+ Bconfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
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发表于 2014-4-15 18:32
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支持！
反对！
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