|
|
http://dl.vmall.com/c0fu1auqa8" \, J6 l6 E% c8 \9 Y' G
`8 I3 x; u, [8 i
# X# v* U& ?" V# a8 C
, I0 A% b+ T0 \* F9 C
DATE: 02-14-2014 HOTFIX VERSION: 023
b' S! v8 U1 K! t: K+ j& q=================================================================================================================================== j* y, Z3 t. F8 x4 i" L
CCRID PRODUCT PRODUCTLEVEL2 TITLE, O" `* T) P( ?
===================================================================================================================================, Y% C$ p3 W0 ~$ ]
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.: T( c; p7 H; ]) P& n
1202715 SPIF OTHER Objects loose module group attribute after Specctra A$ [3 k" R$ |# [4 U- Q2 D
1203443 ADW LRM LRM takes a long time to launch for the first time2 m8 M% v2 `9 i9 P/ V; o( M% J, W; p
1207204 CONCEPT_HDL CORE schematic tool crashed during save all
+ _; e" r- y* j7 U( ~7 I; @' \1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
$ w2 ~& |0 Q. B3 x1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
* }5 _' Y- U: o3 d+ B1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side, p9 V0 b5 ^. r7 {% H
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
2 Q( x3 J/ E+ C: ?% d' v2 _9 t1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.1 f4 N! I2 V! v% v. x
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
2 q7 m# k+ s" W1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
7 s; U! a; v- L1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7" p7 V$ \; p# u, G" p
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's( J l* n( `4 a" w4 {
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
6 M H- k1 U# R0 X) J4 u1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
/ j5 V3 L9 N: M1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form; B- j8 A6 Y3 v0 |: u5 R8 s
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.0 V5 P, X- k* ?% _0 B/ Y4 ^
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
' l/ P7 Y1 \) i: r% h1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
, B; H6 K! o) F! V# V1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.( ~ O, ~3 {" E1 A
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
E6 d! {% F# G) A" f2 a$ v' f$ f$ I1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
$ `$ C0 I5 _+ [5 c( }1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
. ]5 k+ A# O( t1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 16:44
收藏
淘帖
支持！
反对！
楼主
