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You have module Clock_Generator.v
- T. x4 T/ Q* q; pwith port input [31:0] key_value
, R7 X1 {# B- ~* f5 J1 Y) z! Pand you set a instance of ) C# p. y' O. c0 e# O! f
key_scan_jitter key_scan_jitter_inst
, H$ s- o4 m# z4 ~* m2 o3 q! C ($ a& u3 {) ^4 n2 r
.clk(clk),( e I: J! f6 g; ]8 L1 z7 _. g
.rst_n(rst_n),/ A; }! J; T3 H# N5 V
.key_data(key_data),
& t$ j3 ^& ~: q# w" K .key_flag(key_flag),
( u# g# H, V7 E% z .key_value(key_value)+ I! x$ }* y4 T1 P" u
);: I) A9 N* K' N- c# }! p: T$ ~
In module key_scan_jitter.v
6 k) x) _, ^/ Q3 z! ^; D9 N0 ^$ l4 ?& |you have output[31:0] key_value
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So module have to source of key_value:
- |( i2 |: P, t5 a1. From input port (may be 32 pins of chip)
3 J. W5 z1 i! V) ?5 Q/ M# w2. From internal instance key_scan_jitter 4 }/ |+ i1 E$ |8 {2 F: H+ Z5 M
: o3 |. C& R& u- H
Altera can-t to do short circuit in your module.
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发表于 2013-12-20 08:23
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支持！
反对！
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