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本帖最后由 yulizi 于 2011-12-22 11:18 编辑
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http://kuai.xunlei.com/d/DGOHIFKLICUP% O' R+ o2 e+ e' N; f, E
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9 R& Q4 a' g* ~. u3 p& ?$ u7 bDATE: 12-16-2011 HOTFIX VERSION: 013* {( l8 v& v" W5 p- D
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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- A8 x+ m8 M% _1 N! V% z. i7 H875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.+ h, F) f0 @' J
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
! o8 N+ B$ b3 i) t% ?3 u7 r% p938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT6 n4 @9 \1 Q" A
941409 Pspice PROBE BUG : Search accuracy wrong in new cursor window7 }' k% T; F$ x* Y$ T9 f4 J
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command# ~9 b0 x5 i0 O8 }$ V1 S; f
946293 concept_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
1 H) P* v! s/ K946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus.
! l, P$ o$ }$ K- i. a2 h0 q950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function n5 J }0 _3 G
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
5 [. |9 n G" _" y; g953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
8 `4 C0 l O8 a: L953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
: d% m5 m7 R: f* {/ N953971 allegro_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?
" j) o: ]( L2 ^* D0 y954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.0 F% E. r' b7 C" l7 t+ l
954498 SCM B2F SCM crashes when importing physical1 V% s9 R- b" I i) H% \; x
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?1 F3 s2 @9 E# K8 _: c( p+ C4 _
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
G# M9 R& @& p; R& ~, P" q) G955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
; `* F# w' p1 ^% }6 @, O+ C- s955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
+ {7 Q2 L8 i: `+ K0 z8 F955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
) ]+ p7 W$ O% }; e/ p955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
! B) U! Q7 E$ W, \& n955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
5 i* `5 i% z! d955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
8 ^: I/ N f" [, Z7 M9 F955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
" R' }) B, R T4 N( t- t8 ~, N955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass2 ]3 H+ Q5 s: d' N- R; ^
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void) @- V7 i% g2 u, G w9 Z2 a
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.% k2 N6 c. C" S8 x. c8 E& M
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file! A0 Z' }3 o% T1 m! L9 m- g
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.# D' k" d+ y4 ?* W5 X4 h4 q3 ~
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found# N+ K3 ]: d) P/ s! W, i
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
q& x* M* v# b' C: c956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board; g0 z* j( L' R: k
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component, o: O6 M6 ?$ ^
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly: `8 p, g! h+ k% {$ O
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
, V) J3 R( ^$ a- [956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
3 V/ ~8 L6 V/ y5 L+ u4 U956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
2 O3 P' @, c: l5 `' A1 ~' E957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor pads PCB netlist. Y* S# |) b m$ e& {
957137 APD DXF_IF DXF out command dose not work correctly./ H7 [' M# S2 c" I! E0 @
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
, n/ Y2 L) p+ s- ]+ X. Y957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.2 Y" I' i( Z# E
957267 CONCEPT_HDL INFRA Packager Error after Import Design
. g0 ]2 S9 S# j+ C957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file$ |) h7 ^7 _. U5 L( s8 D; U
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
0 T! |, x x, A, X. h8 c958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design& \: G4 E, O$ a) y( Q( m! A
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
! B! M( f6 B0 |0 b) s; ~" O) e7 x958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
" g( y3 j3 L8 p# U! h3 u6 s/ O958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.52 s$ `( |: w/ X! E" @: [
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
- d: V/ [! k3 k6 e% `- x959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs/ e7 e/ E0 z2 j+ t: X: i% M* }
959253 CONCEPT_HDL INFRA Design will not open
7 k9 k0 F7 b# ^: V2 J9 v- a959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
( i6 z& x& L$ i- Z959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
; T3 |& H9 ]- d6 ^; R6 G+ U959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred# A0 `/ l- A/ }9 m: c6 O5 F: Q
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.# Z9 L8 S1 f5 i/ w5 w b$ j
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.+ B8 e) u q6 w& Q$ E- e
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
; [( x) A7 @8 V4 s2 c, |1 ^961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3& E4 U4 h7 {' b( B6 S/ r1 Y
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol; M; X! p5 N. ~ M- W5 ^0 G' \6 T, C3 o
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
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发表于 2011-12-22 08:57
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