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EDA365电子论坛网»电子社区 › 研发技术版块 › 信号完整性SI/PI仿真 › PCB Designer’s si guide
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PCB Designer’s si guide

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snowwolfe

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content
+ _1 o( `, j+ d; v# W# X) y2 `7 }; Y1 NBasics of SI___________________________________________________________________5 * `9 d2 R; e( t8 \, B
1.1 When Speed is important? _____________________________________________5
" O- L, f  b: v1 G+ E1.1.1 Acceptable Voltage and timing values ________________________________5 ( [$ I8 q# p1 g" w9 l8 ?1 z0 z3 }
1.2 Signal Integrity ______________________________________________________5 1 a5 Q  V* g8 g( S. V* j8 X$ g8 Z8 G
1.2.1 Waveform Voltage Accuracy _______________________________________5
, q  U  I* t/ {1.2.2 Timing_________________________________________________________5 5 c  {+ A! A" E4 G3 C3 T
1.3 Speed of currently used logic families ____________________________________5 5 X0 M2 Q6 F" J1 L! Y3 U
1.3.1 Transition Electrical Length (TEL) __________________________________6 . J! w4 n& g! _2 t. c& J
1.3.2 Critical length ___________________________________________________6 , N' ?8 |+ Y4 l+ }; ?
1.3.3 What is Transmission Line? ________________________________________6 / D3 R- s+ F" g8 ]# x5 g  O/ W3 S
1.3.4 What is moving in a Transmission line?_______________________________6
6 O# [: p: r& G! g1.3.5 Power Plane Definition____________________________________________6
8 G9 P9 w; w1 h! Z& X4 }8 E1.3.6 The concept of Ground ____________________________________________7
) a' J( f* n; }' {' n  g1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
, E6 y- s& L5 X4 i1 V' X% ^, m1.5 RLC Transmission Line Model _________________________________________8
3 U$ |- t# e3 T+ t; D* i: ~1.5.1 What is Impedance? ______________________________________________8
! D# R3 l: ~/ [7 O5 z1.5.2 A Practical impedance equation for microstrip _________________________8
, b) R' x  G+ q" W1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

# ~. [4 x4 s4 E+ P: v2 l; p8 E0 g2.1.1 Summary______________________________________________________10
* K- b/ s5 A( l! s$ `. e2.2 Examples of dynamic inteRFacing problems _______________________________10 5 N) C, `4 u; Y( O* H! D; A
2.3 IC Technology and Signal Integrity _____________________________________12 0 h" ]" ?3 j+ [! ^+ T# c& y4 p
2.4 Speed and distance __________________________________________________14 ! d# N1 d' C- C, n
2.5 Digital signals: Static interfacing _______________________________________15
. a+ N7 V: G' F% H2.6 Digital signals: Dynamic interfacing ____________________________________16
# a% s: Z% n9 Q& h7 f- m) d2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20
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3.1 Summary__________________________________________________________20 9 [. f9 |9 v0 \/ ~0 F( i6 _. t
3.2 Reference model for interconnection analysis _____________________________20
. n( p' W3 v. h" q9 {- @3.3 Receiver model_____________________________________________________21
- t0 s  }" k  j# t* _( k3.4 RC interconnection model ____________________________________________23 , K* _- ?$ R: X: t( J: _; w' }- ~% _3 I
3.5 Parameters of the interconnection ______________________________________25
; m) g* j5 m5 W" d+ i3.6 Refined models _____________________________________________________26 & l& D6 s/ }' w; Z2 Y
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31
4 |1 N2 v* t3 K4 N! W; k4.2 Transmission line models _____________________________________________31
: i% c; G' H6 A5 o4.3 Loss-less transmission lines ___________________________________________32 * h; g$ q" @' _+ R0 ?
4.4 Critical Length _____________________________________________________34 ) M) y3 [7 Q+ B- F3 J
4.5 Reference transmission line model______________________________________35
- d6 q+ a, A6 A, I4.6 Line driving _______________________________________________________36
$ o" \+ ~" m7 l$ K4.7 Propagation and reflected waves _______________________________________37 / J) t  X( a, H9 X' [0 W( g
4.8 A sample system____________________________________________________39
4 z0 H( ?  C+ Y" L. d/ Z" W. M: m4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata
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5 Analysis techniques _______________________________________________________45

/ U  q9 s$ Z# I2 q; ?4 V5.1 Summary__________________________________________________________45 2 N& I0 G  N4 K7 t& m
5.2 Transmission time and skew___________________________________________45
5 v) w" [5 v/ \$ N" g5.3 Effects of termination resistance _______________________________________46 ' N2 x& A8 n, L4 o; o7 O
5.4 Lattice diagram _____________________________________________________48 3 _7 u2 G" A3 O4 R6 a* g
5.5 Examples of Real Lines ______________________________________________49
) s% L& g% p0 \$ _5.6 Simulation code ____________________________________________________51 % O9 P( g- ?6 K* d; g) h* c
5.7 Examples of results__________________________________________________54 5 o0 d) }8 ~- H5 J8 p
5.8 Review questions ___________________________________________________55 5 J  \& M2 Q2 k( B  I! D4 m9 @
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6 Design guide for interconnection ____________________________________________57
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6.1 Summary__________________________________________________________57 2 \% p7 Q$ K8 ^; ~  q
6.2 Incident wave switching ______________________________________________57 7 F8 ]4 P  v: D  X
6.3 Effects of capacitive loading __________________________________________58 6 I& u" L+ a: @8 B' N3 y: a
6.4 Termination circuits _________________________________________________59 ' ?+ _$ I! a; z* G  b  j+ Q, Z
6.4.1 Passive termination______________________________________________60 ; K- h$ n: ]; @& s
6.4.2 Low power termination___________________________________________61 # Q7 g* Y% W! j6 r8 g, l  h
6.4.3 Active low power termination circuit. _______________________________61
% ^2 {# [: i" P# T$ O7 L! I3 L$ s$ ^6.5 Driving point-to-point lines ___________________________________________62 " @! h4 A9 C7 i0 N5 l" u5 c
6.6 Driving bused lines __________________________________________________64
# ^( C- d( d. k6.7 Design guidelines ___________________________________________________67 - {5 ^; U; s8 Y9 U& E- D
6.8 Review questions ___________________________________________________67

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snowwolfe

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 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70
# x2 h- V4 R+ }+ x. o- z7.1 Crosstalk __________________________________________________________70
" e" D) @, }7 K" a7.1.1 Summary______________________________________________________70
- y7 W; s: o( @" F1 t  J5 w  Y8 W; `7.2 Examples of signal integrity problems ___________________________________70 * V- ]6 Y- S7 q* L% M( |
7.3 Simplified Model for Crosstalk Analysis _________________________________71 4 A  x# g* q' t# j
7.4 Forward and backward crosstalk _______________________________________74
/ K$ n9 X9 I6 d( F* m5 q! z- w7.5 Examples__________________________________________________________76
3 E/ Z' O5 w3 ~- {7.6 Near-end and Far-end crosstalk ________________________________________80
! A& R) _' T; M  {! J5 w7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85
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8.1 Summary__________________________________________________________85 5 K0 o* _/ ^3 q6 {0 q9 f
8.2 Effects of Crosstalk __________________________________________________85 $ ^7 r* h+ f3 Z! {
8.3 Passive countermeasures _____________________________________________86 ( k1 p- n9 L3 [8 I& T" M
8.4 Active Control of Crosstalk ___________________________________________92   ~9 M# F, S" m0 m
8.5 Review questions ___________________________________________________94 7 p8 u& y* T2 Y  C7 W8 i9 O
9 Ground Bounce and Switching Noise_________________________________________97
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9.1 Summary__________________________________________________________97 ' z9 R6 r3 b6 {+ t" m0 V
9.2 The totem pole Current Spike__________________________________________97 ; k3 G9 D. F) y5 A2 q& ?( O) q, w
9.3 Current flow in the output capacitance __________________________________100   p( S* {0 K' G/ C3 o$ o0 p" j6 C$ G
9.4 Total Ground Bounce _______________________________________________100 ' ]$ }) p& {$ }& Z& p
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107 " e$ v2 f/ N! J$ w
PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107 / _+ O( r+ T* W/ V; e/ G; t5 ^
10.3 Placement of bypass Capacitors _______________________________________113 1 z4 ?& j2 c+ M& `- S
10.4 Ground and power distribution________________________________________114
' o9 d: Y  \( M9 i+ L5 Q1 D, l( `10.5 Clock distribution __________________________________________________115
% _6 ^: P) {8 Z4 X" [+ I$ z10.6 Review Questions __________________________________________________118 - Y% i& I& L& i
11 Laboratory Experience _________________________________________________120
/ ~9 L- w$ b4 z$ J, p11.1 Summary_________________________________________________________120 . M" I/ h/ ~, v! R1 P/ C
11.2 Aim of the experience_______________________________________________120
/ [9 F9 {9 S3 {, u2 H- h( y+ M11.3 Generator Parameters _______________________________________________122 . N0 g6 Y$ _$ U# u6 Q% e+ |
11.4 Cable Parameters __________________________________________________123   S7 O' O# y$ W% n' F4 p2 N
11.5 Mismatch at driver and at termination __________________________________124
: n% T+ s; H5 L+ |8 }8 s1 @11.6 Capacitive Load ___________________________________________________125
' q) L8 ?: r& m+ w( U2 b2 n1 j; g5 A5 G11.7 7. Time-domain reflectometer ________________________________________127 0 _  l8 q& ~, H( B
11.8 Driving the line with logic devices _____________________________________128
1 t) }0 d+ I3 W# r* C) ]/ X12 SI Analysis Strategy____________________________________________________133
9 G+ E+ m! G2 ^/ t1 S* S5 ~% {12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
9 u0 A1 v' g- {. d+ O2 n12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
+ h8 ^) ]" H) g4 [12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
& n) r8 b1 S4 E12.3 SOLUTION SPACE ANALYSIS _____________________________________135 / _/ f9 A5 U! X. R2 j
12.3.1
" r8 ~2 x4 u% M. ^STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135 . U, R/ e3 n3 Q% u2 a
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
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STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136 . p6 }7 H) Q: p8 o) M2 C+ L
12.3.4
0 x6 u& v! {" N, TSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 9 @  |% F# H, ~# B* C. J
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 " J3 v8 G4 F0 u* |. b/ q
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
3 Q+ T3 W% E( x- |( T0 t12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 / i% O* a5 i" Q2 K% l) F
12.3.84 e3 b; b$ K; K* R9 H  g& k" z' P
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137 * l" ?, w8 O& g' T
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
5 ^2 H7 {: j1 H4 n# _12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139   A% b" |* b' j3 V
12.4 CONCLUSION____________________________________________________139 6 O  R$ I4 s) }% V
13 Glossary _____________________________________________________________141 5 |9 m; _+ B: Q: N1 k4 X
PCB Designer’s SI Guide Page 4Venkata

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