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不方便截图,这是新找到的,是17.2的问题
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7 f! X1 O! S m3 @ {1.Close the design if it is open in Allegro PCB Editor.; V# ^+ B- [6 T/ \
2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.5 v. Y: S5 O) ~- l# i
3.Open the design in Allegro PCB Editor.
" [2 I1 ^% T/ d1 P$ c4 y3 z4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.
- t9 d" k, b9 J. f5 P- X9 `5.Open Constraint Manager. V8 U3 t/ W, i0 W/ Y3 k7 H f6 G
6.Select Tools > Options.5 s! {- d- D j5 O* n. H1 ] s5 v
7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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