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Readme for SPB Release version 17.2
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Copyright (c) 2019 Cadence Design Systems, Inc.0 M2 O9 q5 N8 L1 B% _& X
All rights reserved worldwide.( D& r1 m% E& E( k1 o9 z! v
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& d' e; y2 O4 gFixed CCRs: SPB 17.2 HF060
0 @9 A/ K6 i2 e9 ?10-11-2019: |# z! t# x4 ?5 {' k+ F4 ^/ V# a/ F& H
========================================================================================================================================================
- C2 B5 E, l- J# F1 |9 [& _CCRID Product ProductLevel2 Title, X4 A: p- w8 N k7 `2 G# O
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`9 i' D* I! p$ x5 l* W2137594 ADW DBADMIN EDM is not allowing to modify step model
# u ]. v+ `9 ]0 y! o L5 E2115805 ADW DBEDITOR 'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf
$ |6 M. D# w* F5 V, E. [! n2135452 ADW DBEDITOR DBEditor poor performance in high latency networks
1 l+ }5 t' ?* w: }2142315 ADW LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
/ e) C1 \; v, d6 z/ c8 n: e0 ^* g2155396 ALLEGRO_EDITOR DATABASE Netlist error when importing from Capture CIS" Y3 w8 K6 _/ t0 |! o% \
2118231 ALLEGRO_EDITOR DRC_CONSTR Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'
9 U0 `9 T0 ^( Y) T; [2150923 ALLEGRO_EDITOR DRC_CONSTR Via at SMD fit DRC not detected with rounded rectangle pads
2 s( H7 J* j. V8 [* i8 ~6 u2140441 ALLEGRO_EDITOR EDIT_ETCH Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab
+ r. M q5 j5 B2141329 ALLEGRO_EDITOR INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'
! [# C3 _+ m0 J7 [ N8 q3 D5 Y4 v# ?2126562 ALLEGRO_EDITOR MODULES Create Module File / Place replicate assigns incorrect netname. R) d0 f5 @" U5 u. b8 i) ~- _
2150410 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is created in the wrong folder% |* a, u5 s8 L
2136158 ALLEGRO_EDITOR STEP Update STEP Mapping Data Only should be seperate Menu/Command.
, v1 f, I+ K; ~3 X2137801 APD VIA_STRUCTURE High speed via structure instance not adding properly
4 x- G* }+ C& ]1 O- q( K d2145072 CONCEPT_HDL CORE Error on choosing 'Enable Hierarchical Variant'
+ P- N& G R5 O5 `: u# @2124843 PCB_LIBRARIAN CORE Prompt displayed for license choice marked to be used as default
2 ~* ^$ A4 _( d0 P9 v9 X% x7 |2141656 PCB_LIBRARIAN CORE Part Developer pop-up option 'Edit' for symbols displays an error message
8 B7 c- p e6 B' A2125794 PCB_LIBRARIAN SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot
! X/ P7 v) n% }% m% _ k6 M2161864 PULSE R2PLM Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error; r! M" [: G% Q: n$ X t
1997911 SIP_LAYOUT ORBITIO_IF Support keepout translation between OrbitIO and Allegro layout/physical editors
8 R; H1 @7 }" f R( b) Z( x$ O+ T; a) ~3 K
* I, {4 h6 j1 ?7 m% rFixed CCRs: SPB 17.2 HF059
9 l! \) C& |. k09-13-2019- ?3 a4 a5 O' U. m3 K' d& x
========================================================================================================================================================
# Q6 n- B) X1 }2 z4 Y% zCCRID Product ProductLevel2 Title( X! ]3 T6 b5 N H0 y% l1 }9 f
========================================================================================================================================================
7 A3 `$ m5 b; z1 I: r9 k2112454 ADW DBEDITOR Icons in DBEditor do not start applications after renaming a model
( V* B5 H% E) y1 q2120548 ADW LIBIMPORT Missing alternate footprints from vault area after library import.
' b, y) v' x( U/ K) p7 n. c0 H2143314 ADW PART_BROWSER Component Browser does not start after installing HotFix 057 of release 17.2-2016
3 o `- c+ F/ Y- P6 m: F2122302 ALLEGRO_EDITOR ARTWORK Coverlay details not being output to Artwork data as per the visibility9 @9 {& [" d4 z' L p
2135521 ALLEGRO_EDITOR ARTWORK Artwork dimensions do not match Allegro PCB Editor
q6 H c! k4 w4 p2 q2054584 ALLEGRO_EDITOR DATABASE Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top
0 D5 K1 |0 i7 N( w p2111444 ALLEGRO_EDITOR DATABASE No soldermask for mechanical holes within zone2 t6 H& H ]3 T* ?3 ?0 l( |% J% ?
2115596 ALLEGRO_EDITOR DATABASE Unused Pad Suppression removes pin connected to shape using Net_short property( I" U; W- h; n1 \# Y c1 z4 l
2135436 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline( H; P7 g0 R' h1 [
1825020 ALLEGRO_EDITOR INTERACTIV GUI ( Quickplace ) not adjusted to current resolution
. b& \& D. M I7 m% L) i1949705 ALLEGRO_EDITOR INTERACTIV Quickplace GUI not adjusted to lower resolution ~, _# M3 y1 Z, R2 \
2023090 ALLEGRO_EDITOR INTERACTIV Dialog boxes do not fit vertically on the screen/ C% {4 X/ U9 f3 k( W( s4 R% E
2109940 ALLEGRO_EDITOR INTERACTIV Quickplace pop-up window does not fit vertically on the screen1 r; o; K+ j( P) L- l
2136823 ALLEGRO_EDITOR INTERACTIV Cannot resize or move dialog box to access buttons# n5 H4 [! s7 Z
2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets0 O9 \0 `8 J5 O, F
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057
: P; ^# D3 Y( N6 O: m" H# ]' I2132628 ALLEGRO_EDITOR NC Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION
1 u) `0 D N; Q9 f$ |+ C1 H+ D% ^6 z7 R- N2152244 ALLEGRO_EDITOR SCHEM_FTB Netrev.lst is written in the package folder
6 n9 l6 v1 ^" X, `2152493 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is not created in the correct folder - error displayed for neltist import% V/ ]: A5 l. p
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
5 _2 j7 J7 a9 x0 n2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in AMB
4 M4 S' h# S6 G7 J& }7 b" c2125571 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes for a RAVEL rule
- M# r! F4 z2 J$ ]2140707 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes on creating dynamic shape
) f# ?% R, g$ k4 @, b2 }2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps2 `4 E% T* Z% @7 U5 t5 g" R" |2 ^
2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group9 X4 D, [8 ]5 m+ b" P" m: I
2029279 CAPTURE SCHEMATICS Slow response when selecting parts in schematic/ q4 m9 O `7 I7 H5 D
2039931 CAPTURE SCHEMATICS Slowness in OrCAD Capture when ITC is enabled4 g# R; U8 v0 W+ e+ h$ C0 W: T C& H& X& U# B
2106942 CAPTURE SCHEMATICS Inter-tool communication needs to be disabled to resolve the lag issues in Capture
& |* I. N6 @0 a; ?6 e- ~2131683 RF_PCB ROUTING PCB Editor stops responding on using RF - Add Connect
# m+ A* F' ?$ S$ K( }+ E. c% H2126505 SCM OTHER Thevenin Termination dialog displays resistors incorrectly
& J5 G% `: J3 B5 u2102383 SIP_LAYOUT WLP Advanced WLP Non-standard fillets not working properly: fillets not added6 l! i' Z& ^% i! b
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9 f3 s w, E: j! CFixed CCRs: SPB 17.2 HF058
' u! E3 o) } n' \, S08-16-2019
" z7 V- S. j; f4 w# i" o+ X0 y7 M========================================================================================================================================================) g( Y" R7 L; |8 o1 n. T
CCRID Product ProductLevel2 Title* n& `8 a3 l* t4 D N5 J! ]
========================================================================================================================================================* Y O0 X& E5 I e
2113265 ADW LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem
4 S3 _/ x" W, \7 J0 o2122941 ADW LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time7 L! B6 c$ j6 p9 M2 c; v2 i' d
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)2 P! M* q$ G$ u; f( X% G
2107578 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas shows split layer9 p, q9 X+ j" U: c
2099538 ALLEGRO_EDITOR EDIT_ETCH 'Glossing - Via Eliminate' shifts traces to another layer+ e& G" v" R$ l8 ^' [4 b$ B j
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: clipboard origin point is not set correctly
; p3 E% G8 p' y* b2100433 ALLEGRO_EDITOR INTERACTIV Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees k4 i# B$ M- D7 s
2127239 ALLEGRO_EDITOR INTERACTIV Exporting a query result changes the working directory r/ L# p, X g- |
2117160 ALLEGRO_EDITOR MCAD_COLLAB Error encountered when importing IDX file into MCAD tool in HotFix 0568 b" z! K0 B4 x
2117427 ALLEGRO_EDITOR MCAD_COLLAB IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)
5 L3 D8 y, a1 Q- d) `2117839 ALLEGRO_EDITOR MCAD_COLLAB IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools4 Z+ u, l3 c. p1 S; f
2118019 ALLEGRO_EDITOR MCAD_COLLAB Export IDX is not working in Hotfix 056 but working in HotFix 055
6 Z: C: B; E# w2 L7 A# l2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers8 C7 e. R# E; P6 E: q
2126766 ALLEGRO_EDITOR REPORTS Cannot generate reports and export ODB on board# l1 O$ e3 P& T+ O3 ~
2107849 ALLEGRO_EDITOR SHAPE PCB Editor stops responding on updating shapes) V# u2 ^) x# |
1778109 ALLEGRO_EDITOR UI_GENERAL Constraint Manager exits on doing 'Undo' in PCB Editor' i5 D1 Y0 a9 B( W
2064092 ALLEGRO_EDITOR UI_GENERAL Allegro Constraint Manager closes on clicking Undo in the layout editor: H, |% ? Y. K$ k( Y( ?. {8 C
2093341 ALLEGRO_EDITOR UI_GENERAL Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs
$ U! \0 e: k3 B, B2110909 CONSTRAINT_MGR UI_FORMS Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.1 e8 |3 t5 w# R x1 I
2096846 INSTALLATION ADW Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
6 e4 Z3 Y( T% y+ j1 S& Z: |2128118 INSTALLATION ADW Unable to connect to Component Browser.
( U; k4 U4 Y! A0 M2116749 PCB_LIBRARIAN OTHER Cannot open Part Developer with a Venture PCB license (PA3810)
% S" f8 j- B8 `; y; g9 |2115302 SIP_LAYOUT IMPORT_DATA Performance issues with die text in and pin use codes, function utcle pwrgnd
8 E) a/ C5 U- f, ^' r, s* _2103784 SIP_LAYOUT MULTI_USER Symphony Server rejects the move void commands on a specific shape instance
( M- m$ T5 _7 W/ j7 Q- y) S2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file9 k U* L! T. S4 ~9 \) k @
2117572 SYSTEM_CAPTURE EXPORT_PCB System Capture crashes with multiple Export to PCB Layout( i& L" `- L& [0 L0 m: ]$ X
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0 z5 k3 @% S) V6 s$ Q- ]! VFixed CCRs: SPB 17.2 HF057* O/ A+ j4 Q' L
07-19-2019
* E x" H; g, w+ l! v; _* M. C========================================================================================================================================================9 [5 m. O+ S- L- ~! z2 ~, W
CCRID Product ProductLevel2 Title- j( N: i5 P5 w6 b
========================================================================================================================================================- ~- C: W( e1 b1 w, z
1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file$ B- k1 V, k* T1 i$ b% i$ X, s
2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names
2 o" k' z' J9 O! j2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
; M0 u) }7 }# U a+ y# r& C5 F2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected8 I- ^# N, N3 @! a+ {
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
4 E3 o7 n# [* L: Z1 ~, f2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
! c: F: p$ |# |/ |+ e! p, n2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash
9 `. b8 ^' U% Z j9 W2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board3 s5 {, `* Y b! j | n# v5 E& ]
2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony1 y& q* {* u: b& |# V: T. j
2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server
) \( |6 s, b* D. x2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections
% X) d; p3 T! G. A7 p" L& h9 c1 N2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report! c9 R% O% d$ J* T0 j+ _; e- _$ _
2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report
8 j+ x& ]4 D# r1 |- j2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error2 z# l% v4 ?1 `# ?8 @ K+ E: n6 Z
2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information
7 N& L w0 H; b( B! e ]1 z5 A2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board6 U# t/ B c, r7 O* ]5 ^+ `
2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning
; W3 C; p: _9 C {. C2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name
* v; J3 x; Z/ {$ ~& c% Z2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form
& h6 ]: y& l& p7 t, P6 W2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data" u9 W* \2 J q: k4 ~& C: f
2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part/ f! R7 b' R9 y4 @) m6 a
2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working
1 T" `9 S* b. E7 [7 [7 H8 K0 W2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager
% V0 e" {9 }( |4 A2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block$ @8 p; V+ m& C6 F
2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save'
* `: b' f0 v9 a( f$ L/ i/ K2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 0536 f7 K" R" w6 r( E9 C3 h5 `
1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
0 N' @2 }" T! O1 [5 F2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file
* t9 v! C* R) x% U( _2025997 SCM TABLE Copy-Paste Broken in Physical View
" g, i2 g2 d7 A) E, {" X" T' l; x u2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel3 [& O7 s% l% o# Q
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences
, p/ t- Y5 y/ _& d$ ]6 R" E t2 r$ I2 w2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow
) s, U- s' N7 C8 }/ C2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL4 j! ^' I* B" `
2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
7 Q+ X8 _" H0 v9 b2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
3 ~5 n7 M, Y3 A0 I2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 055) ]6 a1 T0 N1 v
2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect
: \8 X5 |" G) t# y/ ~
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Fixed CCRs: SPB 17.2 HF0567 r# I- }' ?; n- v! v
06-21-20190 ~9 N- e3 ^, n' B
========================================================================================================================================================
0 x9 F1 J) R- P0 M1 P2 H- XCCRID Product ProductLevel2 Title
& j8 Q m+ R1 }5 L- j2 W========================================================================================================================================================( a- ^# s, w9 p7 Z9 w& U
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
; ]9 h3 \& P3 r( B) R' b2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip
. I/ s D3 b% {5 H6 B3 c! R2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding3 B2 Q+ X- [9 U+ U5 Q5 I8 y
2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash- @0 [* r2 t8 Q( o" Z; E5 T* Y% j, c
2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file
; R8 ^4 m7 q5 p2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
O9 Z2 {8 [1 K8 _% ^! b* A2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features
) Z! Q1 c: H" C' h- t- W3 f2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time
' f6 r& v+ `+ h* O, w2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016- h3 U8 |( `2 i: x
2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs! z7 d) A8 l F/ N
2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
! u2 s( h" ]7 @- Y; o2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded9 K" p( W; A) z' q
2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area% `% \/ U( H% q8 |
2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component& ^# @; b* X( V0 L! o1 @: A
1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance5 V" w- ^" H- {$ r: ^! b
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
8 b& s6 }/ k# m3 w% ?! c2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words% d% W& U, \* x E6 A1 q$ M. L
2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import
0 |* C* p4 o; A# R+ {2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check7 K8 B! G1 [" `) s
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
$ m& Y2 p3 w8 z4 U7 n/ |2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer$ \) x& H8 V( a$ e
2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained
7 @0 ] L& V: x, }2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane, ]! D! B6 l8 `3 K+ e* w3 {/ a
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters
8 h2 e/ r- p) Z3 R2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.
0 F: q2 {. ]- A$ E# d2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database# Q$ ?) L Z# {$ W- j
1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value2 q! X' e9 S/ |+ d0 s" O( D7 e
2081363 APD DEGASSING Cannot degas for specific shape# d1 W8 ~. [7 m- J
2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component
/ C2 C: c- ^1 J2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.4 }+ \8 B: t {( ?% d# s7 Y7 J
2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
0 t6 s" a" y! e1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor! F5 _( o5 M# P. R# t- {% D
2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode
, v9 I8 q' f; q' _, S! _2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears; P- e% l& } H% D3 f
2076282 CIS PART_MANAGER View variant does not show pinnr and pinname6 a7 X$ E1 s4 E
2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts
& R9 Q `* e. {; x, W* o2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues4 U& X4 h; ]7 m8 E8 F4 Q# I
2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
0 v6 g: ]# o+ u# I& P% M1 I1 o2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB
J0 L, ^9 {+ i; |8 c2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor
. B; T, u2 R; X' f1 h+ {2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor' F$ B9 Z0 d: A9 ?3 f
2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes
( h& T" a3 A/ a+ r& h2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics: B+ U5 k9 E( Z2 Q8 Y5 U; p
1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project
" E1 Z* b: N& x9 ]! E. ^$ U, e4 Q1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash.4 Y# s `% o8 c/ ]& F
2035572 PSPICE FRONTENDPLUGI Crash on archiving project
# Q0 h: Y8 S: \0 k2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global.
9 H3 t- B `, a0 q ^" I# M8 p2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053/ F9 q% U; ^6 s0 Z8 _: u" L
2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project3 S {( |; x4 l; H1 \1 E
2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source9 I5 k5 j5 v! O, p# m$ B8 \& W
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed7 }' e$ Y9 }) A
2094548 PSPICE SIMULATOR Model undefined error on TL494
" w. X% P6 @. U9 `: ~2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
, z, G! v! E5 }8 H* p2 a2 S1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS R0 B4 M1 b7 N
2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes: ]: ]5 w f1 [( s0 s1 G: Q1 K9 m+ U
2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
$ j. M$ f- S; A4 z
, h. z7 K2 | I. ]
+ U$ ?( F& l2 Y0 c) k& nFixed CCRs: SPB 17.2 HF055& [9 u6 [* Y+ p& Z- x
05-24-2019
' Y# l# i* v- h6 M3 W3 |========================================================================================================================================================5 H, A8 F& B. f' a2 |0 n/ c
CCRID Product ProductLevel2 Title
3 K+ r, E( W" w) F( ~& ^2 G========================================================================================================================================================
6 z+ Y7 p7 J, ^' {) K, j# _3 V7 e2078057 ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server
) x0 f3 p3 G6 Z: u% }! V$ ~2092863 ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview r, _0 d/ I, V# {$ w
2076339 ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053- n: w, ]9 r2 k* N2 u6 g) g: ^0 w/ j
2051075 ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor
% |2 P5 k( v) L6 g3 ]2073407 ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes
# t3 @/ Z9 x, L/ Z( G# h2079117 ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014
( U3 E" f" p9 G0 d8 J2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
9 X7 Q5 t* r r% G* O+ @; h. C2082394 ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object$ i, ^. K2 c5 M5 r/ X5 h1 e* _# q
2067916 ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
1 w, F2 t, o" i' e2068449 ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016
' \, f/ r- ?$ Q( y# j+ x+ U2065820 ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import, @) e( v/ d. d) ]4 n
2080164 ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks9 W) l) l" f# f# K
2081955 ALLEGRO_EDITOR NC Artwork file error for via size1 u$ Z( a6 j( x8 f& G) \
2045061 ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does1 I2 |/ I ^ u( T) y. z
2049949 ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import
6 }3 }& i+ c( N$ G" a' U( a2069289 ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)
1 c4 q% H3 G+ c z/ P3 w2056573 ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on. k+ a$ l& ?. J8 z" i& l
2076452 ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected5 R" K3 G" g$ O6 V
2076873 ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file
1 h) [- q0 d, m6 H: Q1788703 ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used
' n7 M! k& _% u p' `# O. d6 C1955127 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
2 `- a& N( ?9 Z2031711 ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup
2 `( ]# |4 b+ U2062527 ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager6 \, x3 Z/ _8 |( F% \
2074249 ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected0 n' [( B; D, [# R
2070534 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database% ~6 ?8 l5 i* O2 r d0 V$ Y' i
2046278 ALTM_TRANSLATOR CAPTURE Third-party import fails! j4 m) a f/ b4 T3 T/ c P
2052399 ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message
4 ?) U( ^# G& J* D$ ^2005087 ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL
5 t8 p* H5 D( j) i \1922222 ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets5 M$ I8 n c, V, y5 N7 T
1987263 ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported
) f0 o; K- K2 r. _$ S5 Y2017988 ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy, `" q7 [6 s7 y; R) M2 f# }5 K
2021300 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas
( m. @; e. u& {4 Z" a1890675 APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file+ Y1 O6 o/ m% S+ M
2064219 APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
% w1 B' L7 ? Z7 g% i2086574 APD OTHER Duplicate layer text shown on the vias
- H, T: q2 O6 o- Q: \1948169 CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders
" d; W/ H) @3 ^" ^# e( i2025385 CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols9 O& a6 F8 R! a" H
2050010 CONCEPT_HDL CORE Copyproject does not properly copy the variant files# C% W* ^9 {" J! I
2063457 CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems, I, t, i$ u L) J. Y. ]# F
2076312 CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants
. _& y, ^" ^9 M' H U2083650 CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on
& n6 v+ Q% y: ]( }+ D2083651 CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name
& ^; W$ K, [+ \4 y H% S2056736 CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open6 L; R! {8 m5 q3 l! r5 Q
1955357 SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license
9 _* {; w) }: \0 M3 t |4 j+ ]8 g G2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
3 N9 p4 @6 }; e3 s+ P2081884 SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections# ]# C/ K! X& c) x! H2 ?1 G
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks; ^, L, E4 x- ?+ m2 I$ R- \
2071303 SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
0 U4 F" d8 ?& ?/ y+ Q( d( |" a2058979 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file# Z! F3 y5 o5 m" t4 B$ r. G
2088210 SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted- G7 O5 [% m5 O) i4 |$ n
/ |) ]2 ]; K& _) c- l# f
. A" \$ U6 M6 G" N" rFixed CCRs: SPB 17.2 HF054
" L" P( b5 V5 E* _% l2 j% H* F04-26-2019; M& z# D) o3 s* W) X, z
========================================================================================================================================================/ T& n1 M" v+ N/ V6 b
CCRID Product ProductLevel2 Title
! y" S/ f: o" Q4 P+ [========================================================================================================================================================
' y' i* y9 ]( k$ P( i" k4 t2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes& _& O N# ?; D* f" j
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
W! b* U7 Q3 s! n4 S9 M- d; I* Q1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser6 D5 a$ J- b: q- q2 C* p- Z' T; a0 H
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache) h5 ~' h- ~8 @# ^. ]
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name+ }! J! S$ H2 t
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design5 k3 \1 ^# _& w5 M; S
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
7 B. i- y" E, h; `5 Y& N2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
# C6 n1 J. O1 u% Y2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
. a# W8 i' P* l6 j4 r2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded- W$ V& {$ z6 \
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off0 b! x4 q2 H( U! f- l3 D* n
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set1 `" l6 ~1 j6 n2 B
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
& Y6 t( }$ V+ i8 r5 n4 f2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements8 F2 d5 f' W8 u. R( @, i$ M$ v& E$ i
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin3 y. p& [1 ?/ L9 }$ V
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element" n" t1 @8 ~1 N/ d
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
1 K2 \7 L8 N6 v; b& B& z% m2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error( e5 r' z' P( }1 F
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
5 Q. B5 u' V/ E7 l& N9 S2 D2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016& S! h4 ~! C1 S) p
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
: v; K/ s1 M) L0 c7 |( O2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets& e/ m2 o0 K' J/ s0 O; l( c( |
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File., Z0 P% W$ e* g4 f5 l& M& S6 Z* t, l
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
. ~) I5 W9 f/ V! ^! _9 ^2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
2 N6 }$ `6 j1 Z5 q2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations" m X& g: E) F' J. ?# Q
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'7 p3 O" ^ @: I' }; o; F' d
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
! o+ J4 J4 q8 p, k, Z& E2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
X3 f' o( Z; l* C: b2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
& i" b/ x2 C3 Y2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
" P' X3 R* ?( e7 @- J2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor% R* j! J. l' y0 l
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
" W9 W) j l7 C9 Z2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components. N) O" [7 `8 ~
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report' z8 _$ K; @6 L' f' f6 V
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL. T" E% l7 C: s
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window9 }; {4 v) n3 O0 K
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
( ~7 f$ e4 L1 H0 b- ]- ?$ s: e2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
* Y: ]7 P9 y2 b' `2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape8 t6 y2 ?0 E( Y* K
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present8 p* ~; t% {8 M* c7 w
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes# ?" F' s% O% _, C- P) X+ H
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
: g+ v1 P' s0 e6 K- b" W- n# I6 d2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.; \+ |( K$ I9 p; K
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash2 U4 f; U5 `; E0 _) G" L
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected., p) w- V' U+ T* }5 f# Q6 v; e& M
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New) {) u5 N# ^; l5 Y3 ?4 v$ `
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
+ ~) l h6 J9 E# U' V2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
# x2 d9 r( w, j7 k2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design) V% }( @1 A7 j B
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas( q6 W$ }$ {5 `4 P4 Q
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice# d( r. D( l2 M% b
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
+ ~+ r% B$ U9 a+ z" B. c$ v+ f2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden6 X) F+ C1 d1 S( n/ F5 N
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.65 D) c- W7 W( r/ M+ e
2050674 APD PARTITION Cannot remove C-Point from a partitioned design6 M1 l( @+ ` o* [) o# w& g& u1 Y; z
2068814 APD WIREBOND Bond wires cross on auto-separate2 {0 O0 B5 W% A* ~8 [7 x, Y
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
# }9 K1 R. d( f& `% `: d ~1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
" [! o! I# f& b: X( n! U2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
8 ]. O- I6 |7 L& b2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
/ W1 h% s% x' z# Y6 |. d8 \2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
+ l2 ~9 p: a! f+ J t2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
" @# f/ m7 g7 m, |, Z( r( T% Y% }2 j2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
( B* ^9 c7 v6 ]/ I5 i+ y2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
& C/ N1 ]6 z/ D' z; o2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
) f2 d' E& i( T5 e1 [% f2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties4 X. x1 Y9 Y( w+ k
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.4 K, }1 ?1 n6 v7 O7 i( c4 T* ?
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
; M# M' t$ V; ~& K: ?8 K# Z5 ^2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor$ g6 ?" |3 ~/ Y" k
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
0 l: J( `/ n/ E& a2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
1 O+ B& e2 A0 E5 U/ ]1 D4 H2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
2 v. T: ^3 Z9 k2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
. o+ _3 ?6 ]' B K! k6 o d* K5 }2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
6 }6 @9 J3 u1 A; p* g- _2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
i* \2 }! k, P8 j1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated0 y7 J- u( L3 L
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
4 C" W7 D- H1 R/ C# V& \; Z. _4 m2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
- E; I4 @" L) ~2038021 PSPICE FRONTENDPLUGI Bias display is not updated
t8 p9 V3 M& B+ h2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
" @; L& \+ [& Y: ^/ e0 `2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
' [7 e6 T) S. f0 l- z0 F+ \& ^2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks, r8 U& H+ J$ J% ~* Q- P* m* X
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.( Q- X+ Z' Z$ k9 ~7 q' U
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
( \; T# w) j3 T2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
& c3 t/ m! ], R: ^6 ?( w- o2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
* _8 M# B5 q+ v2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052$ a8 W/ P# F7 ^, \3 S) S9 R6 |# m. J9 \
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
9 c0 }& m+ t* j! ^0 K1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
" E) N! A% J l# E4 r2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
) V1 S8 Z" Y- C, M$ A3 A1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.* p+ D9 D7 C1 L2 E
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session8 |+ l( {8 F; |! z* n# ~/ o
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
+ p( z5 |1 i8 p* @2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
# X% I/ k& I2 t1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping2 k4 Q- U! s& `/ Q
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
: D1 d* y8 G) V9 v1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
6 I# T& w" ?2 h9 E+ C, C9 u$ I1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
w B, ^8 x; f1 ?! Y1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM2 L6 h1 ~# F; u+ b! w
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
7 f6 A7 A5 q8 k9 X6 ~6 a; z3 i, `8 j( }2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
+ O5 y' ~4 ?& E4 }9 U# r2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
4 L( D( f! e6 q# X; E: i4 A; N. T1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space( ~& d; _ [6 `/ [$ s1 a
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number4 c4 s% w. Z& Z6 N, j& w
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project. n" y3 v- d( a8 B; M6 g5 ]
7 i6 e5 ^. d9 ?# ]& u
$ N$ f s7 E8 U5 S
Fixed CCRs: SPB 17.2 HF053
7 N2 ^! t; A y03-30-2019
6 e1 l5 q) v7 W' O9 ?" ]========================================================================================================================================================
) G$ A+ C2 M" c! K: r+ i) HCCRID Product ProductLevel2 Title' ], C$ [1 }) [1 f; k
========================================================================================================================================================/ o9 ?% G+ O: G9 q* ^: B, p+ T G
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right9 m2 u, G5 }# A+ T8 p. `
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag4 T# P; U8 R+ A# N
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
; |) g. |* k# k8 G. O0 b2 Z2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design: F( F3 ]5 X- ]/ b3 @
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error, |# m( v3 F* ]' v& L _+ r( b5 i
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
- _. i& v1 N, S1 Y E. K2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer1 n9 Z2 G! W/ ~! v
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down+ q( k& M6 g" D5 [6 L; S
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction5 M& z2 K# V' H. s
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
2 w h0 e( m2 S0 j- Z6 [2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned7 i! t; F; c7 ~" n! q, ] K1 q
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
8 F- O( o9 I& @$ C2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone3 `) e8 r8 Y: h/ Z r. E
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.7 ]3 `: p, X O6 q9 n
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
0 ~( C' G2 P! l% j( |. Z' n2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack( \( ^% o; u0 k* u4 o8 `$ _! u1 I
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
' M8 d v2 W t. e1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
7 [4 @' _9 W1 h4 f/ X: s5 ~1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.: A2 i' z( l; M4 J
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
& t0 n. B- I& y7 s. Z: ]7 G O6 M2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.- \* \" }% P' F/ Q# K! S: Y
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command) A# Z% k) @6 l y+ C
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation Z8 y6 ^& e$ b& {( s- N
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design" ~ y/ v/ _; C& h, i
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
0 [& n% Z! ]# v3 I8 _# J2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.% T3 q/ _/ ]9 Q* |" Z
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
9 `; Z5 X6 Y& {0 R; q2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
! s0 ` V0 y$ v0 c, o; g) S2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
* I1 x7 f' x& g% f+ P% S2 |2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added4 {3 Z; ]: Z, ]# s8 D/ f" n1 k1 w
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created( a% t! ^% }4 _; B+ n" H
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
/ f2 y0 Z$ A4 R$ o9 N2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point+ N$ K0 U, i7 j9 m9 r3 s5 s0 `' y
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding# j9 \9 C6 E' ?: w4 ^% Z% z
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
/ X N/ z% h9 S1 U J" \2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
9 a, C. E& E+ T! g2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
: o: O/ v: d! L; h- z6 D2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.# q/ L A1 t8 Q5 n
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash" u1 B' P. O9 k
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint% {0 j3 o+ U" S
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
9 @3 _; |1 b5 f* \2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash; w+ ~$ B2 a/ Y7 F6 e0 b) Z! Y
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
/ d6 w7 m8 P0 H5 \2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden0 h, Y- _0 u, X5 C; G
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
+ J. P( n! u. b% `. J2 \# C1699433 APD EDIT_ETCH Field solver runs when not expected
% e: |: Y: F3 E1937159 APD EDIT_ETCH Routing clines takes long time/ r7 n5 P, t2 t5 C, W
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
+ s, c. P+ c/ ?0 m* |" p2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051 M, l9 ] Q! D- ^6 ?. N( Q; p) h
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
' ^7 a @1 q# W9 J6 ^+ A2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
: r( h& K4 M J L& G2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
2 `. H( l( r+ Y4 ]" E4 S2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
( d& f% w- w$ Q+ b2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM4 f5 ~5 l" {) C" h7 ^
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
& W# x' h$ ]6 ^! `/ D2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
. J% W o/ G. f& Z5 b$ |! L! j2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
% Z8 m% R- w. x3 h2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 ?& r' n: y6 y
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library! `/ _& x. S- |& h& {3 t8 ]' j, d# J
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty( u0 y( e% H0 F8 F$ @! @4 U7 \4 O
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error7 a7 W1 c3 Z5 x" S
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
+ z2 k# r9 y$ {; B0 E( N3 y& i1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components, O8 ], P- W' V4 ~) ]6 x, I
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names+ b/ G4 N0 `8 u2 w6 I& p
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character3 E+ y8 B" o- m6 B9 J
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas! {- _. E! g+ l" m' P
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option8 c* y/ h: B7 J2 B7 X" g, c# c
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped* m* }) J+ O' R/ S# o5 b6 \2 I
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical8 L8 \9 ]3 r, _3 W9 h' i6 R5 ~
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
5 P% g, c& _4 y7 T {1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas# u1 w! [9 `; P# `/ j8 @9 q1 O& l
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
( C4 r1 g1 p4 X) k# P1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast+ O) f7 A" `: i) z5 w" _
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently) d4 B# B: u! J) n2 ]7 z
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
^$ s" f& n0 J. Z R" D% ^1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI+ C, e5 r; `( j
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
# j0 `$ `' o/ j/ m/ }' ]2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
4 n% U/ @$ A0 _+ |6 M1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it1 W% e7 I. r' j5 j4 l
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL9 m2 y9 l, c- M5 c
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
7 Q5 H; i' _2 l2 D. d1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
! u) E( H3 |/ }- i1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor% G" s! P. B n7 |5 g# n
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
/ }- K5 l+ I* U1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
5 R0 [8 N; j' [7 S/ A/ v8 o2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
+ A) V7 W+ Q) ~* X1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES7 ^2 h7 W; M2 I; Z2 r1 {9 w3 C& C
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option4 X3 n( v _' A; \4 S. Z
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
: h D8 t8 i0 N# r
: V6 y8 H* Z4 F* D" D! \, ?: z9 x0 g# g7 g. w+ i6 A/ @ \
Fixed CCRs: SPB 17.2 HF0529 D! Y8 m# T8 ~# u$ {1 u# z
03-01-20195 p& y/ C1 P! ]* A3 S1 ~; ~
========================================================================================================================================================/ x- c" Z1 q! b# k4 u* A
CCRID Product ProductLevel2 Title. v/ [/ g( F5 Z/ ^; B/ t0 m
========================================================================================================================================================% H$ t; a s, [7 Q) y# u6 Z
2020429 ADW ADWSERVER Incorrect adwservice status on Linux' a( F$ @; O. k' t* L8 S. d
2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database
4 e* C# ^: J; }; K1 ^2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005$ ^" K+ C) Q6 Q" T; R% I2 ^8 z% J
2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data; M3 }( ~$ Q) P4 F/ |) F
1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.9 d$ g7 @; n; k& n1 X
1992662 ADW TDA Custom directive added to the cpm file not updated after check-in
4 ]9 H/ X' w" S1 S4 I% U1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol
, R$ o: W) n d3 M! S1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility9 W% j. I4 m- {
2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode0 m; h. o; p2 t8 Q' o: G# w1 l& G4 U
2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file
2 T; T3 D0 F7 g8 [, `3 P- \; e5 ~1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned
4 _& F' K5 Y: y* s- t1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area! g6 L: e6 @* }+ F; e
2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically
0 H; u. D7 _) l0 S3 P& w6 l% q2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color( P& J! \# n8 ^) ^" I- d
2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design$ E0 j; R0 r w- Y
2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog0 k0 \ q" r( r- |
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing
: K1 |7 I2 u: v! V2 Y" D* G2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request8 d( t' j8 `9 R6 @- b. _' t4 R& D
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request7 o. m4 _ k7 O! Z
2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router/ ^. s& B4 _( N |+ @$ G" C! {
2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work
# @+ i$ P u- h6 R6 r7 M& L1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
# {* G7 j4 Y4 e8 E/ p: e* C1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides" I3 \# D" f! \' s. J, {
1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide. m$ q% U9 \. q7 Y, s( W
2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint* M3 t8 a+ h* f, }2 a: G1 T8 T
1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file- L* p+ E* x. W' U
2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.+ O F* Q# w7 v, Q, |
2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol
$ }; P: T0 N3 P& O/ @* ]2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.7 |) z8 f4 u- z) P/ Q6 L1 a
2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor
# k! E! P' s2 {6 }/ c2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round/ @0 X/ k q( K: `& G
2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary
6 K1 q h8 x$ Y @( }' n1 I2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline
5 v- F0 Z) Y& y* `' J2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.& G4 o! p% y8 [( j6 m/ u
2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer
$ a1 x; m4 F' b; R2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 0489 M/ J2 p. c0 V) M1 a% n
2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 0486 }! T ~4 q0 H: c; t; q
2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'
( w. |! Q) v9 @2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description
) E. N5 A) m2 h3 _* u1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor
2 F7 @7 e5 p3 B- S1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode
( V6 ^8 O, m$ c1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.
q* U6 w3 I3 ?8 d% Y1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options
# r# d9 A" A; B/ } H1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box
2 m* ?1 M% d- b1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI
+ K! T7 K$ a6 ]' }8 {1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU4 P$ |/ j5 E5 T: q$ d I+ [- o
1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list
* @1 q8 f8 W4 T" V2 p2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set
& z9 `, L5 Y9 y& N U2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048/ K K3 o% B8 `4 R+ _. _, O
2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other
/ o; z1 A# U! f5 Z9 I2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path, S, g, F. v9 p; P5 j- a! _4 G
2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board.
4 P' {) `6 i. B1 x0 F% n2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements.
" [$ g+ u7 Y% k+ p2 ~3 Y) v/ u2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work# V* a9 c" ?5 N; s2 L
2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box- L' {# A& X) e" ]" }7 [
2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture) E2 A+ o4 f: \. g* P; t5 _
2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
# X: u- E$ E5 L1 A* ~% o. F2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet
2 ]$ |1 ^3 G. O. p2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 048, N' q+ j0 S! B
2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy
! u9 a+ a6 X, O2 X5 c7 y2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-20163 x: A. t. C3 v: h. B
2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations* F! L4 t i+ l8 D9 o: q5 O( r
2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
/ x, j+ B5 R8 T- Q( o0 G2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session5 B! x/ D d: p# u# m) j5 ]% L
2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance5 {, w4 U6 z+ |, m
2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure' Z2 s0 ^6 P0 a" r. \
2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding.
3 z6 |. X- s# f: O3 H2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
( m1 t$ a: w- [% S1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas4 L( ^ [% {0 [0 \
1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction
9 x7 }; W8 e- T2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command
* T) w2 G! e2 O4 \1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol- Q4 ?$ @7 M5 Z0 O0 r. K
1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
7 m( {2 z: I( y% J$ K3 X* Z1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out
' ]' `# x* H5 u, m$ u( S2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design5 Y, z/ k! u3 X1 B7 s6 f" T
1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas+ [5 k/ c/ ^, B
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
$ R* A9 l/ N6 x: Q2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit
9 R5 @- X3 x" [% ^) P, P+ Y% c& U2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%
. L6 S8 f5 ]2 W2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.5 Y6 ~, r# S* ~( S& y
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
4 E+ o! w) M: _3 p2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols
! J, J+ X4 C, i" ^% ~& |2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation! U8 B8 Z2 _6 M$ D
2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS0 C( R* C' {+ B# |0 A7 ]2 a
2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases
W& E/ h% z; X1 _2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors
X; o8 l1 b1 O, l8 a2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly
+ z& v1 f% U- f; i2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.
/ B( H8 R D% L2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants5 P, V& E6 [/ a$ G( d# ^( O4 T
1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace
5 @. t3 W% q M; s" ~! ~, \" U; i2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake
' j" A- S5 Y$ ?( Z% I' ^) h1 E8 Z2 B# t3 R: U
+ a1 i$ E1 k9 c6 D
Fixed CCRs: SPB 17.2 HF051* M0 Y. b! h7 p; b3 @
01-30-2019
+ f; }: t" k* t1 D; O========================================================================================================================================================) j2 A& p# x$ o5 b& c' G1 ^" N" h! ?/ C
CCRID Product ProductLevel2 Title5 p. _# s$ N/ W7 \9 ^' Q2 T
========================================================================================================================================================
- n% l4 T9 ? O: }# c' q" Y) F: j2015843 ADW LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range& j8 M/ p$ a3 E+ w' O
1869914 ADW PART_BROWSER Adding components to System Capture schematic canvas takes long time in Linux clusters* U. }4 }: |5 i8 h& _8 g' _
2010458 ADW PART_BROWSER RefDes values not appearing on parts
& U: M" W3 k. s/ y4 J2022630 ADW PART_MANAGER Unable to successfully import a DE-HDL Design into System Capture
W' D+ m: [% N, H, f) G" ~2005033 ALLEGRO_EDITOR 3D_CANVAS 3D Flex issues: Error message when opening design with bends in 3D viewer& ~/ D$ C! i; |1 o3 @8 X
2023496 ALLEGRO_EDITOR 3D_CANVAS Error for designs with bend in 3D Viewer
; T6 q% Y/ s1 ~2033459 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
' X( M1 b7 x q" C9 A! v& t1996431 ALLEGRO_EDITOR ARTWORK Via holes for connection have incorrect coordinates in Gerber
$ h' P7 X& P7 E& P1995656 ALLEGRO_EDITOR DATABASE Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file
4 a' ?2 a6 }1 Q: N: p2027122 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating Place Replicate module
) L+ K/ c( v5 o0 m* a2023916 ALLEGRO_EDITOR DFM DFF Annular Ring: Thru via pad to Mask violates on via in pad instances.1 N5 R" s3 N0 g5 B
2024523 ALLEGRO_EDITOR DFM PCB Editor crashes in Mask To Trace check of DFF.( R7 [: {8 T. J) T/ O1 |
2021318 ALLEGRO_EDITOR IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow
: T' B4 Q" i Q8 q; \; p- G2014162 ALLEGRO_EDITOR NC Backdrill results using an OrCAD Professional license showing wrong values with hotfix 048/ F7 R, U' B5 |5 Y+ {" o7 Y
2010791 ALLEGRO_EDITOR PLACEMENT Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset
: ]. i K/ g' P5 \. }2017112 ALLEGRO_EDITOR PLACEMENT place_boundary shown at wrong location when moved with User pick and footprints rotated
7 }8 p, l- S0 F' N2028048 ALLEGRO_EDITOR PLACEMENT Rotate option using pick is rotating the outlines in different axis in view0 R7 W- f+ @8 o- d
2028314 ALLEGRO_EDITOR PLACEMENT Crash on moving components in Allegro PCB Editor
) V- g; Y) G7 z8 Y2029235 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component and hovering on IC
9 S f" A0 f" ?; L% _7 A5 o2022644 ALLEGRO_EDITOR SHAPE dv_fixfullcontact obsolete in release 17.2-2016 Q& R; b& b( R! E( s* }6 x
2023322 ALLEGRO_EDITOR SHAPE Gloss does not add teardrops on all clines.
9 E$ A/ ^0 A D2024235 ALLEGRO_EDITOR SHAPE Copper Pour disappears when area includes parts- c0 T6 X ]6 R* x+ o5 l# e R
2024531 ALLEGRO_EDITOR SHAPE rki_autoclip is not working at a special XY location! z# M# |# F- `, _5 I0 S- Z! |
2024599 ALLEGRO_EDITOR SHAPE Cannot create round corner for shape0 ]% E* }! z6 u; x9 Q
2024707 ALLEGRO_EDITOR SHAPE In-line void control does not work when there is no_shape_connect property attached
9 [- V1 o- V0 N' F0 n2026849 ALLEGRO_EDITOR SHAPE Cannot assign region name using the 'next' operation: ~4 [ Q+ |4 D L' A$ C: T2 p4 F
2030156 ALLEGRO_EDITOR SHAPE Shape Area report for cross-hatched shape includes hatching and boundary
# J' y9 s+ G- T8 ?& y5 J1852981 ALLEGRO_EDITOR SKILL Error message while creating Copper Mask layer without a name using SKILL not clear
) {- n0 ^0 O4 b$ ^- P% d1968054 ALLEGRO_EDITOR SKILL Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net
' o" w3 s- w, \: e2 E2026429 ALLEGRO_EDITOR UI_FORMS PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image, z1 j% N; ?* T m: \$ g
1768032 ALLEGRO_EDITOR UI_GENERAL Numeric keypad does not work for file selection shortcut
" y! F% C% {6 ]" K m4 C. e1797376 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used2 d) ^ a1 D( m% x! ^9 I
1798524 ALLEGRO_EDITOR UI_GENERAL Unable to save a padstack using script
T& g/ Y% X# P% Y" y1823031 ALLEGRO_EDITOR UI_GENERAL Help not working for OrCAD Productivity Toolbox
3 i* c: v# e7 U# ?1849921 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI& u, I4 V' x4 h! _+ T2 Y
1951740 ALLEGRO_EDITOR UI_GENERAL Trigger for 'open' does not work when opening a .dra file
0 ^2 A9 P$ D, O1952163 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
0 @7 d" q# F7 X* p1982966 ALLEGRO_EDITOR UI_GENERAL SKILL command to access the Option window fields while in Interactive commands.$ {" o; I4 L$ q Z
1983567 ALLEGRO_EDITOR UI_GENERAL Alias with Ctrl not working with 'command window history' variable enabled
. |9 g; T' w( g2 o1989507 ALLEGRO_EDITOR UI_GENERAL Third-party tool causes PCB Editor to stop responding to command
+ k1 U& y) [ V2 Q1 T( g/ @2003511 ALLEGRO_EDITOR UI_GENERAL Aliases using control (tilde) characters stopped working after upgrading to hotfix 048* M* Z' } e& W z
2010418 ALLEGRO_EDITOR UI_GENERAL New command window breaks funckeys( g6 [+ V' C( W: ?, |0 e- g
2018201 ALLEGRO_EDITOR UI_GENERAL SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
$ |. T, b, h- T9 V) J. D2023468 ALLEGRO_EDITOR UI_GENERAL axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)8 ]2 j; ]; l0 k
2026428 ALLEGRO_EDITOR UI_GENERAL PCB Editor takes several minutes when saving a design
) F0 e. }$ ?/ N) k- M+ e2032697 ALLEGRO_EDITOR UI_GENERAL Funckeys with Ctrl not working with 'command window history' variable enabled
8 M3 D+ `. ]1 {) D, T7 w# ]2032717 ALLEGRO_EDITOR UI_GENERAL Funckey combinations, such as Ctrl + M, not working
$ P( w' u9 i1 Y! f5 p5 E- ?2014211 ALLEGRO_VIEWER OTHER Arrow keys are not panning in Allegro Physical Viewer5 s% C% m5 T/ {+ k3 A+ e6 f) f
2039081 CAPTURE NETLISTS Netlist not created: netlist fails for numeric pin names with backslash '\'5 z4 B0 r6 N, `' f. d- ^
1993057 CONCEPT_HDL CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)
2 i( d0 Y7 A( {/ X1 A$ |, G! ~2004641 CONCEPT_HDL CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager4 y+ |- Z; f6 h! O# t
2020901 CONCEPT_HDL CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
' e6 C8 u# P/ U `2014979 CONCEPT_HDL CORE The active schematic page randomly changes while editing text7 L4 g3 u; Y+ {3 w! j/ l
2027905 CONSTRAINT_MGR DATABASE Pin Property changes in CM during uprev to release 17.2-2016& Y2 i" b4 B9 N' O/ o2 U
1762263 ORBITIO INTERFACES Add set allegro_orbit_import variable to user preference
7 W5 D5 H4 X0 y X$ B9 W- z9 y9 o2005860 PSPICE LIBRARIES Error when simulating design with TL494 part in release 17.2-2016: O2 f" N: Q1 s. d( ?6 a
1980072 PSPICE SIMULATOR Noise in the waveform when using DELAYT and DELAYT1 with capacitor
% C3 q8 P7 k8 R3 } p+ h9 n% E1977615 RELEASE INTEGRATION Cannot import third-party schematics into OrCAD Capture in release 16.62 R" ^. e$ U$ n5 z
2027009 RF_PCB SETUP 'RF-PCB' - 'Setup' changes not saved on Apply; S/ {5 s" ~: z+ @
2002040 SIP_LAYOUT MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die' x$ T! a- [6 v
2024703 SIP_LAYOUT WLP Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'1 w, P1 V" i1 V: z6 B4 q
2010045 SYSTEM_CAPTURE CANVAS_EDIT Cannot snap back vertical CAP until moved up and down horizontally, ]( O2 P8 d" N- w
2010443 SYSTEM_CAPTURE CANVAS_EDIT Cannot select the CAP part
" I! l* U) [5 \. X2012843 SYSTEM_CAPTURE PACKAGER Cannot short two grounds in the schematic
$ X0 v; ?) C8 r, I% }" b; G9 [( y+ U2015574 SYSTEM_CAPTURE PACKAGER System Capture is treating quotes in PTF files differently from DE-HDL
$ R7 {6 G4 \5 `0 b) t2022653 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE- {+ {% U5 I5 N* [
2024742 TDA SHAREPOINT Accessing projects is taking time
$ Z8 R' X. ]! F0 {2010531 XTRACTIM OTHER Allegro crash on repaint of command window: W }* @4 {9 ~9 y8 n
2022351 XTRACTIM OTHER XtractIM is crashing the latest HF S049
/ [2 x: J- k' B2 `1 }. n( f. F2 O% Z, _+ x( p6 D
' j+ M$ m$ d7 F* f B' J: iFixed CCRs: SPB 17.2 HF0508 ]& V2 [3 E( B( l& }7 k0 P
12-23-2018 \) L7 K, ]# j( h) x
========================================================================================================================================================
2 W( B0 M9 U2 J& E( @CCRID Product ProductLevel2 Title
6 }( C$ Z* `) c3 V" q' z" M========================================================================================================================================================
4 K/ h+ v; c( y. T. Y9 H2012119 ADW ADWSERVER Cannot connect Component Browser to server
9 n6 M! d* p+ Y+ ^" z/ C6 _( J1998856 ADW ADW_UPREV adw_uprev fails and a typo in rule name
# a: d0 E' K' o8 y1 d1 L1673333 ADW CONF Configuration Manager stops working and gives Java Timer-1 Error' z; f0 c2 @6 w9 \0 Q' Q4 u( ~
1900342 ADW DBEDITOR 'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis9 z" J8 @: z, u( |, G
1997516 ADW DBEDITOR DBEditor stops responding on changing attributes
, w; k* n+ C$ {+ Y8 i1986292 ADW LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).
- Z. T8 I& k% ^6 _6 k2010460 ADW PART_BROWSER PKG-1002 error when opening a DE-HDL design! T3 |4 }) \2 g/ Y
2013430 ADW PART_BROWSER Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory
7 c4 j3 i& i* N; d: _2022806 ADW PART_BROWSER PKG-10005: Cannot package the following primitive instance in any section of the physical part
# G% z. f4 ^; x8 }: n2006528 ADW PART_MANAGER Part Manager does not update parts when Key PTF property value changes3 {* f. m0 |% n3 e6 r9 b
1980397 ALLEGRO_EDITOR DATABASE Mechanical pins with route keepouts (RKO) not updated
3 j* t' M- Z3 F5 s$ @' }1988171 ALLEGRO_EDITOR DATABASE Backdrill clearance Keepout is not applied consistently
6 @; t" C' q& q1 M4 F" T; D1994280 ALLEGRO_EDITOR DFM PCB Editor crashes during Unplace component
7 a# @: ~4 c9 D. _2012742 ALLEGRO_EDITOR DFM DFT for testpoint to outline not showing DRC
/ b# Y6 X! z6 H: B1 L; o! }0 u2002680 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on choosing Add Connect for two selected nets; T+ C! M% W/ u4 w9 R
2004597 ALLEGRO_EDITOR EDIT_ETCH Illegal BMS Identifier error when copying multiple via structures ~' K0 l# b6 w' y0 g' j
2004929 ALLEGRO_EDITOR EDIT_ETCH Net with physical pin pair constraints is using incorrect line width when routed3 }: ~+ T7 B- p% O0 q' b
2008314 ALLEGRO_EDITOR EDIT_ETCH Adding nets in tabbed routing crashes PCB Editor
! |5 r1 A6 _6 X5 q! C2018710 ALLEGRO_EDITOR GRAPHICS Using the mouse to zoom by scrolling stops working randomly$ r& w, R# z- f* P
2018841 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working in the Options pane in hotfix 049
' V: I9 p$ [2 p6 g% M+ ]4 Y9 f. v3 P2019482 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 7. J7 o; V* r" E s' ~
2019864 ALLEGRO_EDITOR GRAPHICS Using the mouse scroll button to scroll the canvas: focus is in the Options pane( I& }1 r/ m4 t: S# ?6 i
2020750 ALLEGRO_EDITOR GRAPHICS Zoom in/Zoom out scroll does not work
& I0 b! n) D% _2020847 ALLEGRO_EDITOR GRAPHICS Scroll up/down key focus remains in command screen even when canvas is selected/ B% J3 R% g, h* V0 U7 U8 F
1908812 ALLEGRO_EDITOR INTERACTIV Tools > Design Compare command does not work on Windows6 H; p5 Z) {9 [7 w
1995846 ALLEGRO_EDITOR INTERACTIV When there is an embedded component, the result of Metal Usage report is incorrect.5 e# U6 Z' W9 p/ y4 R' U
2011449 ALLEGRO_EDITOR INTERACTIV Command not found error (_impvision) for Impedance and Return Path DRC visions
' F$ j4 @- r3 C4 K1982867 ALLEGRO_EDITOR INTERFACES DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased
) ]1 ]0 s: s8 F1983177 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file: f- O- w8 T( a( V) r
1985623 ALLEGRO_EDITOR INTERFACES STEP model not exported from PCB Editor
, i# d3 I S) k/ }: V1994855 ALLEGRO_EDITOR MANUFACT Drill legend with counter-bore: legend size not uniform when database set to inches
7 R) ]; b! ]0 ?* f0 C$ t2001355 ALLEGRO_EDITOR NC PCB Editor crashes with NC route parameter& A( V2 p$ \9 S8 y! i7 P5 d( o9 |
1753414 ALLEGRO_EDITOR OTHER Ability to add Rigid Flex class in a format symbol5 z1 U0 N; v/ ]% w# r
2004786 ALLEGRO_EDITOR OTHER Legacy menu option missing in OrCAD Professional
3 h" Z7 C: r/ P( ^ i1949695 ALLEGRO_EDITOR PADS_IN Third-party to PCB Editor translation does not make a clean conversion* c( ^! }* V2 a" K( ^5 R- e6 Q
1949658 ALLEGRO_EDITOR PLACEMENT SKILL module creation issue: subsequent runs rotate module incorrectly; ?& k' Q0 E1 I& e7 h
2001496 ALLEGRO_EDITOR PLACEMENT Constraint Region not replicated as part of the Place replicate apply command
0 e* v. z6 ~+ Z5 w' [8 r5 }- h$ n2002989 ALLEGRO_EDITOR PLACEMENT Default rotation point is set to 'User Pick'
4 Y$ l* E" _' W0 K) p2007301 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
5 Y8 x% q0 V7 G, R! x$ Q1 V6 X. H, a7 h2007312 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
# K6 Y$ D, n+ z& W) \/ F- ?2008098 ALLEGRO_EDITOR PLACEMENT DFA boundary shows a shift if anchor point is set to 'User pick'
$ \4 i7 u2 o$ _0 m5 |% r7 P5 z2009085 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
# f% h! c8 k* y( |0 j2009090 ALLEGRO_EDITOR PLACEMENT DFA boundary is being offset when moving components with User Pick
: s: M9 X' d; g6 v2009580 ALLEGRO_EDITOR PLACEMENT Component outline offsets during move process+ w- a% o3 T6 f' q \: v. v/ v; }
2010726 ALLEGRO_EDITOR PLACEMENT Two images appear when moving component in release 17.2-2016, hotfix 048& O0 T7 G: P, G/ K' W. a
2010819 ALLEGRO_EDITOR PLACEMENT A separate outline appears when moving components using User Pick
- ]- g) H# m$ {' C' B& d7 b; f! `2011454 ALLEGRO_EDITOR PLACEMENT DFA boundary is not centered correctly on moving components+ t/ Z4 h! ^- r* P
2011497 ALLEGRO_EDITOR PLACEMENT DFA boundary shifted from the part when moved( P5 z5 j: \0 H$ C" Y) z
2014250 ALLEGRO_EDITOR PLACEMENT Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor
5 v& j7 W& P/ i& `+ ]" ~* c" c/ A2015676 ALLEGRO_EDITOR PLACEMENT Strange end-to-end DFA checking: offset of DFA from component when in user pick" a5 Q6 V9 C8 Y
2016421 ALLEGRO_EDITOR PLACEMENT Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED' p5 U8 T9 r; ?2 X0 K
2016452 ALLEGRO_EDITOR PLACEMENT Some symbols cannot be placed due to property definition differences
* k( ]9 ?4 {0 i1 }( ]2016527 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on moving all components on board
0 R7 {8 Y6 _* J2017364 ALLEGRO_EDITOR PLACEMENT Strange behavior when moving component: DFA or place bound area is centered around the User Pick position
$ }, R3 [2 s' o! T5 P2018859 ALLEGRO_EDITOR PLACEMENT Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines
) y# I) q2 E4 l+ X6 J* t2019364 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when moving components( Y1 O! H) Q; V6 y& e9 p
2019478 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component across the design2 v z$ n) `' n. h+ O5 ~. w7 [
2019624 ALLEGRO_EDITOR PLACEMENT DFA Boundary is offset from definition when moving symbols with user pick3 O$ C; K4 R1 h5 Y `
2021625 ALLEGRO_EDITOR PLACEMENT Graphical Issue with Edit - Move and User Pick: additional outline image shown
+ F& v; u ]: m! a0 K2022203 ALLEGRO_EDITOR PLACEMENT Place bound outline is shown at the center of the pick when moving a part by User Pick
6 I q8 q" F5 C2024655 ALLEGRO_EDITOR PLACEMENT Moving multiple components causes PCB Editor to crash" `$ {5 s. ?. z- ?
2025895 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol' J1 Y/ `2 M8 S5 r: u
2004497 ALLEGRO_EDITOR SHAPE Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes* ^, w5 |6 Q; o$ \( w2 x- }) r# B- X8 F
2007832 ALLEGRO_EDITOR SHAPE Cannot void shape properly after rotating symbol4 O @! s7 o6 P- w# ~
2009601 ALLEGRO_EDITOR SHAPE Error for shape created using third-party SKILL utility% m5 H( y" Q8 u
2010924 ALLEGRO_EDITOR SHAPE Dynamic shape does not void in route keepout areas
3 C1 j" m& S, e. _. m6 {2011176 ALLEGRO_EDITOR SHAPE Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI
& \9 }) ^, a3 ]2015446 ALLEGRO_EDITOR SHAPE Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.8 G w9 b% B( J. | r' ~
2017273 ALLEGRO_EDITOR SHAPE Same net spacing does not void properly for shape to hole.
7 m9 v' P! p* z: p/ s6 W2012878 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
. `2 J7 f3 `8 Q. [2018177 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
; d& j4 R# {" I3 x6 W; c2019437 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
- t& m$ M! r+ p5 D2020491 ALLEGRO_EDITOR UI_FORMS Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect& |* o5 M1 F, @: J! u3 [% ^9 a
1897843 ALLEGRO_EDITOR UI_GENERAL Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time
3 D, |) q* m5 v. `( t7 i2000445 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 048 with the new Command Pane as default
5 R4 M% B% o; A2001847 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys not working in hotfix 048
- i q" ^8 C+ R7 P, t6 V2008112 ALLEGRO_EDITOR UI_GENERAL Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)
1 \5 I, S" l# m% w2010370 ALLEGRO_EDITOR UI_GENERAL Shift + arrow key does not move component in release 17.2-2016, hotfix 048
g7 i) e$ s7 C2015418 ALLEGRO_EDITOR UI_GENERAL Funckey not working
/ W0 J: Q( a4 E1 G$ o6 A0 k2015443 ALLEGRO_EDITOR UI_GENERAL Text does not regain focus even on clicking after using a drop-down menu
X6 v' C1 b/ C8 R# e! L2016899 ALLEGRO_EDITOR UI_GENERAL Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane" ]& e- s9 d- g) P
2019753 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set3 K1 q5 y$ h7 V4 W
2019990 ALLEGRO_EDITOR UI_GENERAL Mouse over does not highlight pin, need to click
- M; V. a& _$ C0 o! R+ r2020162 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 049: pressing F4 not running Show Element
2 w- D8 n# M1 P. `7 _2020168 ALLEGRO_EDITOR UI_GENERAL Data tips not shown on mouse hover& m; q7 Z! R- L* F3 N
2020840 ALLEGRO_EDITOR UI_GENERAL Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed: i0 s3 Z- e r+ b% F+ D
2021416 ALLEGRO_EDITOR UI_GENERAL New user interface does not shift input focus and zoom in/out does no longer work in layout window8 D& N* B* a( b* y+ o
2022185 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys are not working( W3 V M! h8 ~5 L4 ^0 l+ _1 D/ t& H
2023402 ALLEGRO_EDITOR UI_GENERAL During Add text, focus does not move from the subclass dropdown to the canvas.
0 O o8 {. `% j6 A2025806 ALLEGRO_EDITOR UI_GENERAL Function keys and shortcuts not detected
4 [, F) E- ^! @' z$ }2027581 ALLEGRO_EDITOR UI_GENERAL Funckey problem: focus lost from canvas on using another window0 X4 |$ X% t5 Z7 O* S
2009382 ALLEGRO_EDITOR ZONES When deleting zone by Zones - Manage, the shape in zone is out-of-date' Y3 P# B4 n7 ?" |9 d
1977211 APD DXF_IF APD: die pads shift after export DXF+ H, J4 l: A4 i4 |4 j: O: R
2018483 CAPTURE NETLISTS Error when extracting netlist from schematic (ORNET-1193)
# v& O5 Q7 y+ b9 C1 u2022764 CAPTURE NETLISTS Schematic will not generate pstchip.dat file
$ }! v( _% O8 [* b6 q9 }; ^1921557 CAPTURE NEW_SYM_EDITO Zoom to region option grayed out
6 @! W4 f/ \7 e, V- B* e* y, o `$ F1945203 CAPTURE NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins$ N2 _7 V5 U, _
1950178 CAPTURE NEW_SYM_EDITO Ability to remove convert view of a component
3 L7 X' R* S6 H4 l2 I1966792 CAPTURE NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0
1 M& [; j; d' i2 }1969099 CAPTURE NEW_SYM_EDITO Cannot add convert view after creating a part
' q; z9 r3 w% B( l1969834 CAPTURE NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor
7 s! l0 b3 q. g! h, c+ l( W1970984 CAPTURE NEW_SYM_EDITO New part is getting Numeric Numbering automatically* z) u0 Z9 y$ ~* E: a" u/ f# C% d
1972607 CAPTURE NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property
- r2 G4 b5 |' M5 b" F/ P1972635 CAPTURE NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane
: j: R0 t& g! o8 T1 O1974296 CAPTURE NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation/ T+ R* Z- O/ e" \, b$ Y) \
1982783 CAPTURE NEW_SYM_EDITO Part Editor is blurry when zoomed out.
# \ U0 }6 q: |2 i1993361 CAPTURE NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default5 S* W% v4 ~+ E2 O# P2 C$ T
2003749 CAPTURE NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048
* @) e* M% ]) r: i2 \# n- d' f2004395 CAPTURE NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 048# c" }3 D: G2 `# S
2007747 CAPTURE NEW_SYM_EDITO Cannot add Convert View after creating a part
6 g4 L* d- f5 j6 u! P8 c% [% g2011321 CAPTURE NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048
8 Q6 h" k( M9 O+ z+ T8 D1 u2013146 CAPTURE NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block7 M7 L4 B; ~; t9 D7 i: J) O8 {( x; i
2002904 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048
Y0 l( A; W3 a) e0 _; q2002922 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048
6 ^+ `6 K: p, l8 u! T8 R1988812 CAPTURE PART_EDITOR Parts created or edited with hotfix 038 Part editor do not use default font size' |1 F/ m. t3 P/ y$ I) o
2008912 CAPTURE SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output: E* _) t4 p/ ]' W; w$ ~
1985701 CONCEPT_HDL CHECKPLUS Library symbols are missing from the examples folder
6 f3 U5 n' ?1 p4 S2 }1933789 CONCEPT_HDL CORE honor_sch_custom_texts
/ a" c0 F) X3 R1 t- i& U5 V1933892 CONCEPT_HDL CORE HONOR_SCH_CUSTOM_TEXTS
5 E& n9 w. [2 m6 V2001737 CONCEPT_HDL PDF DE-HDL crashes on choosing File - Publish PDF7 e. Z( R. a* ^
2010508 CONSTRAINT_MGR CONCEPT_HDL Schematic data corrupted on reading the data from CM database using the CM SKILL APIs
, O; ^, B2 X) h+ J1997461 PSPICE AA_FLOW 'Edit PSpice Model' from 'Assign Tolerance' window does not work1 i: V+ e( B$ F, p8 j9 W
2005948 SIP_LAYOUT DIE_EDITOR CTE expansion tool shifts pins off the die* f3 T* u/ O3 n
1893045 SIP_LAYOUT INTERACTIVE Refreshing bond finger labels causes all the labels to shift location
2 A4 Q$ t& B% }2006926 SIP_LAYOUT ORBITIO_IF Bundle translation from OrbitIO is incorrect
& a6 Y& h" }% X. d. {2006659 SIP_LAYOUT SHAPE Cannot form fillets inside a shape in hotfix 048
+ H1 @) v6 t* A1969192 SYSTEM_CAPTURE CANVAS_EDIT Pin Numbers of Discrete Symbols visible, n1 _5 A3 L& P2 y. u
1982368 SYSTEM_CAPTURE CANVAS_EDIT System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode
: i5 [; [9 D0 p1995012 SYSTEM_CAPTURE CANVAS_EDIT Connect lines do not move with components9 B+ U7 Z, Y0 ? N) r
1907992 SYSTEM_CAPTURE CONNECTIVITY_ Draw stubs is not respecting stub length setting.$ E7 u3 w+ i; O8 z4 M& i
1960100 SYSTEM_CAPTURE CONNECTIVITY_ Moving components after routing failure: connect lines do not move resulting in disconnected route
% N+ |/ V( B6 k9 I' o1988284 SYSTEM_CAPTURE CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level
; ~$ V6 ]0 l! b5 h0 _1996039 SYSTEM_CAPTURE COPY_PASTE Cut and Paste change the pin numbers for connector after saving design.
5 i E2 Q A) t+ s: T$ ]1951700 SYSTEM_CAPTURE EXPORT_PCB System Capture: Export Physical - Change Directory UI entry block not displaying properly
4 l" }) W @6 u! M# {9 \1970761 SYSTEM_CAPTURE EXPORT_PCB Cannot import System Capture netlist if PCB Editor is launched with -proj argument
" f1 ~) F7 U% @6 F0 W0 m. o1997533 SYSTEM_CAPTURE IMPORT_PCB Pins do not swap in System Capture on backannotation
, B$ T+ `# B$ t% K4 n! K1910962 SYSTEM_CAPTURE MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol# H0 f1 Z$ Z1 R, R
1962037 SYSTEM_CAPTURE TABLE_OF_CONT Table of content link number not same as page number in the title block
5 n L/ l8 s# ?0 _5 f% ]# y1986317 TDA SHAREPOINT Cannot enable Design Management and SSO session expires
0 | T6 W& ^" ?" H
% u7 P) K) {2 {# A
& a3 F; ?) a, kFixed CCRs: SPB 17.2 HF049( a( s) d) {7 G$ V: q6 _. p
11-16-2018
, {! I) I$ g/ w7 x+ k0 F" j2 H========================================================================================================================================================
1 i+ g% n5 \4 Z* L, t7 G, lCCRID Product ProductLevel2 Title ?# |1 z& R% O! ~1 ?( `
========================================================================================================================================================
* ~% a9 _. p H2002642 ADW ADWSERVER Exception in adwserver.out with LDAP enabled: t) I0 {* Z* J# }
2007046 ADW ADWSERVER Component Browser is not connecting to server in hotfix 0486 K5 r& F9 ?0 `4 S: V. ^+ X0 o
1997678 ADW DBEDITOR Model not deleted due to missing cell model relation. ]8 m% d* x$ \8 p/ l7 D
1985059 ADW FLOW_MGR Flow Manager issues warning about project path that contains a period, removes from catalog file/ s& ^* a m1 O5 B9 x
1991515 ADW FLOW_MGR Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code
2 P1 ]8 g9 G _: ?1972762 ADW PART_BROWSER The Schematic Models icon does not match the definition in EDM Component Browser @4 h& o6 k: l/ u
1830062 ALLEGRO_EDITOR DATABASE Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6
8 T) {3 ?3 n9 ~; f D1980161 ALLEGRO_EDITOR DATABASE NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor
2 f k1 i M6 y0 ^, A2003757 ALLEGRO_EDITOR DATABASE Open circuit not detected by PCB Editor: reports unconnected pin as connected
& Y6 M6 N" g3 }1 j# {9 P2009748 ALLEGRO_EDITOR DFM PCB Editor crashes on Update DRC
! b1 w4 n% F8 D1796895 ALLEGRO_EDITOR DRC_CONSTR Increase precision of Inter Layer Spacing check% O% ^9 O1 |$ y/ f8 l
1997487 ALLEGRO_EDITOR DRC_CONSTR Cannot add teardrops to some pins3 v8 Z: ?" G1 g+ G, h
1857024 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'
; }7 h. h8 G) V2 [7 Y9 e. K* g1979750 ALLEGRO_EDITOR INTERFACES axlStepSet not working for component definitions
7 W* x6 ~& F, Y1988168 ALLEGRO_EDITOR MANUFACT Graphical Compare in productivity toolbox terminates with errors2 ~9 P. y7 R3 h3 B( G
1982233 ALLEGRO_EDITOR SCHEM_FTB Netlist files cannot be imported into board as the process is not finishing
' G; ~% h. f5 Q8 n; t( S$ R2000367 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048
, E( L. w) q3 s2000397 ALLEGRO_EDITOR SCHEM_FTB Cross-probing not working with hotfix 048 q: M$ ? o% ~/ ]# e
2000552 ALLEGRO_EDITOR SCHEM_FTB Cross-probing is not working if we are importing Netlist from PCB Editor7 t; m# O+ g( l+ C) E- N* o
2001165 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between Capture - Allegro PCB Editor fails after hotfix 0480 B# `4 _3 o, w0 o* q
2002635 ALLEGRO_EDITOR SCHEM_FTB Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)
* l" v3 v7 A- M; a3 |& Z2004252 ALLEGRO_EDITOR SCHEM_FTB Cannot do cross-probing between Capture and PCB Editor" ~# ]2 b+ c3 H/ @! [& L, `/ P
2004305 ALLEGRO_EDITOR SCHEM_FTB Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 0484 f& U& D6 ?4 Z8 R* {1 q
1978660 ALLEGRO_EDITOR SHAPE Static shape on dynamic shape issue: thermals not removed when component is moved: o8 _( k/ |! u( q
1985035 ALLEGRO_EDITOR SHAPE Thermal reliefs not removed on moving parts2 W4 x8 J8 ?% z, z9 i* }
1960966 ALLEGRO_EDITOR SKILL Stackup import is not working in release 17.2-2016 via automation
# K- m. |5 q/ b2 ~2003651 ALLEGRO_EDITOR UI_FORMS Error on starting and loading footprints in hotfix 048: message about customExtended and customState& S# n4 @1 y# c$ N7 S8 c. A
2003810 ALLEGRO_EDITOR UI_FORMS OrCAD layout editor font size is too small for almost all UI8 ], g" s6 H4 r7 F1 q; B6 m
2003832 ALLEGRO_EDITOR UI_FORMS Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem
" j$ |/ p' P* }7 G$ w9 Q1 b2004769 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry
2 @6 _- z+ r& J' n2 d2007669 ALLEGRO_EDITOR UI_FORMS Broken scalability between OrCAD PCB Editor and Allegro PCB Editor" w! O. C% W/ H% f8 ?! B
1987164 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding when multiple sessions are accessing third-party tool/ K. @6 T2 G6 e( p
1983512 ALLEGRO_PROD_TOOLB CORE Allegro Productivity toolbox: Advanced Testpoint Check is not working- }7 P. m0 M4 l# b: d
1996008 APD 3D_CANVAS New 3D Canvas does not work in APD
" T2 B# x" D/ a. p$ f% M1993698 APD SHAPE APD stops responding and database is corrupted on moving, deleting, or updating a symbol
& p5 x0 i7 }; }* P1999446 CAPTURE OTHER Update symbol database in Trial
* j1 f. H& Q7 b" y2 Y6 o1962222 CONCEPT_HDL CORE Nested hierarchy block RefDes transfer issue: suffix added to RefDes
2 h6 Z, k/ D: x5 E1964260 CONCEPT_HDL CORE RefDes not updated in a hierarchy block on repackaging release 16.6 design
0 F4 F- ~" t; s# l: D b. e1972243 CONCEPT_HDL CORE Version filter does not work correctly3 e' N. D( [! t5 b
1993448 CONSTRAINT_MGR DATABASE CSet is duplicated with same name when modified in SigXplorer2 p5 c2 _, `% e" E! o# Y( g! E
1976148 CONSTRAINT_MGR INTERACTIV DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch
) u$ t2 @6 p E' m6 Y5 P1948372 CONSTRAINT_MGR UI_FORMS cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'0 |% `9 G: @, R% o4 ]$ z; ^
1961750 EAGLE_TRANSLATOR PCB_EDITOR Voids and some shapes of third-party board not translated correctly7 y+ R; \$ x5 x% ^4 n
1984569 FSP DECAP When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
* c/ ]: e0 s$ W1984588 FSP DECAP FSP crashes when changing pin functions or bank settings for a connector0 W& h$ O; _4 |$ E1 Z( n5 A
1984590 FSP DECAP FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf
' j4 i0 R& T% O1985555 PCB_LIBRARIAN IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap# L* B; _: t1 P4 {3 T. l
1961944 PCB_LIBRARIAN SYMBOL_EDITOR Hide symbol outline in new Symbol Editor
8 h6 w0 y& h' q* m1967532 PCB_LIBRARIAN VERIFICATION libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.* S) S. _. ?: Y2 L) e
1976965 PSPICE SIMULATOR PSpice 'Tools - Generate Report' not working in release 17.2-2016* [- \6 k6 y0 N/ U/ J; ~; Z
1982260 RF_PCB FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS.
0 j1 e/ V" S; M* T* z" ?+ k1981585 RF_PCB LIBRARY Cannot load RF symbol via2 into PCB Editor
|+ L' W* z5 O1976845 SIG_EXPLORER OTHER CPW trace models do not solve in SigXplorer after changing some trace parameters
z; h0 g8 W, G/ h H& ]0 }1986466 SIG_INTEGRITY OTHER Delay in Relative Propagation Delay worksheet is displayed as a negative value
( o4 O* G% @- P+ @1980264 SIP_LAYOUT INTERACTIVE SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text'
! y: [5 ?2 Y. l1 q1983381 SIP_LAYOUT REPORTS Incomplete Design Summary Report
9 q: e5 j0 B/ D2005709 SIP_LAYOUT SHAPE Dynamic shape voiding around same net cline segment: no property attached
) Z7 Y8 A; @6 n* R2008064 SIP_LAYOUT SHAPE Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted: n8 k0 ^; T/ S: c
1980967 SYSTEM_CAPTURE CANVAS_EDIT System Capture does not reflect part symbol changes- l* |+ k I4 Q! n# \9 V
1988928 SYSTEM_CAPTURE CANVAS_EDIT Changing version 2 of the resistor part makes the PART_NUMBER property visible
, M7 t4 `+ H9 I/ Y- Q1990215 SYSTEM_CAPTURE CANVAS_EDIT Draw Multiple Bits: Bits do not follow mouse smoothly5 m: W! N; H$ Z; m, a9 j( N1 t
1972658 SYSTEM_CAPTURE EXPORT_PCB Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
5 k' p6 g! V: K! G% L1989421 SYSTEM_CAPTURE EXPORT_PCB Part Manager does not update the PTF values
) a/ u6 u2 ]9 r h3 s- s6 s1992407 SYSTEM_CAPTURE PART_MANAGER Part Manager removes part properties and main window and details window updates are inconsistent5 Q; q% B% a& r5 S; K
7 K6 _. x U! E$ o# u6 m9 q' b$ Q' c( }7 x4 }
Fixed CCRs: SPB 17.2 HF0486 Z- t4 G0 X$ p0 g/ S2 [7 I/ A! x
10-13-2018
) K# J0 r1 m% s3 H% M! P4 Q4 Z: w========================================================================================================================================================& Q# o" T- o4 ?) k9 ^
CCRID Product ProductLevel2 Title8 f$ C8 u) C8 D! d# L z N) W
========================================================================================================================================================9 M3 v) R0 v- p: o" ]
1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service0 J b( k! n$ s* n0 u
1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library$ a% a, X) N, ~! A7 N
1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL
; ~3 Q0 ~; D; M9 `6 V1 J! e1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version1 e, }/ \* @* ?/ K0 q
1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter. D8 w+ K7 B0 ]" Q m
1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
' k/ ~' ]' B! W; }1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.( Z& r# M5 G$ b1 P8 h
1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working
4 g7 r( b V: |1 G' P& O1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors6 _$ x4 y5 M) M& C8 X+ r5 Q/ r
1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error2 v+ y, z7 \* e0 z7 t- A9 _
1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
) `5 q# A( a* w7 Z1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf
) s2 E+ e* y! ~# w x5 V3 l1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed
! d1 t7 Z, N& P l6 V1 V& o1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project `! o8 [; L' A7 a5 z) p) d3 g
1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
0 W# o0 o' b! k$ B1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.
5 Z+ f" [6 M5 {% H9 m* }6 C1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation
" x; W) P7 [ ]" Z: R1 S2 o, G1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux$ @ \& S7 a9 O; {6 _# {# |
1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
! S0 t, B1 B- k- G1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system) y3 n* _2 L* K2 E1 I3 V
1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library
# z" I E P+ i3 q7 B1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models
2 s% I. r# C# I8 e H1836620 ADW LRM Library Revision Manager crashes on clicking Help
5 l) z8 A. H4 Z' R1961845 ADW PART_BROWSER Error regarding environment variable
" d% l( r% ~8 G2 V' f1 ?1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error7 h2 d5 D$ X W7 M( `/ ^
1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design
; e1 a9 D, @! \! n9 c% v4 y1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas
: Q6 n# g$ _$ E/ r( Z: O1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius" Z9 P3 Y8 ?( y; `
1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file
% A2 b6 i! f# V: |6 j1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas
! z0 q1 ~. N! ^7 n# Q- q1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
7 i( T1 v& L3 C1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly.! _* f; S. V- v, i6 ]
1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas( H- n% ]$ E/ d
1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation9 d* J6 A& @/ x6 L
1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added9 x( p/ j, Y! V7 U, }
1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
* Y g) i9 U5 o% t% r( c1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut." Z2 s- T" `* r! Y, H: m/ V( a [
1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process( I1 a9 g, K: g6 [$ u
1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad; ^' b" ?& }+ V i
1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information$ \. [! X3 l9 Y* [% }
1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error3 g" f9 F8 V9 y7 R/ P9 y
1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced.
6 {2 m/ H! S1 n7 |* O+ w1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
, h5 K A M6 a; a- g; p1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
; v: z/ m. {7 `) I1 O# T% ?1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT- u* q: S; g" z1 S
1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin
, D1 N0 N% ]# Q* {4 S3 P$ E1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement
/ ]5 U1 ?/ I5 @5 H; `; B1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
8 I3 g/ x3 j) G: k2 E1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC.
8 g' J4 r3 W- t4 e& W8 w9 _1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii
; o, _' T+ o' S1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints9 A! c7 O+ D6 s, H6 m$ W& N
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command' u; ~1 I" A2 W. m9 b0 P
1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command
2 Z) p+ \* T4 z- l. _4 P1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command
6 N; N' \( c1 R/ u1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit
- B( Z! K) R& o: ~, E1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc
6 x2 O- n- n& g' Z8 K8 t1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired" L3 t# u' l; e+ p
1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode
" ?1 e& X' q# A* K! T2 N2 O1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor
5 P# _ g: W* y8 m1 r1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query
+ @# F0 s8 a0 s. c# C: X1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash
; w+ ^5 q* H# U e) I% {1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters.
4 j6 R2 a6 e1 y4 w9 Q0 J1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes
* k' Q0 j2 R; o Z/ Q. M3 |1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines ?) C0 C) c: o! v. r. K: _
1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file1 \* K9 u6 j3 w# r- \
1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro
: ]! E# t3 h- y# ~; I7 y1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger" C# e3 [+ `* ]
1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf( X8 ^+ t, E; u% k0 X
1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing4 [. s! a" ^0 K) @; m
1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running& o+ j1 C, l( Q4 Y/ V
1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class5 }* i5 ?! R: ]4 h' K
1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
& j1 V. ?8 u3 Q! i! ?1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly
/ O- Z) \& |$ H1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor
! r, {1 C) Z+ N8 X* r0 Z1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu
: }4 _8 M7 ?9 ?; K; [% W ]$ C& h1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.0 Z, U6 @. W4 i6 w/ N6 X
1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.2 S& f5 J- l0 ~# t8 j" u( k
1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER5 z- B z9 R/ _% c- M! d9 w
1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance
/ r: I4 }( M& c: f7 e* j/ Y6 a0 T- w1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer Y9 Q: Y) x4 F. Y
1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design
5 ? G# E/ {% T! C. m1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.
/ g) L) n4 A @3 ~7 U1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism: R$ ]- f- y1 o
1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present
P o( f; T2 C4 g/ [) h1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular
0 x7 `/ X" s' s3 P1 a: v, i+ r1 c2 n: P1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor& e2 j# b" e# p+ N2 J
1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined
8 F: G0 g6 ^7 A& v1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none
& B) F( m( `. E- U) z4 n8 \5 e$ d1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views6 y$ g% x3 v$ L! n- n
1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed! R4 R* L. P) S, F
1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems
2 q: u& Z/ h$ q1 C( M. Q1 u1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap
0 e8 r4 t- M* i1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively4 Z+ U- m- V0 a8 g' k
1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring
5 a" z- z) p. s1 D h1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics
" x; h+ ?! m5 C+ `0 p1 h1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash
+ m) s) @! t. m! \& e: `1 B- ^1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command
6 [/ d4 C S$ x# R4 ]1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room
& q1 `) X0 ]3 g G1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report
- L7 I2 ?2 k1 ` D# P1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file1 Z6 {! i3 r: d. e: \$ ]
1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary
+ U0 Z1 q% ]7 d% \3 S, c1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline/ @8 O5 w: z0 N8 d# \ V
1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes( s ?4 I, Z6 I6 m% z( M# Z
1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects
8 I$ I d9 q( @5 h' h( C4 f1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property/ H- U# P( w9 K3 m
1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6+ x/ }! w. y, k' O
1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect ?1 R' T# U+ @6 T' }' R
1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled
0 Q6 {/ ?% ]8 U; x' Z1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
7 d# p/ R) g- p# x7 F1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias
5 G$ q3 M- U! @5 S, P: a1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.
& a+ e( P) \* r; f- y1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments
' Q$ @, M6 M( k/ |& x8 L1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong( j* e' z3 [, G \
1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference/ C% t1 C; b0 n6 H: h
1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing" D7 \/ B' s7 {. }6 x; N3 U& f
1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board
$ `. w5 S% z, C7 I( p) i1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off
S W" @5 `: E4 T$ g4 @$ f2 x1 S B1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory6 D" Z/ Q' V U. z( v7 ^: V
1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory. {" `( n3 h {
1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path
8 c& D/ I4 X L/ G$ ^1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016) g. a; ^7 l# M! N( h, Y) {8 z
1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus( s2 O+ L3 C. U# q0 E) h
1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable
6 X3 \) i! v6 B5 b1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
/ G9 v' C2 @- q% t0 |3 q/ D% u, \1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-2016: M: \$ d' K. Y
1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-2016- V/ O6 ]8 D. L- X2 b6 |3 P( H6 W
1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports8 k7 }; L8 a! N+ ^+ |' Y
1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report/ v# \' H1 e1 @) }; \7 G2 e+ j8 S$ Q$ H
1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
8 A8 Q) D) F! q( V9 w1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects
# u: O0 w. L; \; {$ ]1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
! K6 B1 X, S! s- t$ \4 V8 L, a1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set( n6 C0 o7 ]+ h {6 O' D
1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup
, \+ a. Q( l+ f/ T/ ?8 _( M1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor
- U! a# D: V- r- ]* g1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor
/ |7 H, i) f! |% |; l5 R* a' Y# m6 Y1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor. M6 ^1 M$ w4 ^% v0 |3 u; {" y5 q) D
1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions( z6 Y. f7 u, k+ Y- G" [+ F3 Y
1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out
* B: o* S6 B4 W1 c1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 0380 r+ Q+ U" x2 p. O9 a
1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability
+ X/ M- ` ^; R& x3 m5 b. f4 J1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution
+ N% P/ {/ l9 u: H) i1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.& h' D9 i* ?: ^" o
1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid
/ I/ _5 `2 d" O9 {9 y* r1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'
5 l, Z9 k4 M8 n$ i1 |& I/ I1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.
& X# g3 i4 Z) B% O; U! Y- v) A1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor2 d6 n! s4 E/ o# u" p" H
1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out& b; E$ F* L0 z' M0 n3 f1 b
1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins
* t. B* y( T7 c5 G3 R% B/ n; h1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design
3 P: G) W$ C5 i' C, Q1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor' i. Q8 Z. E$ T" x
1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet8 `6 H% Q v0 W+ q# `, d3 h
1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets
6 z/ k1 K* K- \1 {5 Y' x3 Y9 q0 y( R6 I1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)
0 P* D$ g8 \8 s+ r1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path
1 L, W6 _; U6 }# i1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038& {5 O* n' E5 T( l, o# B+ t
1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.5 U1 @- G0 X( Z7 c6 P& y y( k
1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box
# W: f/ x' B {* P. {' ]1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.1 G6 C7 x( h: M% ~
1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table
( k+ ~1 t* r/ V3 e# C# N8 M1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name
; A c' m$ j, {8 b' w) P z& C4 ~" h" U1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved
% q w0 s2 @0 n/ t; H W# ~1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned
$ O+ u3 K* W, e& | S5 `% X1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs& k) W2 E# ?5 t; t
1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D
3 P9 S6 ~& i& e3 T! y1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
* T6 R5 F: Q, ~1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
. {# ?7 [0 I9 N8 R1 |1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.
, x( q8 S5 t, E# Y: [- v1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.
0 f( G; p, ~5 @) e& v h' _) z. L: u1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version
8 f1 e, }9 ]* r: Z% @6 X5 f5 {1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme7 b9 O% s$ }8 {6 r
1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation9 j# S3 Z: O" F$ u8 s
1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time& B' J* c2 V! ^
1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.
3 B8 e0 d- j) M1 f1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value
; G' @2 H- M8 c( R, \1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name5 A. T7 b7 q6 k6 N/ h
1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection+ ~' b6 s" Z) b. ^7 U9 B$ F
1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic
7 r. t( ^$ m# Y) i0 t! z' q8 q4 v1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename
' H! b& F6 E5 N4 t1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging
1 v$ P: v# y& z" b1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore- V( |2 J9 d( Z( ]
1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044$ M& z' d# K0 ^3 i7 Z1 M
1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic8 w5 v4 P$ o% t8 r: L0 n! E
1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option( N: v+ i# Q. p# Q; v3 Q7 c
1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file
& B3 V; k7 r5 P9 z1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1' p0 I4 L5 Z4 z1 Y1 |+ \
1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.' r+ g. B% a( u/ ?" t2 T
1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF
2 X: l1 T$ X/ A1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file
1 x5 _8 q. B3 y Y( ?/ N d; T) `1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session
7 R" J* m) ~' Q, [! o' I; C1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error- I* f9 c7 U( J1 w, v0 @
1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash) U5 _+ q9 l4 U# N/ e% H ~" ?/ A
1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet5 A: k4 K6 p( {
1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design7 O- @- T8 \& i2 ^' y7 h
1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 0367 m: Y) V* W: Q @5 K4 f
1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever) i$ C6 u5 I/ |# X9 L) A7 d
1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM' j- i+ V: |8 u
1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode
9 n! e' L D5 x, K1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.# ?* o3 m, r: J& A: w( t
1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors/ A8 g4 G# J$ u- Q! p: I9 p; U
1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users
D& |+ E2 m# k G1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149
4 `! ^/ b G* D% X# v5 W1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016
, P, I8 L% y+ s! [& n& S6 E5 t* \1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow
, d3 D9 p' C: \6 T$ O: N$ M3 b. \" L1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL% L8 E6 H- x, C( K
1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
+ }. G# d$ O+ u2 A$ ~& I1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included
& _- P! E. I9 U1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error0 _9 A% m d8 p% L
1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file& H/ C8 s! F+ A) C# F, ]
1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer
! B0 v: i0 X e- D$ a1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol
8 }- z, ^) f# o3 B1842007 PSPICE LIBRARIES Change required in swit_reg.lib7 _. B$ G. R( |
1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
) f. G) D' \* [; W1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB' Y+ S$ ?6 G* P! i: `" B
1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation j" q3 q1 ^# v2 {7 Z+ @
1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow' w# |1 ]! v% l# K; z5 t# d
1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation6 x0 |7 j9 a! P n
1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor; m& V( P8 J( m7 h! `9 ~
1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke
& F( J8 W/ T2 Y1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries
0 G2 q/ v* P; I8 R" }1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
" R1 y9 G; D2 f1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design
! E$ A7 K3 w8 ?5 C* P; t7 f, X1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis
5 D9 I/ H) J6 u" r% r1887119 SCM IMPORTS Cannot selectively update changes in VDD! m4 h0 D& k9 t# I2 W$ X# N
1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences
* @8 S/ s% x: l" F: Y1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL4 M+ s6 u2 a. X* i m
1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved
' y4 I; u1 j! X* \9 l: |1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager
; U X/ ]' l- t: D/ }1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save
, k/ [2 h9 V5 Z1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology
) |. L* E3 D* Z( r E6 `1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected
8 f' S& P8 I, @* r2 k$ I/ G1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines' t4 X" }4 R* p* a; A, ?
1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation
! Q8 _$ l% b: E0 x% R0 B) v1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor, T8 U0 S* \* l O
1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs
M- m3 Y) K* f* `1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation
" Q$ g8 x( e( n. A6 e1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s
8 J- W: b" i! K4 C1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive
# M% v/ G& j2 D/ M9 \3 g1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read- u9 m2 t: `3 D: e
1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA
. Z+ d. M2 {6 D1 S5 o1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file4 G; h$ @( P' g+ ?: N+ |2 T. @
1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window5 ]9 I' K* n: b: }
1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation# F! @$ f3 @& V+ b( ^
1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value4 N7 j+ B, v1 f7 k$ u/ \5 d
1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly
7 |4 [! V2 [& d" j. y4 D) a1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash& d4 G/ f. s8 n: k# z# u* e
1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work/ J- K( R, n+ S9 p% S+ _
1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up
% x% j! L" L! T' z$ c. J1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values
: B! z* J' S( I3 |# u6 Y1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive. O2 T2 t4 i$ L+ K
1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics% |# F3 V& m' V0 d4 z
1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views
: q; G$ X, N; a1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken
; N8 ~! }9 W, c" Q2 U9 k( B* K1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view
5 h0 @( L# u$ M4 g0 `0 Q1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error
B l7 n4 t- l3 A1889898 TDA CORE Cannot check in the top level of the project in TDO
: z- P0 s4 v* g& l( p4 ~5 F# a2 Y3 S$ I1892411 TDA CORE Unable to undo the block checkout if something fails9 w5 T* e4 y* q) O$ n1 r5 N, P: J% V m
1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL
5 P* C$ e( K' j8 W0 `( x% P& P0 c" g" U
' f0 }* G/ m% d$ A7 U+ U/ J, WFixed CCRs: SPB 17.2 HF047
6 k D0 x4 n L! P; ?* w) m09-9-2018( Y* O& ^6 `' g& p; j2 s
========================================================================================================================================================" w& g% A X" b+ I0 X2 g5 b) V1 v
CCRID Product ProductLevel2 Title
! Y6 q5 T% n. w+ }! t _1 c8 ~========================================================================================================================================================
) j" b/ K9 ?0 [1969527 ADW LIBIMPORT Getting java.lang.NullPointerException error on bulk import in hotfix 044- p0 D+ i. o& b5 e* h$ B w' Q
1976219 ALLEGRO_EDITOR DATABASE .SAV file not created although message states it is created. y4 W( ]! J3 h( ~0 q# ?
1968270 ALLEGRO_EDITOR DFM PCB Editor crashes when running DRC& `& L* L' f6 |. v6 i5 Z- {
1978421 ALLEGRO_EDITOR DRC_CONSTR False DRCs between via and its fillet shown after editing shape boundary
0 l$ W6 ?4 h" {% c: D1966772 ALLEGRO_EDITOR PAD_EDITOR PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor0 x5 i- T) ]+ Q* f$ C8 o
1973866 ALLEGRO_EDITOR SHAPE PCB Editor crashes when deleting a group# W, Y8 |3 d3 H5 R- F9 S
1818779 ALLEGRO_EDITOR UI_FORMS Dialog box goes behind main window on clicking PCB Editor canvas
0 n/ T1 o# ~1 x# ?6 S S1880175 ALLEGRO_EDITOR UI_GENERAL Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016
9 w4 k2 @2 o) w# R% D3 y1946027 ALLEGRO_EDITOR UI_GENERAL Arrow Keys in Canvas stop responding after changing the view.
1 Z6 c+ r5 x1 ]& n& ^5 C1967701 ALLEGRO_EDITOR UI_GENERAL Arrow Key panning does not work when third-party SKILL call is active
/ N' r" U8 l2 d3 o7 W1967706 ALLEGRO_EDITOR UI_GENERAL Observe Special Characters when command is run3 h8 `$ `' S) t$ }, n8 E* K7 k, b
1971183 ALLEGRO_EDITOR UI_GENERAL Focus is lost from command line when Save icon is used+ Z3 ]) W( t1 Z8 ^7 C2 g4 r9 I
1971186 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + N
3 ?) }& Z1 R& w7 W: g- T# z1971190 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + Alt2 o7 q1 b: w( \3 h9 M
1971200 ALLEGRO_EDITOR UI_GENERAL Focus is lost in comand line when you save using command save
' ~$ R2 h# m6 W( D6 {% j/ J1961833 APD SHAPE Crash when changing dimension of existing via padstack in the design6 }' ^9 i" ?+ [- k7 O) `
1968256 ASDA EXPORT_PCB SDA crashes directly after Export to PCB. `% P4 I' l a2 M g3 r
1970284 ASDA EXPORT_PCB Placing part crashes SDA6 R' ^7 N9 [8 f* C) w Q
7 M) @) @. f' [3 O5 f
6 @+ z [# a* g3 w3 y0 x8 xFixed CCRs: SPB 17.2 HF046) ~6 G4 t! Z! A) M+ f( f
08-24-2018
$ z0 V3 O% J, e" f7 F5 @7 P========================================================================================================================================================$ V) f& m2 ?% N! @* ~' {
CCRID Product ProductLevel2 Title
3 d; q' n8 D7 `/ T- q========================================================================================================================================================
9 k9 t) R: c1 _6 w, y, |+ K( d. t u! q1880800 ADW PART_BROWSER Server connection failure on a running SDA session.
& `; J! s0 V' Z5 E1880895 ADW PART_BROWSER NCB - components missing from the component browser' w* `$ s/ t6 f3 I
1962336 ALLEGRO_EDITOR INTERFACES Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom); o) x d \1 F `1 |
1955128 ALLEGRO_EDITOR MANUFACT Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart$ B5 t# v8 E# h4 Y/ c
1969088 ALLEGRO_EDITOR SHAPE PCB Editor crashes on updating shapes to smooth( J7 {; Q$ _% i2 w f+ x4 F
1963828 ASDA DESIGN_EXPLOR Unwired schematic block movement with text is not correct3 C8 y, h* }, g. {) x- V# C B
1954426 ASDA OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA
9 a, w( P" z: b, d1965423 ASDA OPEN_CLOSE_PR Crash when working with notes in SDA
; ?7 b4 [. v! P7 x9 M/ k" }1960060 ASDA PART_MANAGER Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset% ^* m \ h3 p9 f) V
1960112 ASDA PART_MANAGER Part Manager incorrectly updating part property values8 x9 }! ?$ p9 F" |" d$ [# ~
1955723 ASDA ROUTING Draw Multiple Bits misses bit 0 when in reverse order.
2 C0 [7 k9 z* @1 M1952963 CONCEPT_HDL CORE Variant Editor takes a long time to load( M' z8 {- }( _2 P
1962568 CONCEPT_HDL CORE Directive DEHDL_BROWSER_FILEPATH does not work" V; t6 g( O, |
1939192 PCB_LIBRARIAN SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap$ u/ n# O9 N7 x" `3 r2 Z! `
1952967 SCM OTHER Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version
! z6 _( t- x& R* Y1948999 SPIF OTHER Some place_keepout shapes and antipads not exported% d. W! L, c y6 ]4 |: U3 J
* v& r! l3 G- l5 ]2 ?8 r
7 @* n1 T6 J8 g& T, o+ y
Fixed CCRs: SPB 17.2 HF045
2 }1 M- n7 G' u. T2 J2 M* z1 V08-10-2018
3 H6 K% b, F4 z, |, w" d' a r========================================================================================================================================================! U ~3 @% D2 b; x5 n9 P7 `+ u
CCRID Product ProductLevel2 Title5 Z' [6 r* x% _& J: t8 _
========================================================================================================================================================8 |% |& f8 |% u" w, {/ |
1934956 ADW DBEDITOR Footprint missing from part in release 17.2-20160 }9 M# E8 M: a
1945005 ADW DSN_MIGRATION Right side of Migration dialog box is cut off
& H, w$ E: i" t1933245 ADW FLOW_MGR 'Open last Project' button should open the last opened project( P+ B7 `3 B( V3 Y# y( ?8 y* K
1953210 ADW LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.3 ~2 ~9 ~+ Z1 |& d6 U% o
1953727 ADW LRM LRM missing two symbols when migrating from release 16.6 to 17.2-2016
6 g7 h' `6 M! s5 r1952923 ALLEGRO_EDITOR DATABASE PCB Editor crashes on trying to delete layer9 D! t+ n) k# J5 s, N" x# {0 g
1957171 ALLEGRO_EDITOR DATABASE Pastemask offset not working when creating a symbol that requires two top-paste masks# x6 [2 K& C, F0 R. x* O
1960059 ALLEGRO_EDITOR DATABASE Stackup definition causes custom script to crash! l7 E. s% \+ F
1932864 ALLEGRO_EDITOR DFM Exporting DFM Constraints losing the association to design level. R3 \( u' L3 [) j+ t
1957467 ALLEGRO_EDITOR EDIT_SHAPE Compose Shape copies lines to wrong subclass
5 B. }+ E3 H% E/ ~ e5 [ g1938536 ALLEGRO_EDITOR GRAPHICS Multiple crashes on different boards after installing hotfix 040
8 J7 q7 L$ W# ?( Y) k1954075 ALLEGRO_EDITOR SHAPE Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled6 m# q3 B' ?) q: A3 K: ]( R1 x: N; H* T
1957803 ALLEGRO_EDITOR SHAPE Wrong dynamic shape status
' u: r# F' P0 Z1949923 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when any command is active
' l5 ^: S6 d* f- N+ o) v1 `, k/ j I I1963245 ALLEGRO_EDITOR UI_GENERAL Alias behaves as Funckey in release 17.2-2016, hotfix 044
) \! s1 Z# Q3 f7 D! |" Z1892126 ALLEGRO_PROD_TOOLB CORE Clines disappear and then reappear suddenly on using Route - Shield Generator: |* g& Q3 R. s6 \* ~; ~
1931127 ALLEGRO_PROD_TOOLB CORE ZDRC not working for Xhatch Shape/ Q8 J# n) l3 n' t/ c
1932563 ALLEGRO_PROD_TOOLB CORE allegro_legacy_board_outline environment variable not set in PCB Design Compare.% }4 i( | O3 n' d. h) U
1929855 ALLEGRO_PROD_TOOLB OTHERS Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist- d+ }2 p1 m0 p8 f. Q
1956494 APD DATABASE DBDoctor removes pads* ^/ b% B& Z+ h5 _0 J W
1956291 APD INTERACTIVE axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style( u7 [6 t) Q* J3 O
1960127 ASDA ARCHIVER Using the Tcl command 'archiveproject' crashes SDA( E1 Q4 C/ _8 S- F) z: @
1953718 ASDA CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why
; a, Y$ } a9 I g$ {' Y1924498 CAPTURE SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set7 t; |9 ?" R8 @2 H! ~+ _/ g. r/ S
1927129 CAPTURE SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window& [/ l6 Q1 O% \% {- S) R* i
1928255 CAPTURE SCHEMATIC_EDI Unable to place a specific section from Place Part) P, E# I/ e! q9 c# v( m i
1945207 CAPTURE SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part
# E) _4 R, ?+ _3 h( r' ~( D1945661 CAPTURE SCHEMATIC_EDI Section drop-down in Place Part window is not working8 ?" M) h: U1 V: } W2 ]. @7 v% R
1958121 CAPTURE SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor
) f4 f' l! G; Y8 ] U& K+ J; m1956535 CONCEPT_HDL CORE DE-HDL crashes on Import Pin Delay for a CSV file: |- S0 b R) }5 ?: {
1960922 CONCEPT_HDL CORE DE-HDL crashes on moving netgroup on Windows 10+ I0 e( h; O) u1 w- K# P9 P
1964016 CONCEPT_HDL CORE In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10 |/ i/ o. b x, H% W
1907040 F2B PACKAGERXL Export Physical output board file name reverts to old when changing options
7 v8 h0 {6 D7 \1957862 ORBITIO ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack
3 l6 u- h! ~" I) t9 O; L8 j8 Z9 @! R
9 V# i7 y) b/ b5 A$ R4 c5 p
Fixed CCRs: SPB 17.2 HF044& A, a5 P2 ^! U4 ~1 h3 ~. {7 @
07-27-2018
d/ ?4 Z) M# }6 e+ Z2 L8 n========================================================================================================================================================. i# f: ~; w' p8 y! y( y4 R
CCRID Product ProductLevel2 Title, P2 z8 g; P. r! I# U1 j
========================================================================================================================================================
! l6 g7 _9 K" U) o1943727 ADW DBEDITOR EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts* z5 L! c. h. M: o" @
1800630 ADW FLOW_MGR Support spaces in design directory path on Windows2 _9 W1 i/ Q3 B
1951052 ADW LRM LRM stops responding on project update and removes parts from design
3 @# b" y$ X4 t$ N9 M% Q9 g1891428 ADW PART_MANAGER Resistor turns into a capacitor when placed
, y2 C" g, [. G1945194 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer crashes when opening from board file.
( c5 ^0 C7 g! n% A6 C% Z, n" i1935558 ALLEGRO_EDITOR INTERFACES Exported STEP file missing components when viewed in free STEP viewer! U4 t0 A; l+ F- z2 X7 U. k# h$ [
1945640 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification0 i6 m6 c1 z) n1 p. S& b I, L$ i
1948454 ALLEGRO_EDITOR MULTI_USER Window DRC stops responding when run in Symphony5 J! K# K9 M. ~6 Y9 G2 V
1946619 ALLEGRO_EDITOR SHAPE Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.
2 Q: k( d+ a8 f1946708 ALLEGRO_EDITOR SHAPE Same net hole to shape voiding is incorrect.6 F! H) [- Y I' x* _- Z( J5 j4 V
1952213 ALLEGRO_EDITOR SHAPE Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent
- x m w- ?- o/ T1889433 ALLEGRO_EDITOR UI_GENERAL Command window shows result at the end of a command rather than showing dynamic updates% R% m( k6 z- h. T( ^
1933503 ALLEGRO_EDITOR UI_GENERAL Extra click required to enable command window
, s0 a- U# _6 r5 C, c0 m1943692 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working' A4 B) V! ]4 H8 I' L
1945914 ALLEGRO_EDITOR UI_GENERAL Mouse focus lost in the command console when doing an 'undo' from the toolbar icon
0 ~1 U# w; R$ Q+ z. E1 x+ Y1945920 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when the toolbar is used for any operation
, E/ r) j' p1 ?# c" V% G1949922 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window after save or even autosave
6 a$ z$ Y& @, P, L1947551 ALLEGRO_EDITOR WIREBOND PCB Editor crashes in wirebond edit mode
2 \% u. E [# l! M/ m1935722 ALLEGRO_PROD_TOOLB OTHERS Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016
! z7 J$ E% ]5 `7 D7 n/ L1951511 APD REPORTS The result of Metal Usage Report is incorrect.
! _' O" i! `9 S( c3 Q1952942 ASDA GRAPHICS Need metric (mm) support in grids in SDA" n' ~2 O8 L0 j8 I. z
1948122 ASDA TDO If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project
5 f9 F- i6 Y9 i, F0 z/ T! U6 B1931199 CONCEPT_HDL COPY_PROJECT Stop hard coding Copy Project license inside EDM1 } x9 A- i3 t& M7 e4 s) C, F4 f
1938153 CONCEPT_HDL OTHER Component Browser stops responding on replacing and modifying components
- U6 B4 {" W' ?3 X7 Z' _1770601 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line not shown in PDF
# y3 y& a$ b% _- S) S6 u/ F, f1791175 PCB_LIBRARIAN CORE Allow baseline of cells with pins at symbol origin: change error to warning2 t5 _" n! N- s
1922238 PCB_LIBRARIAN CORE Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point
- x$ @1 \ y5 ]# c: a; W! O' l0 X1936812 PCB_LIBRARIAN GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste
) c9 S, t1 J1 F/ l1804159 PCB_LIBRARIAN SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move
( O5 H9 `$ l0 g5 @6 l! j8 k1 E/ n3 v$ z! Y1927422 PCB_LIBRARIAN SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016
. w( y" `+ p( b0 a1939272 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin% ]+ [8 h; l* m: X% g4 i e' _
1928076 RF_PCB DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF! s0 n9 J" { `7 ]; w6 k1 E
1929574 RF_PCB DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly" Q, o: V' [0 L5 b; ^
1850360 TDA CORE TDO crashes while changing the root design
9 W. }, I# C# C% p1934388 TDA SDA SDA TDO crashes on attempting to check in a 'New Block in Shared Area' B2 L1 j3 r2 {. g p
+ R8 B1 C& D. E* n% Q# S9 {& S% O) m6 }7 O( S o
Fixed CCRs: SPB 17.2 HF043; D0 k3 G- }* i. j
07-13-2018
% ]0 E+ b! _; f, s========================================================================================================================================================
" P5 p& d$ R4 {& e7 nCCRID Product ProductLevel2 Title" J7 k! h% {* C- \
========================================================================================================================================================
, T9 \0 c" u u( y' _1 c" f1935813 ADW DBEDITOR Auto merging of DE-HDL and Capture Classifications is not working
! |9 q6 C, j! D9 A; p; V1935834 ADW DBEDITOR Some DE-HDL only classifications are removed during the CSV merge process of libimport k6 ?; [. y- J9 N/ S8 T6 A! x
1941570 ALLEGRO_EDITOR DATABASE PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins" ~+ p) U4 ~% }+ r4 e- P% l
1942536 ALLEGRO_EDITOR DATABASE Allegro PCB Editor fails to create backdrill plunges in Zone area
. I6 x; a+ y& k! ?1 t1925899 ALLEGRO_EDITOR DFM PCB Editor crashes when placing components in Hotfix 039
# ]& M; E; ?# _5 R3 D" G5 r1943113 ALLEGRO_EDITOR DFM Restore normal move/slide via performance when annular ring checking is enabled.
- i$ x) C, D$ u" H1940939 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashed on running the Gloss - Line and via cleanup tool6 M7 A# Y8 U+ R
1937754 ALLEGRO_EDITOR GRAPHICS Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR& _# ?: e: Y& Z; M# z
1937056 ALLEGRO_EDITOR INTERFACES Cannot import IDX acceptance of third-party change to PCB Editor1 b$ d" {0 Y# S) T. {, ^1 t2 i
1940197 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file from third-party
i0 L. {+ \1 E0 C( w1940232 ALLEGRO_EDITOR IN_DESIGN_ANA PCB Editor crashes when running Return path DRC7 a* y) ` e' ^
1916921 ALLEGRO_EDITOR PLACEMENT Property Pin_Global_Fiducial not inherited from symbol into board
) J: t, e6 c( Y0 @; G1862241 ALLEGRO_EDITOR REPORTS In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics
# P( X6 m8 ]8 v: t1935448 ALLEGRO_EDITOR REPORTS Etch Detailed Length Report lists only one coordinate pair per trace8 p$ b* ?1 l- ]$ P( G" m0 b& x
1948322 ALLEGRO_EDITOR SHAPE Allegro hangs when axlPolyOperation api is called6 o& H* U; l7 t* I
1795564 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, focus is lost from command window after right-click. ~0 N8 ?$ U7 w2 K* C/ F$ g7 M
1919247 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh
; |/ v! D& Y- u$ f1919256 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issue: Symbol disappears during rotate6 K; O) V: l- ]* d* u7 ]
1933526 ALLEGRO_EDITOR UI_GENERAL Panning is slow in PCB Editor in Hotfix 038
8 Z% P# P6 O, _3 t9 S- e% n1933530 ALLEGRO_EDITOR UI_GENERAL Strokes are slower to respond in release 17.2-2016
H0 @3 N7 J) o% [, a# [1933536 ALLEGRO_EDITOR UI_GENERAL Third-party dialog stops responding on running commands
4 {& a n! S. u- |/ Q- v1782227 APD DIE_GENERATOR Ability to specify rectangular shapes in die text in. ^3 H" p2 \/ J* f4 Z
1933011 ASDA PART_MANAGER Parts changed in library with new pin names are not reported or updated by Part Manager
" Y; e; H7 d- o, L( A! E( H* X1924529 CAPTURE NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/0394 X8 @: o! D0 D3 q0 U5 z1 l. O
1925846 CAPTURE NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception' S7 j4 h/ U) P2 r# t, G
1928905 CAPTURE NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 038
G9 N9 K7 A) z. p/ a7 ^1928965 CAPTURE NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing3 E, \9 Z2 K" z1 H' _; L
1932149 CAPTURE NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039
+ H% g/ ^# m- O% o" i0 j: a/ S0 ]1936301 CAPTURE NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)
3 M2 g; t: ~' u" _( g6 }' w: l1917172 CAPTURE PART_EDITOR Pin name rotating on schematic even when pin name rotate is off in symbol editor9 }$ _7 I4 f+ u4 Z
1924456 CAPTURE PART_EDITOR Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic
& F+ ] h/ B8 L3 q! i) d" {1928872 CAPTURE PART_EDITOR Pin name locations are wrong and each needs to be placed manually
( h# e6 K1 ?) i' ]) ?+ k1929562 CAPTURE PART_EDITOR Changing pin name while adding a pin not intuitive in Symbol Editor, Z) \* i' }, e9 k
1932732 CAPTURE PART_EDITOR Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
; Z6 y0 _% R0 `' n! t+ ^1933523 CAPTURE PART_EDITOR Connection box does not appear after changing pin of a placed part in Hotfix 040, v" s2 k9 w/ H1 \
1936994 CAPTURE PART_EDITOR Error because of illegal characters in pin name and number and net name$ j! Y8 D8 ?; x/ ?
1943074 CAPTURE PART_EDITOR Pin names rotated in Part Editor not rotated when placed on page
2 \% h' L/ P3 e# `9 L) _3 a6 r1943078 CAPTURE PART_EDITOR Pin name rotate not working.2 I) T0 z( h: W- x- u+ t
1945055 CAPTURE PART_EDITOR Pin names not rotated in schematic8 ]; L9 `* c5 }2 F& \" B
1925700 CAPTURE VIEWER Pin numbers and text not shown during Variant View mode anymore., X; q2 r7 P" e) x
1914437 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference Report appears even though there is no difference in constraint.; w3 X' j3 _' K. {& j
1935152 CONSTRAINT_MGR CONCEPT_HDL Match Groups are not formed with the correct pin pairs0 v+ n/ l( X2 L0 K8 y
1940575 SIP_LAYOUT ORBITIO_IF Need new routing flow/ C4 _+ @' l, [
1923722 SIP_LAYOUT STREAM_IF Use one symbol for all instances of a Via Structure4 s" X, J6 `6 H$ `
f! v# L) b: A+ y! ~" }. L5 R
: W) ]; b+ X4 K/ X
Fixed CCRs: SPB 17.2 HF042- C$ c4 F# Y& w0 B1 h0 @
06-22-2018
; U1 H* k8 p# B+ c- t========================================================================================================================================================6 w' `& I' l7 i$ b9 Z+ A
CCRID Product ProductLevel2 Title8 p! x1 w$ m3 Q, T) ]
======================================================================================================================================================== P( X6 A; {8 P( b) R
1922654 ALLEGRO_EDITOR ARTWORK Difference in board and Gerber display3 t5 o+ R; V _9 }1 @9 P/ D
1932714 ALLEGRO_EDITOR COLOR Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file
; S6 k7 k* [% }$ m! I1932316 ALLEGRO_EDITOR DFM DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing
7 h; n, H# c- u% R4 j) B Y1914334 ALLEGRO_EDITOR INTERFACES Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor4 c" h0 o% w9 Q6 U
1910213 ALLEGRO_EDITOR MANUFACT OrCAD PCB Designer shows Backdrill Status in Check - Design Status$ e/ U1 F( a! a7 c
1933049 ALLEGRO_EDITOR MANUFACT NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.% S0 S5 Z5 J- M" {
1880576 ALLEGRO_EDITOR PLOTTING Extra lines appearing in plots that are mirrored# y' Y2 _- G( c8 t
1881031 ALLEGRO_EDITOR PLOTTING Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes
! K* H; ]% v( \; P1908005 ALLEGRO_EDITOR PLOTTING Plotting with mirror options set results in strange lines on the plot
' B0 z/ R8 ^; S# C3 t* d- r6 @4 A' G1909530 ALLEGRO_EDITOR PLOTTING Use mirror function when plotting lines to design
9 P3 Q) [* [! p8 l1919405 ALLEGRO_EDITOR PLOTTING Printing with the mirror option results in arcs in Print Preview
$ q; {* l. R% b1830419 ALLEGRO_EDITOR SCHEM_FTB Import Logic with 'Overwrite current constraints' deletes attributes from drawing
- k1 L$ H7 H- [! R. v1935253 ALLEGRO_EDITOR SHAPE Compose shape command causes tool to stop responding
3 m- l" v( Y% [- E3 S4 `2 ?1571600 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016
$ G$ M% r! E! h0 S1650403 ALLEGRO_EDITOR UI_GENERAL Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016( y( a2 M6 v1 [( B r
1710310 ALLEGRO_EDITOR UI_GENERAL 'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016
) i9 b9 q3 J) `* ~1 E1718407 ALLEGRO_EDITOR UI_GENERAL Reintroduce the Capture Canvas Image command# M; N' @" `" p7 i
1729699 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image is not present in release 17.2-2016
, {- \6 k' s# _" e+ D4 g1753234 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image missing from the File menu l( Z' S: g Z# C4 Q6 Z% k# Q
1754222 ALLEGRO_EDITOR UI_GENERAL Need command to capture view window as image in release 17.2-2016( i |* u, C; r. I9 n# O) E5 c
1794348 ALLEGRO_EDITOR UI_GENERAL Reintroduce Capture Canvas Image in PCB Editor in release 17.2-2016
$ q1 n, \2 U* ?1 J5 S8 L1818610 ALLEGRO_EDITOR UI_GENERAL Restore the option to capture canvas image in PCB Editor in release 17.2-2016
?8 d3 S+ Y+ b2 U1844591 ALLEGRO_EDITOR UI_GENERAL Reintroduce 'Capture Canvas Image' in release 17.2-2016
( Q7 U# n$ d0 Z2 C ?+ j1869380 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016; s0 ?3 d# }3 o
1889412 ALLEGRO_EDITOR UI_GENERAL Cross-probing between two boards in release 17.2-20169 P/ ^* {4 E; q
1922329 ALLEGRO_EDITOR UI_GENERAL Add the 'Capture Canvas Image' command in release 17.2-2016
$ G* c' v+ Y) y- {+ A1932070 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image is missing in release 17.2-2016
/ y( w9 {! y; p/ i; r2 @, D1885594 ASDA PACKAGER Export to PCB Layout exits without reporting error when Netrev fails
# B6 M* E2 y9 p; A* P+ m9 n1931657 ASDA PACKAGER Export to PCB Editor does not work for a project" ~8 j- {4 u- W# j- {6 u
1937757 ECW METRICS SDA metrics not getting collected
3 |* d' ~& Q% X7 _/ W# s1934482 EMI SETUP EMControl function flow is not working correctly in release 17.2-20166 P+ a% Q! B$ X/ Z8 {
1931623 SIP_LAYOUT EDIT_ETCH Shapes are not updated and force update does not work' ]& Q/ e4 B+ Q0 h8 Y
3 i5 V1 J6 H5 _3 e1 [8 o
+ y W0 Z, m8 K4 YFixed CCRs: SPB 17.2 HF041
$ \; B( m$ O; P06-9-2018
# z) L( R/ ~1 y" @' V========================================================================================================================================================
+ D) q* U' i) o" v2 }0 X# r8 yCCRID Product ProductLevel2 Title X- w0 C- j3 s
========================================================================================================================================================
% k0 y9 E+ c- |$ I: ]' E1880083 ADW ADWSERVER ALM fails to connect and authenticate LDAP server
* x. n( z. w7 }0 W1922218 ALLEGRO_EDITOR 3D_CANVAS PCB Editor stops responding when 3D Canvas is opened for a symbol# V( j% P0 T& T8 G. Y
1915838 ALLEGRO_EDITOR DFM Outline to non-signal geometry is not working for non-etch layers in design0 ?( Q; _+ M3 x: \
1925263 ALLEGRO_EDITOR DFM False minimum spoke count DRC
" {; Z1 U7 }: e, n' e" t! S1895486 ALLEGRO_EDITOR INTERFACES Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)+ J% S/ m5 h7 r' b, c5 i
1927266 ALLEGRO_EDITOR INTERFACES Miniaturization license required when using enterprise licenses# d# o9 V" |. A3 n& } D
1912186 ALLEGRO_EDITOR IN_DESIGN_ANA Coupling analysis on one net takes a long time: Q! Y( p8 S0 E6 o! X
1916015 ALLEGRO_EDITOR NC Improve the message for reporting unsupported characters in the directory path while generating NC Drill data
- R [/ ]) n5 o0 V ]1926072 ALLEGRO_EDITOR SHAPE Dynamic shape to route keepout not voiding correctly
4 c% Y8 h4 w; m! E1 J( C& ^1903202 ALLEGRO_EDITOR UI_GENERAL HTML report dialog does not handle relative links to files correctly
: P# x* [, V1 t/ l) t1880684 ALTM_TRANSLATOR CAPTURE Importing third-party schematic is not working in Capture9 A- h! S9 r/ A U
1870218 ALTM_TRANSLATOR DE_HDL Unable to translate a third-party design to DE-HDL
0 P5 D8 d* x' y' A, u1881208 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL translation: schematic symbols missing all pins
4 o+ R6 g% X, e: T) S) @1889909 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash
6 d8 f4 z/ Y% \3 M% Q1924375 ASDA NEW_PROJECT SDA new project path truncated at ellipses
2 @7 C% c# l0 J4 [- ?1900957 ASI_SI OTHER axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6
) A/ G; E( n d6 f1918499 CAPTURE NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed; S$ G2 D6 D5 d
1921505 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'6 H$ U6 R$ d1 v a. V( M1 n
1924273 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'* Q3 w% A+ G$ z7 E
1924332 CAPTURE NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'
: g! ~; k% [( ]) e1934655 CAPTURE NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
& D: ~8 [5 p. Y: O1855851 CAPTURE OTHER Crystal Reports not working in release 17.2-2016
& T$ [, Q$ j& z8 Q# \1 Z% c# p2 S1918048 CAPTURE PART_EDITOR Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor8 U8 n- C2 p* l+ k/ G$ D
1919459 CAPTURE PART_EDITOR Part Editor background display color is not consistent when zoomed out/in8 L! v( F: j; q1 [' Y- ?
1920078 CAPTURE PART_EDITOR Option needed for updating pin type of multiple pins in the 'Edit all pins' menu$ h0 |+ _1 {6 D0 y: a# q) O6 ]
1922785 CAPTURE PART_EDITOR Cannot place pin array with zero in the suffix in Symbol Editor
# \0 @4 n4 D9 F' R" f6 G1922831 CAPTURE PART_EDITOR Symbol Editor redraws when scrolling with non-default background and when zoomed out
+ t. ]; _& p: G" w. r$ `$ u ?1923772 CAPTURE PART_EDITOR Placing pin arrays results in error' ^5 j) W: Y- i* t2 x3 G7 f
1888897 CAPTURE SCHEMATICS Capture slowly redraws schematic page
1 o4 d+ K' J0 b1910087 CONCEPT_HDL CORE DE-HDL crashes when adding Current Probe to a design, A8 Q6 S! o, Y8 o* S
1930364 CONCEPT_HDL CORE SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design* L2 C( I2 c9 E1 {% L
1920716 CONSTRAINT_MGR CONCEPT_HDL Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor* D; \2 l2 u" d
1902591 ECW OTHER Flow Manager reports a digital certificate error when launched with Pulse
: r! Z0 D( M) i! Z2 }1926029 PCB_LIBRARIAN GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-20166 Q5 K o2 P2 I- p9 t+ D& u7 P2 {
1884694 PSPICE ENCRYPTION User-defined library encryption is not working as expected9 Q+ W, m4 Y' \1 d' H0 q+ Y
1927537 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
" {3 X3 K/ X5 G4 L+ m1 ?) m1878733 SIP_LAYOUT CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout
0 f" L6 t: [4 F1900628 SIP_LAYOUT CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added" \; E ~0 G$ R
) h" `$ V+ A ?
, J5 e- I( \4 z& N$ P- M' ^ Z, BFixed CCRs: SPB 17.2 HF0404 N/ R% R% W' F" Y
05-27-2018
" {6 |* s5 z( j6 K========================================================================================================================================================
+ \5 k8 U) X r' I9 c5 Q1 fCCRID Product ProductLevel2 Title
. Q6 ^8 n# ^4 j========================================================================================================================================================
3 l" W3 U2 ~ G) P2 V! O; g1924541 ADW CONF Designer Server configuration cannot be completed
E$ i' p y/ O/ I7 y4 A2 D% u: q1906973 ADW DBEDITOR Rename attribute fails to preserve values in affected parts% d+ l3 e/ b0 I- [9 ^# L
1718524 ADW FLOW_MGR FM: Find Projects does not find any projects when Project Path contains a period
) z3 C: W9 ]. z) d3 `1803310 ADW FLOW_MGR EDM Find Project no longer supports dot in the project path! a- Z4 s. t n2 l. l& ^1 H; j
1916898 ADW FLOW_MGR Flow Manager does not recognize projects with a dot in the path
# j0 r4 i7 f8 e# C! Z- L1887669 ADW LIBDISTRIBUTI ptfgen displaying Java errors% [% |. Y* U4 U, T2 `3 ~* [/ d
1897991 ADW LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.1 j! i7 Q* W9 w( p9 P
1915319 ADW LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically6 O" r- i% d5 q- l3 i- R/ B
1920309 ADW LIBDISTRIBUTI Java exceptions in the ptfgen log file
( P7 ?2 M E4 ]1 D+ D" j. r1914706 ALLEGRO_EDITOR DFM False Mask to trace DRCs
" J5 Q* ^3 i% i1912290 ALLEGRO_EDITOR GRAPHICS Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol
9 m* C" o% l; v% _7 u1927425 ALLEGRO_EDITOR GRAPHICS Infinite PCB Cursor disappear while moving objects on layout
5 \9 _/ U7 q' O1908867 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes in release 17.2-2016, Hotfix 036 and 037
. e' G0 T% e B$ V1906116 ALLEGRO_EDITOR IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
# x( e4 L% k3 N; P: `, V1918161 ALLEGRO_EDITOR MULTI_USER Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate
5 [* c/ G Q$ ]9 n1919467 ALLEGRO_EDITOR MULTI_USER Random crashes while routing design in Symphony
; c0 R' ^% G1 M$ V: l- {) k1918702 ALLEGRO_EDITOR SHAPE Differential Pair vias not voided in a split plane
- v' K- ]3 B/ d+ K0 B2 @$ M8 h1905109 ALLEGRO_EDITOR UI_GENERAL PCB Editor randomly stops responding in release 17.2-2016 in Linux
1 ~0 f9 Q5 D* z$ |+ p6 i1882365 ASDA CANVAS_EDIT SDA - body changes but not properties when changing version of a symbol7 m$ F! e, g+ d9 y1 U" |
1900370 ASDA CANVAS_EDIT Version command in SDA should use placeholders from selected version
: F. R/ J' I" ]! ^1901120 ASDA CANVAS_EDIT Choosing a different version of a placed component does not use the property placeholders as per the new symbol" b. \1 e) h% {, x" E
1907497 ASDA GRAPHICS DNI Cross Mark much larger than Components
+ `. J% E% L6 K) L) @/ ?3 T1895135 ASDA MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib
! p8 Z3 w) U: L [1895139 ASDA MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design* w8 ^1 \% l6 j# P8 l
1920753 CAPTURE LIBRARY JavaScript exception reported on opening part with name containing '\' in hotfix 038! I6 O! q: s8 p8 a: D5 O! j4 j, |) {
1925848 CAPTURE LIBRARY New (QIR6) Symbol Editor has Script error / SR 600037969* b4 t6 ^7 Q% R; A( u+ t, Y2 O! L! ?
1916991 CAPTURE NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences
) W+ G& y) U! A% Y ]1917090 CAPTURE NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button7 r0 {/ f! \; G. \0 X9 F! e6 D* v
1918041 CAPTURE NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files
% v- z- Y: w v) ^4 [1918497 CAPTURE NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor
1 Q; B7 m$ W2 H. Z0 E6 `1918711 CAPTURE NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name4 v4 M( `2 @$ S' I
1920889 CAPTURE NEW_SYM_EDITO Unable to edit symbol with name containing '/'
, j4 v. `* }" {+ Y' o4 T/ j1922123 CAPTURE NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files& n5 M3 ]# y" v# S% E+ n. i
1922276 CAPTURE NEW_SYM_EDITO Space between pin name and pin for names having bar# a6 }' X) Q0 C
1922282 CAPTURE NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts5 [% [9 z6 X: b6 @$ e M
1923526 CAPTURE NEW_SYM_EDITO Unable to "Save As" in new symbol editor.2 F3 X+ Q4 `0 Z3 y9 \
1927262 CAPTURE NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions
% Y) Y7 D1 [0 e, M/ W9 B& _6 [# l1919322 CAPTURE PART_EDITOR JavaScript exception on opening parts and creating new part using right-click
6 N" ^% @6 w% m& G# ?! `1 {1914183 CONSTRAINT_MGR XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL
s& L* U7 T9 O y# Y: p% y1908102 ECW DASHBOARD Some lines in Design Dashboard in Pulse are grayed out
' `- f% |' o! d2 M1914812 F2B PACKAGERXL Hierarchical variable not evaluated
9 y* V, l2 R( C" E2 i w1639231 PSPICE ENVIRONMENT Remember last location in simulation settings
( B( [2 q; w+ u% E; C1804391 PSPICE ENVIRONMENT Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'1 ^; R( X5 l. N# E8 P
1879915 PSPICE ENVIRONMENT Check points cannot be loaded from a directory with space in its name
6 C6 N0 z' f) p5 b+ Z1695306 SIP_LAYOUT STREAM_IF SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer+ r: G5 ~" Q* i5 {
8 @- e9 i! ]8 x7 R4 c; Y
0 u. f4 y0 u/ R5 Z5 A1 ~; F1 ~! _$ aFixed CCRs: SPB 17.2 HF0399 `: E: T. ?3 H$ K# z ?3 b
05-11-2018, f. v+ s# V- l( k. j. j
========================================================================================================================================================: M+ K% L" K2 d" C; V$ Q! ~2 W
CCRID Product ProductLevel2 Title
# N: @# l+ O! j- O========================================================================================================================================================
: K/ x: Z2 x% H( b' U; O1915149 ADV_PKG_ROUTER OTHER Auto-connect fails to initialize when rats are selected, but works with bundle
* O, t$ r! N+ L% F& K' L1870109 ADW ADW_UPREV Most mandatory properties turned into optional properties following database uprev) H. V# o! {9 y* L* Z7 x6 b
1758396 ADW CONF Server Memory setting in setting.ini is lost if server is re-configured using Conf% ~6 h2 }, R- S1 [7 `; X3 E
1911591 ADW FLOW_MGR Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog4 B# b4 R6 h8 y3 n8 }, g9 k2 j
1887861 ADW LIBIMPORT Library Consolidation reports front2back issues but does not provide information about the issues.
. H5 r$ j: f s Q" s1778977 ADW REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure( O6 o3 z! E Q
1900422 ADW REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
, f1 M4 E! g- m2 u1903888 ADW REPORT_GENERA Report generator not outputting values as expected for PPL field
E4 h7 k" d- }# U- ]( B# C1916903 ADW REPORT_GENERA Reportgen -gui is not producing the expected result9 ]/ n, N' D. f& }, Z
1902184 ALLEGRO_EDITOR DATABASE Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable; a7 L/ M" x8 l* Q) g0 r
1914793 ALLEGRO_EDITOR DATABASE Updating shape crashes Allegro PCB Editor
* [6 O5 J) D6 D1 D( {8 s" f1905138 ALLEGRO_EDITOR DRC_CONSTR Max Via count DRC disappears on running DRC update
: J9 T! I7 ~8 M# k1 ]" {( F3 X) m1848015 ALLEGRO_EDITOR MANUFACT Export Creo View cannot find the webpage on the PTC site0 [ v4 G1 [9 ]% |; P+ p. Z( G" I7 N
1850553 ALLEGRO_EDITOR MANUFACT 'File - Export - Creo View' is not working
( s/ O$ e, B- n- a4 w1853960 ALLEGRO_EDITOR MANUFACT PTC Creo Interface link is broken
0 ^2 c; ?5 l, ]1862305 ALLEGRO_EDITOR MANUFACT PTC Creo interface link is not working8 Q+ Q2 E- R, x9 u% U3 s1 X) A% j
1878682 ALLEGRO_EDITOR MULTI_USER Delay in Symphony server session when server is started from Allegro PCB Editor' e+ V/ @* O2 c" D4 @8 |- W# m- }
1890108 ALLEGRO_EDITOR MULTI_USER Database rejections in Symphony
# u4 r4 _5 _0 d+ l) a) q. s1887331 ALLEGRO_EDITOR NC Milling (NC route) in Gerber tools is not the same as what it is in the board.
1 v2 }: X5 P% M. y9 o1 n* e1898179 ALLEGRO_EDITOR RAVEL_CHECKS PCB High-Speed option required for high-speed rules when Venture license is selected$ v7 }4 M( y/ D, w# K9 {
1461142 ALLEGRO_EDITOR SHAPE Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.
2 Z# x% r! W1 ]3 a) P1863467 ASDA CROSSPROBE Highlighting all parts in PCB Editor does not highlight all parts in SDA$ U0 v% J: E' _5 i. \
1910974 ASDA CROSSPROBE Cross-probing between SDA and PCB Editor does not work- K4 S! h. Q/ R1 q# `* c
1904440 CONCEPT_HDL CORE SPCOCD-577 error on migrating from release 16.6 to release 17.2-2016
1 b$ w- T7 D& Q& U6 D- Q$ p1909611 CONCEPT_HDL CORE DE-HDL stops responding on running '_movetogrid' and clicking 'No'
! ^/ `2 [7 }- V9 [( r1 O$ v1808743 CONCEPT_HDL PDF Inconsistent display of Publish PDF hyperlinks1 p: B, ~" x' P. l k7 B! r
1894868 CONCEPT_HDL PDF XREFs getting clipped in the Published PDF
, H* i- ^* f0 o3 e* W9 D1911676 CONSTRAINT_MGR CONCEPT_HDL DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option
' C; n% Y* `4 B7 b8 x: m( ] [& T1913968 CONSTRAINT_MGR CONCEPT_HDL Match Group pin-pairs are not created on applying ECSet to differential pair
. _1 I) ?2 h8 {8 M9 _1899638 CONSTRAINT_MGR XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6
" }: H1 V! O( ~! Y8 Q. M1914116 ORBITIO ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout2 z6 \- ?, v4 z$ |( P8 B
1896487 PCB_LIBRARIAN GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor
+ f/ ?8 ~6 K. D& p) o1898008 PCB_LIBRARIAN SYMBOL_EDITOR Styling is not available for custom shape and pins.# `; E0 J! N9 E' r5 u! u
1644787 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path/ X0 q" l$ |# F" C* P, W
1785939 PSPICE FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories3 ]7 l- F; Z/ M" s1 U
1855867 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path' i" f! F3 ]1 N+ Z. X
1887016 PSPICE SIMULATOR Pseudotran should always be invoked first time in case autoconvergence is ON; `. Q+ l( S3 r' \% h% ^
1895752 SIG_INTEGRITY OTHER Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions
: g6 Q/ Z8 Z& {3 Q. l5 S: |9 i1895759 SIG_INTEGRITY OTHER Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value% v2 b& F4 {9 `0 `/ J6 D
1909257 SIP_LAYOUT INTERACTIVE Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols
2 J2 u: g" f/ g# O+ N/ l! n1900970 SIP_LAYOUT SHAPE Shape does not void around SMD Pins and Vias inside pad9 h5 v' V3 H' J/ ^ H" V: m
1885496 SIP_LAYOUT SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.1 ~( D1 C7 x6 t l- H
1907796 SIP_LAYOUT SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout: Z8 m/ r5 J! b& A2 T- ]7 v$ f
1887703 SIP_LAYOUT WIREBOND On trying to add wire bond to a die, SiP Layout crashes displaying a restart message
) T* u. d& W! q" ~- Z) j4 n5 G/ w( s1903081 SPECCTRA LICENSING PCB Router is failing in Linux 7.1 in release 17.2-2016
6 Q0 b$ U" K2 T; d2 N0 n: X1721606 SPECCTRA ROUTE PCB Router stops responding on exit if opened in the stand-alone mode$ h B, o" ]' _/ f8 X
1844366 SPECCTRA ROUTE Allegro PCB Router will not exit
# R1 D" \- L3 E0 X# [1 }1 I1873716 SPECCTRA ROUTE PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode
- a# |: ^' m) x1 f8 f* }1907703 SPIF OTHER PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-2016
5 p1 z3 Q/ ]1 r1 D8 V# q& f# ~1889059 VSDP DIEEXPORT Incorrect pin location if bump cell origin is not at lower left for rotation other than R0
" F q, F; y$ V3 D4 ~# E9 i& i" Q" u6 @. o1 r0 Z) N
% j6 @, o) S A1 ~) R& wFixed CCRs: SPB 17.2 HF038" {1 E( A1 g% o* d8 Y
04-27-20185 A# _1 L K* ^7 x9 h
========================================================================================================================================================+ k+ C3 Q7 @9 h5 k
CCRID Product ProductLevel2 Title
! J2 a- z# c+ m; B+ `. z4 @$ O& Y1 \========================================================================================================================================================
I- B' s0 m, O3 d1861616 ADW TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature
0 m5 ^( C5 N* g1784170 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show the flex zone thickness correctly$ w h0 `' q( ^/ O; F% z& B
1801053 ALLEGRO_EDITOR 3D_CANVAS Moving component in 3D Canvas does not move the pads
1 }6 ?3 Y7 o; l0 e3 i$ t1805038 ALLEGRO_EDITOR 3D_CANVAS Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open- P) F" C, I( z- j; b b
1808579 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas displays annular ring incorrectly2 K+ |) M- W+ b1 b2 d2 H
1816732 ALLEGRO_EDITOR 3D_CANVAS Mismatch in shape width between board and 3D Canvas
( c$ f4 ?/ C+ e; e1 h, r2 E6 p1822778 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas does not display nets when selection is done through click drag
# W. |1 W' D* T+ H7 S1838129 ALLEGRO_EDITOR 3D_CANVAS User is not able to create a pastemask layer that is visible in 3D Canvas1 q3 k f+ w) U
1842911 ALLEGRO_EDITOR 3D_CANVAS Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing
! ]% N" Z% y: q1849380 ALLEGRO_EDITOR 3D_CANVAS Mirrored components placed in flex zones are not displayed in the 3D Canvas
! D2 W6 `, e9 ?; S2 V1851898 ALLEGRO_EDITOR 3D_CANVAS STL export from 3D Viewer scales it up by 100
7 j6 ~$ H+ f. h1853378 ALLEGRO_EDITOR 3D_CANVAS The new interactive 3D Canvas has a display issue with the off-centered drills.
9 F2 s$ d% r, h/ H& Z1859713 ALLEGRO_EDITOR 3D_CANVAS PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas
I6 H$ R4 F* B6 x1880073 ALLEGRO_EDITOR 3D_CANVAS Design Outline is not displayed correctly in 3D Canvas
, |7 X5 D. H; c1880338 ALLEGRO_EDITOR 3D_CANVAS Step Model missing in interactive 3D canvas.
$ i" w6 \7 c& N% R, y, \! n/ R7 ~$ Y1881889 ALLEGRO_EDITOR 3D_CANVAS Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.
* @* v) R- }' e8 O1 H1889861 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas swaps padstack from Bottom to Top5 c& }9 F7 j, |. [' h# U* C/ e
1830749 ALLEGRO_EDITOR ARTWORK Gerber 4x and 6x output do not fill the shape
9 v- x% H7 a4 f" R, B1848514 ALLEGRO_EDITOR COLOR axlVisibleDesign does not interact with wirebonds
]/ o, ?3 _4 U6 h, W, G1837388 ALLEGRO_EDITOR CROSS_SECTION Cannot add solder mask to the site layer mask file
" \* o2 h6 J# |+ n+ R1859797 ALLEGRO_EDITOR CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC2581; E* L' W ]8 y# _6 j4 x
1877858 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
0 {5 D2 t& q/ r+ |/ C1880093 ALLEGRO_EDITOR CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section
, @: H, i5 z' o! J' y v1886283 ALLEGRO_EDITOR CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'$ ]8 w% c% u9 `2 N6 d
1890959 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
% m B4 o) z+ @# C2 K! {) H1900397 ALLEGRO_EDITOR CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.
2 R c p/ S9 a( ^3 ~) r3 g O1905315 ALLEGRO_EDITOR CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.2 k8 b9 ]3 F& A# @9 q# b
1861406 ALLEGRO_EDITOR DATABASE Refresh symbol for flex zone not mapping padstack layers correctly
/ f5 v$ z# l) L. O( S7 z1877132 ALLEGRO_EDITOR DATABASE Fail to open #Taaaaed17598.tmp file and save database$ E5 \/ M3 f5 O: \% A4 d ^
1883747 ALLEGRO_EDITOR DATABASE PCB Editor crashes on stackup modification b0 I; `( y7 i1 @0 B7 k! C, i' `; l
1860238 ALLEGRO_EDITOR DFM Applying a DFF constraint set closes PCB Editor instantly
; [) j( ~1 t L# h% ^1872780 ALLEGRO_EDITOR DFM DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad% r4 y$ C( Z, |5 y% ~7 q) w
1823912 ALLEGRO_EDITOR DRC_CONSTR Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)
) |- i( i& Y$ i) i9 P1828168 ALLEGRO_EDITOR DRC_CONSTR Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints" O/ ~9 J, q& }7 g( Y
1844780 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to Shape Air Gap value is reduced when updating shape
3 ?6 H, K+ l9 `6 J' f/ o1845011 ALLEGRO_EDITOR DRC_CONSTR When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly
) ?) |9 _. o* q2 q- N* u) t7 O1861548 ALLEGRO_EDITOR DRC_CONSTR Inconsistent Micro via to Micro via drill to drill overlap DRCs& U% c+ H" q; L4 c: i
1862281 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin/hole to Shape spacing too small
$ u$ B; o1 R, x* Y% C |1887145 ALLEGRO_EDITOR DRC_CONSTR Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016! c C+ c4 o' E; V1 i" e+ O
1893012 ALLEGRO_EDITOR DRC_CONSTR Shape voiding not taking the shape to hole spacing rules for NPTH+ o0 s a2 Q0 `8 e0 t
1906840 ALLEGRO_EDITOR GRAPHICS Context menu stays when PCB Editor is minimized.
, U9 b5 h+ F; c, S7 v9 H& B3 z1738624 ALLEGRO_EDITOR INTERACTIV 'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied1 J9 m' ?8 C: o; w8 x
1800741 ALLEGRO_EDITOR INTERACTIV Search in User Preferences Editor is giving incorrect results- |; ]- I$ q8 e! i( R# N
1812530 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes when opening a file that is in an unsupported format, h6 ]3 P, t, ?' ]$ T! c
1812570 ALLEGRO_EDITOR INTERACTIV PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode
% ]) M8 i7 Y" }! o& I1826819 ALLEGRO_EDITOR INTERACTIV 'Route - Resize/Respace - Align Vias' menu is not available
4 D2 n- V% X9 {% M5 K" R7 N, r) L# C1842645 ALLEGRO_EDITOR INTERACTIV Via align command is missing from the menu path
4 }9 V% |! ?6 D; V) M1 {: K; g1845748 ALLEGRO_EDITOR INTERACTIV With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper.4 H3 }' r! z1 O0 L, F. k" G5 ]
1849700 ALLEGRO_EDITOR INTERACTIV Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
; K( a+ w- s1 |7 b5 b1860934 ALLEGRO_EDITOR INTERACTIV Auto-Paste environment variable is not working as it should X P; N- u: L1 ]
1861928 ALLEGRO_EDITOR INTERACTIV Provide a Persistent snap pick option for Display - Measure
5 I* g: u8 l8 E1 x1864238 ALLEGRO_EDITOR INTERACTIV Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action' d6 ], N) E) M$ Q0 M
1877026 ALLEGRO_EDITOR INTERACTIV Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied3 f" r k/ @7 b4 u6 b' z
1881637 ALLEGRO_EDITOR INTERACTIV Radius of Shape changes when trying to place circle using Place Circle mode.9 H4 E- t1 `; c- Q5 v+ X
1883032 ALLEGRO_EDITOR INTERACTIV Find by Query does not find all padstacks in a symbol drawing {& \& \, K- C Z
1855248 ALLEGRO_EDITOR INTERFACES The Technology Dependent Footprint command returns an error
x' R' m# W+ |$ c1885716 ALLEGRO_EDITOR INTERFACES Increase supported STEP model size to enable the use of models larger then 500MB" J- v- s# ]; ]5 o
1860835 ALLEGRO_EDITOR MANUFACT Display a message when backdrill_max_pth_stub is defined for vias or pins only/ H; _2 o$ w1 F) A# w
1869528 ALLEGRO_EDITOR MANUFACT Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop
# R- E6 U& E( x' y# {1885672 ALLEGRO_EDITOR NC NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
6 ~& d4 @7 L" j: s# o# z) O1895084 ALLEGRO_EDITOR NC Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling
U! j3 n; Q$ x( g( n4 C2 x6 W1837514 ALLEGRO_EDITOR PAD_EDITOR Offset is not consistent for keepout and mask layers in padstack editor.
6 m+ u# w4 u0 H& ~; K) x5 ?( D1842902 ALLEGRO_EDITOR PAD_EDITOR Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)3 q& Z) k2 T, b
1846504 ALLEGRO_EDITOR PAD_EDITOR COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
4 T d# T5 E* x+ k2 _7 ]1879453 ALLEGRO_EDITOR PAD_EDITOR The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.
! h: _( H# E. n: v+ D2 f9 p9 G+ k* T3 ~1805202 ALLEGRO_EDITOR PLACEMENT Place via array adds via on differential pairs incorrectly) t/ w* \% B5 H
1806675 ALLEGRO_EDITOR PLACEMENT Place - Manually - Quickview displays the Assembly Top details only3 Y* O5 h1 B% v- L2 p* _$ }1 y; ]
1835177 ALLEGRO_EDITOR PLACEMENT Can place symbol even after cancelling copy by choosing 'Oops' from pop-up+ \' \* @( e" l1 @& _
1846892 ALLEGRO_EDITOR PLOTTING PCB Editor Export PDF does not show lines correct for certain component
* [" h" ^/ F3 z5 e. H# h% B1006328 ALLEGRO_EDITOR SHAPE Static shapes should void around corners as dynamic shapes do+ [8 m2 g6 q* Q" g, Z
1033326 ALLEGRO_EDITOR SHAPE Cannot compose lines to shape- I" G( _/ b8 h) Y2 W
1045089 ALLEGRO_EDITOR SHAPE Dynamic shape voiding is inconsistent for solid and xhatch shape fill type
) @; `4 R3 |8 A1069959 ALLEGRO_EDITOR SHAPE Compose shape crashes PCB Editor4 f% S2 c7 p8 Q
1085907 ALLEGRO_EDITOR SHAPE Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.7 L- v+ M) v6 p% g0 R7 G0 V# X
1143563 ALLEGRO_EDITOR SHAPE The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.' o, x/ A$ j9 Y* B
1243688 ALLEGRO_EDITOR SHAPE shape_rki_autoclip fails to clip shape to route keepin
* t; i3 `/ \- j" }9 L. d- V. S# D1269069 ALLEGRO_EDITOR SHAPE Shape void not working properly in release 16.5 hotfix 054
' u* `$ j. `2 A$ e* f1327755 ALLEGRO_EDITOR SHAPE Need the ability to nest dynamic shapes on different nets partially or entirely
# G3 K- `8 t( o" |. Y* u1417394 ALLEGRO_EDITOR SHAPE Shape not updating correctly7 d, u5 d1 _, ~8 t$ w6 l1 S
1430742 ALLEGRO_EDITOR SHAPE When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped
0 \, x1 `* J1 t! j- ]1750760 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC for a void that meets route keepout& V6 S. |/ P" W' h
1793898 ALLEGRO_EDITOR SHAPE Add teardrops fails to add anything with different settings
- |* o3 {0 U. x& y" T) U$ o1811662 ALLEGRO_EDITOR SHAPE 'show measure' gives incorrect air gap value between two pins
3 `- B' r9 I* ?- p9 ^& v: W4 W1820901 ALLEGRO_EDITOR SHAPE The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks8 U. f1 v7 T$ T# u; V' S
1829570 ALLEGRO_EDITOR SHAPE Display measure airgap value is very large6 z3 O5 G5 t, ]* k8 d
1858696 ALLEGRO_EDITOR SHAPE The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added5 c$ R4 o: P, S7 n1 h: S# X
1873384 ALLEGRO_EDITOR SHAPE Boolean AND operation returning nil1 c- ~0 D: }; F' g
1873860 ALLEGRO_EDITOR SHAPE Copper shape does not respect route keepout- }% d7 L. C2 r+ H/ C0 t
1889312 ALLEGRO_EDITOR SHAPE Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression
; S5 m/ E7 c" |4 n! P1890702 ALLEGRO_EDITOR SHAPE Not able to add teardrop in release 17.2-2016& |3 |- n4 E- G( n: m6 T
1892692 ALLEGRO_EDITOR SHAPE Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes3 \% `0 U# T, y+ }. \* m9 Y
1893492 ALLEGRO_EDITOR SHAPE 'merge shapes' results in moved void1 [2 }$ m$ T0 @
1896543 ALLEGRO_EDITOR SHAPE Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef
( n O- n1 I4 z1 A' ~1897645 ALLEGRO_EDITOR SKILL axlCNSGetSpacing() returns nil if active class is non-etch.8 }2 m* L3 z9 w6 y A
1822364 ALLEGRO_EDITOR UI_FORMS Design Parameters dialog disappears if prmed is called while show measure is active
5 o7 A# O- [+ `) S: w- G1834395 ALLEGRO_EDITOR UI_FORMS Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command
7 H' e: c* W6 v+ s1838941 ALLEGRO_EDITOR UI_FORMS Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
; P6 M4 B/ ?8 ^! s8 Z5 w1716433 ALLEGRO_EDITOR UI_GENERAL Alias keys do not work until mouse scroll key is activated
6 ^* ^0 C+ [4 K" n4 d% d1721761 ALLEGRO_EDITOR UI_GENERAL During manual placement of symbols, hovering over symbols does not highlight them! f+ ]4 n; l0 S, i2 k1 V
1732915 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows' u1 U/ y! K9 A4 F2 f3 U
1770723 ALLEGRO_EDITOR UI_GENERAL Funckey does not work if focus is not on canvas in release 17.2-2016
# C7 l1 M; Y2 `4 h1793839 ALLEGRO_EDITOR UI_GENERAL Function Key does not work if a form is opened by a previous command
, F$ B/ T$ q1 h5 t" y$ @1813961 ALLEGRO_EDITOR UI_GENERAL Inconsistent file formats available when saving reports
# K$ Q/ N$ c1 |1 q1 b1816716 ALLEGRO_EDITOR UI_GENERAL Shortcut not working when using working layer with 'add connect'
% v; K& o5 Q7 H& N1864321 ALLEGRO_EDITOR UI_GENERAL Funckeys not being registered after focus has moved to other window and back again in PCB Editor
8 `" j1 d# ]1 [, h% W3 D* r0 d+ ]1865010 ALLEGRO_EDITOR UI_GENERAL PCB Editor does not get focus when clicking shortcut after switching from any other program or application
: I8 l, K) N" {( h1868708 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 0325 c9 F7 S9 \/ ~3 K! T. i
1869745 ALLEGRO_EDITOR UI_GENERAL Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar; W5 s& V) F5 w4 @# u0 {
1869860 ALLEGRO_EDITOR UI_GENERAL Hotkeys no longer functional on switching from PCB Editor to another application and then back again
3 c$ U8 M7 z6 a3 {1870744 ALLEGRO_EDITOR UI_GENERAL Need html extension added to Save pull down menu.$ `9 } ^: K( u2 D2 s
1870996 ALLEGRO_EDITOR UI_GENERAL If you switch from one active window to other, hotkeys stop working
0 c' Z- B% L3 S% j$ C1883507 ALLEGRO_EDITOR UI_GENERAL Hotkeys stop working after Allegro PCB Editor UI window is opened; G5 s/ H1 ]) h8 Y4 s, v/ Z! M5 T
1886981 ALLEGRO_EDITOR UI_GENERAL Focus lost from layout when switching between PCB Editor and Capture& ^( P3 A! ^ G' Q7 i! z2 A& N
1887519 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly M1 d* H% c `
1887660 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows.0 b5 V1 w: f2 n. f R
1891204 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes if SKILL form is closed using the Close icon ('X'); u6 k6 X Z+ K! @! S
1898059 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working consistently in release 17.2-2016
+ t7 ?! V- {" Z; J3 ~: B2 M' k1902322 ALLEGRO_EDITOR UI_GENERAL Cannot use funckey commands when cross-probing: ?, Q, E! L& p0 R* R+ `9 U
1905906 ALLEGRO_EDITOR UI_GENERAL Issue with keys and focus when navigating between windows
( H+ c; q/ h6 q. D1913768 ALLEGRO_EDITOR UI_GENERAL Uppercase funckey shortcuts do not work
( I. T# @# t$ q1 `8 w1751586 APD OTHER axlGetMetalUsageForLayer() for etch returns value including pins and vias
$ [, B8 {* ?+ s2 o1863241 APD SHAPE Fillet is left on the T-Point without Cline(center) connection.
3 \0 C" K. g1 X5 Z4 ^' Z1894438 APD STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS4 S' [, n2 a$ M. z9 g6 j! ^: h
1812699 ASDA AUTOMATION Enhance the performance when extracting data from SDA, using TCL functions
. L) y+ L/ Q8 r. {( s0 I1863436 ASDA CANVAS_EDIT alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement$ y a' _4 c; h# F
1863445 ASDA CANVAS_EDIT Dark theme blue text in docked CM needs to be of a different color: difficult to read- V# w% T3 K6 f# l9 P1 r
1802111 ASDA DARK_THEME Dark theme in SDA should also change the border line color and text color of grid references: they are still black
0 d/ p& C3 T" T6 j* z5 Z1869951 ASDA EXPORT_PCB File browser button in Export to PCB Layout flashes graphics of the window behind the form
4 D, Q. a" F" i6 [+ k1845831 ASDA FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly7 e4 b6 M. v9 I5 \% H
1879914 ASDA INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value
- e) d2 A$ [6 @1 E- v7 |1865753 ASDA MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box
8 j; |$ |) Z- E1863457 ASDA PACKAGER Unset all user-assigned references globally: |% {' H* P0 O) H5 j
1889301 ASDA TDO SDA TDO Crashes when switching to/from Offline mode7 W! b% i- M- p' S, {
1823203 ASDA VARIANT_MANAG Variant setting part to not present does not do anything
. g) `' V- x# s1823992 ASDA VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC
" Y+ V% B) w+ T1863451 ASDA VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset
9 b/ D! h5 \% C# o( @+ e1863455 ASDA VARIANT_MANAG Cannot resize any panels in the Variant mode
% A) B: q4 I+ D [1 i% O2 e4 \/ H1874952 ASDA VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be white for readability
; n, J" m' a2 {% ~1878401 ASDA VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red
* T1 B K3 b/ r3 ^7 n1877239 ASDA WORKSPACE SDA DRC window is hidden if undocked and minimized2 g* d$ T0 N. F& ~- J# T' I
1809605 CAPTURE LIBRARY Part has pins in the incorrect order in the Connectors library
0 z- K6 q* J0 M$ F) `( G/ B0 q1638693 CAPTURE OTHER Capture Footprint Viewer not showing footprint.4 c4 E1 v' r- z% A, C
1873612 CONCEPT_HDL COPY_PROJECT Copy project causes nets to be added to net groups and ports - fails to package due to mismatch
+ ]3 X4 k* s3 j$ n; U5 b& \8 v1779289 CONCEPT_HDL CORE Adding a component and wire and saving the design results in a 'Connectivity save failed' error
. [4 H3 ~# a3 E! s: a* U1878719 CONCEPT_HDL CORE Cannot enable or apply block variants at the top-level in a hierarchical design.
8 Q7 K3 l; l/ o( d/ ]3 a1865480 CONCEPT_HDL OTHER 'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml7 [* s4 g" Q1 h9 o
1829966 CONSTRAINT_MGR CONCEPT_HDL DML independent flow: Export Physical audits missing signal models in release 17.2
9 R+ U9 I% a3 {% c) ]6 }1904458 CONSTRAINT_MGR ECS_APPLY 'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037- Y# s# n* p9 m5 M
1798269 CONSTRAINT_MGR OTHER Script changes '-' in layer name to '_'+ D9 O( r) h4 u/ D
1835520 CONSTRAINT_MGR OTHER Cannot add members to netclass name with parenthesis0 P0 J3 ~+ M A; [" h8 `0 E5 W
1896638 CONSTRAINT_MGR OTHER Constraint Manager worksheets jump abruptly
4 L/ F: G4 S* r& G" j& P1801938 CONSTRAINT_MGR UI_FORMS Add To Netclass window: Focus not on ClassSelection
0 S7 b0 |7 }- p' w) _1854060 CONSTRAINT_MGR UI_FORMS Using the tab key in the Manufacturing workbook jumps a cell/ L/ @' l2 I$ k0 w; h3 n+ P+ j6 j
1881832 ECW ROLES_PERMISS Adding Users in SSO environment using PS is error prone
$ D5 i2 {- O. [1 W# g4 G1864870 F2B BOM Incomplete BOM report generated4 U0 D6 Y& Z" Y0 r( i. [) X3 ~. U
1846578 PCB_LIBRARIAN GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules2 ?: z6 U" |* ^3 U9 a. H
1854080 PCB_LIBRARIAN METADATA con2con needs to support special characters in Primitive Name4 ^# c9 n! \1 s# {) [
1796377 PCB_LIBRARIAN SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor3 a* e/ G; h0 V4 ~0 V6 R4 E* _ B
1839692 PCB_LIBRARIAN SYMBOL_EDITOR Properties tab grayed out in Symbol preview window# k9 W) F$ P, ~8 |
1865657 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change symbol properties using the General tab3 c; R# ?% a/ Y3 }
1906888 PCB_LIBRARIAN SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.6 h( B6 A; d, W: @! L$ }
1891248 PCB_LIBRARIAN SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL
% n1 O6 U# D( Z6 R% t3 I" Z1908381 PDN_ANALYSIS PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016/ Q' z2 r+ X; \4 I4 M7 ]3 ~
1825087 PSPICE AA_OPT Graph view menu does not appear when we use 'Curve Fit' in Optimizer.
0 B0 v3 |% o$ k! ~: d9 i, g& N7 f1808091 PSPICE ENVIRONMENT 'orSimSetup' crashes when 'Restart Simulation' is selected; X) Q: M9 `8 {% b5 c
1811782 PSPICE ENVIRONMENT Setup Simulation Profile no longer enables Advanced Markers when appropriate) ~+ m2 ?- \' ]' [
1834147 PSPICE ENVIRONMENT PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016
0 T1 v/ f* [5 j1841992 PSPICE FRONTENDPLUGI Getting a blank Error dialog while adding a marker* L. J8 _, l. w
1858574 PSPICE NETLISTER PSpice simulation: Some models cannot be used after upgrading to release 17.2-2016- `- k+ x( _/ K9 O7 F
1865022 PSPICE NETLISTER The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016
/ j4 E' R- A. y1 B" q1677119 PSPICE PROBE PSpice crashes when plotting simulation message summary) e# Y4 u7 J0 ]* _
1837046 PSPICE PROBE On Windows 10, PSpice crashes on clicking Yes to see message
) R* I# f! Y8 W1879387 PSPICE PROBE PSpice crashes when we choose to plot simulation message summary
4 O1 @, v' ~' \/ l2 M* e1 n# S$ K4 J1842231 PSPICE SIMULATOR Wrong results in PSpice Advanced Analysis for DC Sweep Analysis- g1 k$ ^8 S# a, O
1843446 PSPICE SIMULATOR Distribution type is not showing under Assign Tolerance window for transistor2 l* v: Z4 k5 u# X$ u
1872630 RF_PCB ROUTING Transition taper length does not work in route- Add RF trace% w' N( A3 e) C f2 J( |
1872636 RF_PCB ROUTING Inherit Width parameter in Route -RF trace only uses width of one side4 X7 k8 U) b0 S) E8 Y
1872644 RF_PCB ROUTING Regression RF trace: change in trace width not retained while routing
& S( H2 D6 g3 c& z1901201 SIP_LAYOUT EXTRACT extracta is not retaining custom layer names
8 b! C; x9 W1 U$ T" |; P. `1813380 SIP_LAYOUT OTHER Layer Compare is not adding the required shapes# R" N/ R3 v) t" f# q
1852762 SIP_LAYOUT OTHER Error generated in Package Design Integrity Check when adding soldermask to my design( `" }0 h2 m ^8 E9 g6 P/ K
1886847 SIP_LAYOUT REPORTS Incorrect metal area in metal usage report
( i% f8 ]- f# E* @* \7 Q1491315 SIP_LAYOUT SHAPE Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command8 W. k) Q4 X5 Z2 M1 w
1853989 SIP_LAYOUT SHAPE 'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally! r+ {, b6 s$ K# s! e
1868509 SPECCTRA PARSER Autorouter takes long time to invoke
) u4 m& a7 d; Z* T% C' Y1869317 SYSTEMSI ENG_PBA SystemSI PBA does not align correlation waveforms correctly on Linux platform, Z3 E3 V, M) V1 Y7 |
% j$ o9 l2 v- u. i2 U% t( q; d) b( J: Q" {7 |/ R% f) |, d8 `
Fixed CCRs: SPB 17.2 HF037
2 a. B3 w1 |' W2 M8 F$ m& \" V03-30-20189 a) g/ q( S ]8 G1 C! ~4 S4 w$ q* E
========================================================================================================================================================# K& A0 }* e# r
CCRID Product ProductLevel2 Title s! D$ u0 ^& b' m1 Z# V# o
========================================================================================================================================================# `$ X+ L I$ r$ u, g. @
1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016; D9 ~" H1 M% e$ ^, {- [
1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
1 q/ Y$ Z% r1 F2 A0 g5 y7 N' Y6 S$ `1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
# S) v: }2 [ w1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution/ q2 P4 C2 u2 ^* o* C( @6 A
1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design
! E* P7 _3 U" ~' H5 @1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined
" X; ]1 x' N: k0 O3 V) F1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes; C) O* R4 o/ V4 l# R
1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement
! K; L' O/ {+ k& Z6 Y! }1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly
" p1 [: g: T" n- i4 m3 G1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design& W9 L% P7 d/ j0 U, o
1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016# k% p, N0 t J$ x/ w" {
1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct
& P; x. j. R$ W1 y/ E: ~8 U1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL
! P/ M: w/ r# R$ T1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology8 I* t/ x7 M! T, L# K& R8 }
1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2
" b# s I2 o; m9 j1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow: m0 O& q" P" h: ^* \% U b
1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow1 B) _* B) O7 _$ S; H$ O& t- u
1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero
: Y6 W9 D3 |) H( M, X4 N. A6 f% Q% I8 j
7 ^0 R! j9 K* d: G4 h
Fixed CCRs: SPB 17.2 HF0366 s" h( J3 R1 V$ C/ e, [6 n' @8 H' I
03-16-2018! z1 p, R: j6 ?) [0 F1 _
========================================================================================================================================================7 X" ^) }/ u& d+ ?6 t) r
CCRID Product ProductLevel2 Title
1 B9 O% x, q3 d1 o$ w========================================================================================================================================================
& p& H* Q, E; S1880209 ADW DBEDITOR DBEditor quick search is resetting the check boxes in the Attributes tab3 Z; a9 j( D3 x" }# T: f# H
1880376 ADW DBEDITOR Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.4 M7 [3 B& ^7 c& h6 E
1855444 ALLEGRO_EDITOR DATABASE PCB Editor crashes on creating MDD files after deleting subclasses
/ U5 R* m; ]5 v2 W7 _" `8 m1 @1863478 ALLEGRO_EDITOR DATABASE PCB Editor crashes on a specific machine when loading any .mdd file
! d. t, |* z* J( a W1875544 ALLEGRO_EDITOR SCHEM_FTB Constraints are getting removed: t( |" _2 e$ [+ x/ V1 {1 u$ T
1719683 ALLEGRO_EDITOR UI_GENERAL Incorrect display when using infinite cursor.
" I3 }8 u0 A5 I" e: l( W: w3 b1765989 ALLEGRO_EDITOR UI_GENERAL Selection window does not work correctly with infinite cursor option checked# M- G7 A0 e1 K" m2 o, w t! S* @
1885667 ALLEGRO_EDITOR UI_GENERAL Infinite cursor is not working correctly: e: g+ ?2 }% @9 u
1873954 ASDA IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project0 Y* k# _. u' H' [
1873883 ASDA NEW_PROJECT SDA: New project from DE-HDL creates blank Page 1% A0 d6 k5 w6 B! x7 o6 e
1852036 ASDA VARIANT_MANAG Design with variant cannot generate a variant BOM
; h3 q: V& |' Q6 o' {1875549 CONCEPT_HDL CORE Incorrect PART_NUMBER/VALUE properties on schematic' R+ H, e* M i3 [
1881848 CONCEPT_HDL OTHER License issue: Cannot open Allegro Design Authoring and unable to choose options and features
9 Q& ]4 R c4 i7 I, u1872189 CONSTRAINT_MGR CONCEPT_HDL Pin-pairs are created for incorrect members of differential pair after ECSet is applied& j( _2 Y/ n( g) @
1880235 CONSTRAINT_MGR UI_FORMS Ability to lock auto-generated Constraint Set in UI
. d6 ]- C. Z3 Z" t* [( E1868711 CONSTRAINT_MGR XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow
- l' [! g4 `; m* G: \1879296 ECW PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys k5 B# F) _" k& ^5 h
1881632 PSPICE SLPS PSpice creates 'psp_input.log' during co-simulation flow4 G m* J7 P& `
1879302 SCM OTHER SCM crashes when global nets are changed in the Block Packaging Options dialog box; T8 h# a/ K: A% F# }9 N: Z
1879580 TDA SHAREPOINT GetData error when opening a project in Design Data Management3 J# p! n7 l2 B$ U
; Q6 u6 g$ u1 ?& I! }
( Q9 U% n3 O. _1 i' G& vFixed CCRs: SPB 17.2 HF0359 z% }3 h2 b1 L1 e q3 h& ~# g/ v
03-02-2018- p8 q" e+ V7 p/ e6 ]: L6 P
========================================================================================================================================================. W- S* Z5 b; d; q; i. ]
CCRID Product ProductLevel2 Title
) F/ Z7 l2 k v1 c7 c========================================================================================================================================================
2 n/ _* C; |! [& r% F3 `1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML* V4 D8 Z% a9 B
1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib
( B9 T& S/ R# I- r* O4 z% _ A9 ^1846400 ADW DBEDITOR 'Copy As' and 'Rename' STEP model options do not work# g$ a/ s' a: e1 s. y: [/ b
1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive
" Q$ R" ^( I( p8 O6 I4 z Y1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB/ `) x3 e; I9 c: m# \
1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack
* I5 [! ^5 d+ M9 w% B" P1877219 ALLEGRO_EDITOR DRC_CONSTR PCB Editor crashes on updating DRC7 t5 W& \- b2 A
1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition
$ E$ q0 P; i! G( ]1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6- N5 f: v! i. e, Y+ L; A" p9 M7 ?
1822989 ALLEGRO_EDITOR UI_GENERAL PCB Editor very slow when using infinite cursor# _6 P4 z; ^* `# w) Q
1855275 ALLEGRO_EDITOR UI_GENERAL PCB Editor becomes slow if OpenGL is disabled
: Y, I+ m' p7 g' a; [' z! Z1868803 ALLEGRO_EDITOR UI_GENERAL Infinite cursor not working as expected
: ]2 N8 q0 g O: i0 j" U1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign' a4 X, P6 Y0 `2 V/ o' @
1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set
: p& C+ p! X- Q* G& H1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare
8 f' p! c9 J! n1872772 ASDA MISCELLANEOUS SDA pulls a license for 'Allegro_performance'
" @% ^* }9 q. a0 J0 @1877070 CAPTURE OTHER Capture redraws icons$ B+ O2 l$ O% s
1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016
& @: W. X* K" I$ a1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property6 F' `. X: |- L5 z# b# ~
1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw5 u4 C% w- {$ Y% X) e7 X/ N
1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command
0 ], I" U0 t* ]( n5 Z2 N3 r# }+ [% e1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently9 N$ q' G6 g9 }+ _" ?* T# P
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet4 Z+ G# q2 \% p/ w8 E' h
1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit./ t5 m' i: [5 ]& h3 K# r9 z
1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup
9 J' Z" d- S$ O2 o, o& q1878619 ECW PROJECT_MANAG Too many mails generated on doing create project
: G M$ o. B' O4 _1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.( r; f. D# n& n- B
1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings! s8 p5 A! `; o- X- }# N+ \, T) P
1867195 INSTALLATION DOWNLOAD_MGR Download manager crash$ u. y8 H- W0 s1 q/ m8 {( h, J
1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
8 |6 v- H9 F f+ N$ L
) ?+ I- E5 L4 p: w# \
/ \/ U4 M: A( s! E& CFixed CCRs: SPB 17.2 HF034
+ L$ G5 R8 r6 r& k* x02-11-2018
. W# g2 i6 X9 k5 L1 C========================================================================================================================================================
# f! K( o1 K9 X0 | r3 ~% kCCRID Product ProductLevel2 Title
5 c( Z0 z: k6 {6 d========================================================================================================================================================
4 I3 l! H: G, m1 r2 b: L9 s1863981 ADW ADW_UPREV adw_uprev is taking a long time after installing hotfix 0313 a: c. Z1 x4 q" R1 U
1868186 ADW DBEDITOR Configured LDAP authentication giving error on launching DBeditor after ISR31 installation% Z: Q6 I/ @/ x) b! D
1861524 ADW LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time- Y+ Q9 d& o, r
1842998 ADW LIB_FLOW Footprint model check-in fails with verification checks failed error3 M) U4 P( \: Y/ v% D7 Q3 c
1863047 ALLEGRO_EDITOR DATABASE The layer added above the TOP layer in SiP Layout cannot be deleted from database. \, n% `9 D3 N, v8 E* E* Y4 G$ V
1852799 ALLEGRO_EDITOR DFM Refresh symbols crashing inside constraint re-enablement code
, A) p" W8 C$ v: n" Z. l1865732 ALLEGRO_EDITOR DFM The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter
1 n9 R0 J) C& i" U/ _7 ^' I* g1862977 ALLEGRO_EDITOR DRC_CONSTR Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow" X: W7 ~0 x: v4 f) U- u7 N
1864460 ALLEGRO_EDITOR EXTRACT Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs/ h' `% R( w* Y& @
1859208 ALLEGRO_EDITOR GRAPHICS Pop-up menu remains on desktop when PCB Editor is minimized3 f# b- w" v# p5 c. n8 `1 C5 u$ m
1866422 ALLEGRO_EDITOR MANUFACT Backdrill update taking a long time
& }1 `3 R/ j' z2 V% D4 o; Y8 Q1867148 ALLEGRO_EDITOR MANUFACT Backdrill update taking longer time to process.& _# o' u& t: o9 C* g
1872127 ALLEGRO_EDITOR MANUFACT Backdrill performance issues - Additional fixes required for S034
- O& _$ f8 o( x' R t. j$ ]1866577 ALLEGRO_EDITOR SHAPE Board becomes unresponsive on Shape Update or Slide Trace- L2 O7 _; y6 `
1867590 ALLEGRO_EDITOR SHAPE The Shape to Pad clearance on multi drill oblong padstacks is not working correctly
7 z% B) |- F q4 m/ x# _4 x& O ?1871902 ALLEGRO_EDITOR SHAPE Void issue during rotation of symbol with multi-drill padstack from hotfix S032. c4 g6 E& N. @8 T( K
1866778 ALLEGRO_EDITOR UI_GENERAL Unsupported prototype 'Enable_command_window_history' is not allowing text edits using arrow keys
) M: ]1 n6 l! N- K1 j5 Y) k1865757 ASDA DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry$ R: U6 m% _, v& K
1865872 ASDA DESIGN_CORRUP Corrupt design crashes on editing.9 Q: k0 H6 K: C- v9 ^2 w( F
1867039 ASDA DESIGN_CORRUP Design corruption issues
$ W9 i1 J7 J$ N- s$ x9 F% Z1831263 CAPTURE OTHER Toolbar refresh is very slow on windows 10 after installing latest windows patch
" H1 D0 L/ I% \/ D# h% U1843595 CAPTURE OTHER Icon refresh is very slow on Windows 10 Professional after installing Hotfix 029
p5 n% j, _ I% o1845003 CAPTURE OTHER Application slow to respond after running for a long time
0 d9 Q P: m$ T* L& @0 L% o0 s1847062 CAPTURE OTHER Starting OrCAD Capture redraws the toolbar icons many times.! }% Y6 |( c" L$ `
1850816 CAPTURE OTHER Capture redraws toolbar very slowly and repeatedly5 R6 g" W4 ]6 O
1851346 CAPTURE OTHER Capture CIS redraws toolbars repeatedly
0 w/ H/ ?' |2 j: ~" M4 v; t/ u1851354 CAPTURE OTHER Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly! Y) _# |# h7 H
1851883 CAPTURE OTHER Toolbar content refresh is very slow
0 j3 ~9 V. |; V1852819 CAPTURE OTHER Capture refreshes toolbar again and again
# w8 T9 s! I% F. w5 R$ @, P. I1853395 CAPTURE OTHER Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix/ g7 e) L* b) k( _. f) n- t
1853972 CAPTURE OTHER Capture starts and redraws toolbar very slowly
& [( L) `1 x8 [% M1854735 CAPTURE OTHER Capture toolbar reloads multiple times8 @8 P& D, z( n o7 t" k" i) [1 s
1855850 CAPTURE OTHER Toolbar content refresh is very slow' ~3 [0 M( w) T, |% Y
1857523 CAPTURE OTHER Toolbar icons refresh multiple times and very slowly in release 17.2-2016# n2 w) w' f& c: S0 [
1859219 CAPTURE OTHER Toolbar is refreshed multiple times while starting Capture CIS
- Y2 V$ U: V8 V' L2 [# [' |5 ^3 J3 K1859626 CAPTURE OTHER OrCAD Capture does not work with the latest Windows 10 update
; ]5 g2 [4 m/ @% e: q+ |1 v7 S1863341 CAPTURE OTHER Toolbar icon refresh is very slow
1 T- X2 y! ~6 [! M6 u i, ?! _1865661 CAPTURE OTHER Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10
% [6 G- k! `( N$ L5 B; A1867009 CAPTURE OTHER Slow graphics with Design Entry CIS on Windows 10.8 A: ]3 z8 R' {% Y% ^! o7 c
1869160 CAPTURE OTHER OrCAD Capture poor performance (toolbar related)
) I" ]2 M8 r/ j- s$ `1869692 CAPTURE OTHER Redrawing of toolbars on Windows 10
2 Q8 |& l7 S: i1 \: u5 r1870310 CAPTURE OTHER Allegro Design Entry CIS redraw issue
" R2 _# g) g: o% T/ p1870367 CAPTURE OTHER OrCAD Capture Slow Redraw; T8 M) U! \) }
1871382 CAPTURE OTHER Schematic will not open and toolbars refreshed repeatedly
& ~* e, A% @' F& y, o0 ^7 b p' X1872427 CAPTURE OTHER OrCAD Capture freeze on Windows 10, G$ f c" {5 w5 _
1862679 CONCEPT_HDL COMP_BROWSER Unable to input property value to search in Part Information Manager
# |1 x+ a0 b# F# ?2 G% F+ T) T3 N1865039 CONCEPT_HDL CORE 'Save Hierarchy' of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
0 u s3 m+ k2 q) C" G1866544 CONCEPT_HDL CORE XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files
3 @0 m; v: S6 l; [+ k1849363 SIG_INTEGRITY SIMULATION Differential impedance calculation shows ZERO when changing dielectric constant; ]# f4 P1 [7 i
1854195 SIP_LAYOUT UI_GENERAL After setting 'enable_command_window_history' in QIR5/Hotfix 031, Edit - Text no longer functions
" e" R; ^& p! Y1 o! H% D' {9 s6 n- @
! d- [4 z1 I5 w: ?' L4 hFixed CCRs: SPB 17.2 HF033# Z: e2 ?+ {; _" a. F
01-25-2018& C% @" I! Y, D) x
========================================================================================================================================================
! ?/ \, D5 J6 W$ e' `CCRID Product ProductLevel2 Title
1 U# V( }( m0 M5 O4 ^; A3 Y4 m3 C========================================================================================================================================================
9 p1 s$ F; `4 K5 x1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor2 H! F( M) l+ j4 s; {& A# T$ p' N
1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model, ^; c+ J; P3 N4 l/ o
1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
8 [! K4 B i7 f J, [1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
5 Y. c- ~2 a4 A! D% G$ z" W; @1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database$ U. h) l; O: D0 d+ Q
1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout/ U. u6 t" b+ {; M9 x+ z! C* }
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor
2 B5 U! A) \8 x$ g9 p0 `8 G" k1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
$ h [# ?3 _' [1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
/ b5 a+ K2 x* \' F7 j3 L1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route; ?: h) j4 R! i
1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
" {7 B% @5 g" k2 T2 x2 M0 ]# O: E1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes0 @8 T' s5 V9 j
1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning. T5 I5 }8 y- B# {
1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs. q& c( {4 t6 ?+ F4 _
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
$ Q$ h7 {2 T' l! @( }, e1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap. u4 h. m6 @" ]) b8 o3 V% ?& T
1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap2 R+ Z/ h1 f. R$ \. O
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
% ^7 s( f# v+ @" j$ x1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs6 Z/ h: Z- y! O; O& X
1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
5 {, l+ \4 f1 w# t$ D1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly, @+ U8 d l, b9 L3 }/ {9 z
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression4 a4 y- p6 @7 f% J$ s
1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.
. O$ e0 _/ y: m) [( j- N- U( n$ U1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected8 _' r7 P& s6 v+ R9 n1 r
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.
; v- o5 p- x, W! `( L* u1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules# G9 S0 ]. {8 \8 I2 h' s- s' n- m0 s
1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-20160 e4 Y- \3 x/ w/ t W, p
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly0 |; z! |6 p3 q$ ~( T3 g5 W# W5 L
1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set0 c! f0 x/ j9 e+ A% n
1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
8 F ?; z2 Z# ~) F- t- }1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 0316 L. Z1 P. h) J% y$ \) [" ?
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031( `' ~) ~9 t# B, a9 b4 `* R
1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
" L1 h: a3 i# h9 K2 s3 I/ j1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand
( t w4 E: T4 }' r8 H F1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss% r N$ ?# N5 h$ o& h
1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design9 x7 h: Q- q* S$ J; x1 P
1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS
. x" Z5 X" {! [: ?: x1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32: W1 Y) X# E9 Q& M6 i
1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic+ L- t p& t- T$ Y* h1 K2 |# q4 r/ \
1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic* o; ]0 W0 D& l, `
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL$ ?& b0 i6 [1 K
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license. h2 x" u5 Q# q7 l b4 F2 e# Z
1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer- g# ~8 L/ ^/ E t! Z _/ @, W
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values8 S0 R3 u, z% K* i6 p" p3 w
1846541 APD SHAPE shape degassing does not obey void to shape boundary6 E$ p& z1 L! N0 _( a" B! ?1 s
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name- r H1 g& X; u, d# m0 K
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)4 o* b" `, J* V( Y9 @
1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually1 n1 e' m' K% |+ U1 z2 w7 j1 E1 n6 e
1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode- a$ D9 J C& G. m$ S2 M8 F# p
1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file$ {, {& q/ L1 }- C+ y) y! j! z8 o
1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol
b4 d" Z! h/ A6 z& B9 }1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
4 ~2 f9 f, a6 Y, K5 h7 A1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point k+ t& X) o! v) n" k3 {
1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
2 t" |$ R1 Q/ Y/ i7 n1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design
9 { ^7 T S* Y x3 z! i/ G, Q- @1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)
; [- u* L3 f: p; ~3 T5 j; v- `1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
9 i6 c5 |6 M7 B0 I6 O9 ^1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default
2 q, N; S7 ~+ t1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file
" l. {" t: r( [, k* C, T! P0 [1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
8 C2 X. w6 T9 W* l, ^ z1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
$ J* p& \, N0 d3 [) ?. n+ E1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change5 @6 @& ?" D% y- d4 Q* G
1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers3 m& n- ^2 q8 C7 H, A
1619098 SIP_LAYOUT SHAPE Acute angle of shape in design2 p7 e, n/ m6 w
1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed% E: O8 v5 v* n3 n4 {
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error' V! T: S: ]+ M. _( ^
. _; q4 z9 K& D1 J: `& U+ s# f& C. g' _. Z. ~
Fixed CCRs: SPB 17.2 HF0328 f7 E8 o3 W1 n% H) j
01-13-20182 t: h# a. j- ?4 s5 i- l% |
========================================================================================================================================================
% H+ u( o" ^0 V! SCCRID Product ProductLevel2 Title
+ z* v" C% w; q/ U2 _$ T6 x* J3 ]. f========================================================================================================================================================
" {& }) A* f8 n; n1846603 ADW FLOW_MGR Copy project GUI not displaying correct design name after changing the project folder name
. l, p% M6 \# Y0 R) F/ t3 Q1831152 ALLEGRO_EDITOR 3D_CANVAS New 3D viewer canvas is blank
* o/ I8 C+ K( F$ s1 B! q' _1805870 ALLEGRO_EDITOR COLOR Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
# U0 G: S2 g* y$ Y3 Z8 }* ^* p2 }1843126 ALLEGRO_EDITOR DATABASE DBDoctor UI is taking very long# a2 p8 ?5 H* b- c2 W- c0 S4 S
1857588 ALLEGRO_EDITOR DFM Design for Fabrication - Aspect Ratio is not taking correct drill hole size
: ~+ [/ D- p/ ~1 x1844313 ALLEGRO_EDITOR INTERFACES STEP output viewed in third-party tool has parts sunken into the secondary side
' S! E5 o/ A' e! g5 {1801301 ALLEGRO_EDITOR MANUFACT Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component" x7 ?, M# L# z! m
1850078 ALLEGRO_EDITOR MANUFACT Choosing 'Manufacture - Artwork' crashes tool. U/ W( `6 q5 C* b
1844049 ALLEGRO_EDITOR MODULES Module deletion not removing related component information.4 a/ U* k1 i- {3 l
1849665 ALLEGRO_EDITOR MULTI_USER Shape rejected by muserver
' X5 J4 C3 [" T1782831 ALLEGRO_EDITOR RAVEL_CHECKS RAVEL file does not load when it is located on a network with a UNC path specified
* T) w8 R9 B: ^* R0 |1 X4 L1830442 ALLEGRO_EDITOR SCHEM_FTB Fail to import technology file with message for failure to read the configuration file
5 c1 @. v4 Y1 m9 m* x2 J1837391 ALLEGRO_EDITOR SCHEM_FTB Capture Property cannot rewrite or update constraints in PCB Editor
$ D* G, n+ L |1 c# s q ^1840643 ALLEGRO_EDITOR SCHEM_FTB Export physical does not work after modifying PCB cross section
1 K. Z, P7 ?0 z1 D5 Z# ?1718165 ALLEGRO_EDITOR SHAPE Drill hole cannot be voided by shape5 f9 ~- V- W4 e# l$ ^1 M; R- A c v6 C
1753245 ALLEGRO_EDITOR SHAPE Update Shape retracts more than the shape to shape spacing* U1 [. u' u0 j7 u* b* J7 _. Z
1827366 ALLEGRO_EDITOR SHAPE out of date shape is not flagged as out of date
7 O `7 f' B5 M' F1828208 ALLEGRO_EDITOR SHAPE Shape remains out of date, but status shows otherwise
0 d4 N0 U* }! Z& ^1832098 ALLEGRO_EDITOR SHAPE Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.+ H. u- x" T- w. [" E7 g/ |7 w% V
1834281 ALLEGRO_EDITOR SHAPE DBDoctor creates a large number of DRCs
% d& T& \/ C( e6 I$ p1842121 ALLEGRO_EDITOR SHAPE Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.6 [' h# T# h$ c2 M( N7 d& B
1846010 ALLEGRO_EDITOR SHAPE Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date5 g4 a# d% y, h
1839119 ALLEGRO_EDITOR UI_GENERAL On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design8 F" _5 e$ g( z- u: f
1828794 APD SHAPE Setting Shape Fill Xhatch Cells option to HIGH, crashes the application
* i; y3 c. b8 Z* x! }1840748 CAPTURE PROJECT_MANAG Capture crashes on opening or creating designs
h3 Q2 N+ D3 D1785298 CONCEPT_HDL CORE Incorrect object access during variant load
& g9 a% d% l% ~& k% l1832119 CONCEPT_HDL CORE Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error" q( R- G' ?8 J& k' C6 X+ K
1833036 CONCEPT_HDL CORE nconcepthdl crashes with a core dump when running an external script
I+ R. u# P6 c y1841545 CONCEPT_HDL CORE NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016
, u) z2 ]$ q3 P: G- |1842289 CONCEPT_HDL CORE Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten
+ ^$ O% f6 A5 A% `3 F; E3 m1841543 CONCEPT_HDL OTHER DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029* K4 L! n R: @! X
1843791 CONCEPT_HDL OTHER Table of contents listing does not update for some hierarchy blocks at the top level
: D) _9 X8 Q8 J+ x8 x" L1850709 CONCEPT_HDL OTHER DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 030 \' S; Y( a4 X0 H- P- X. _
1853377 CONCEPT_HDL OTHER DE-HDL crashes on trying to edit bus tap value on Windows 10.
1 i. C9 l3 \; x1857213 CONCEPT_HDL OTHER DE-HDL crashes when changing Power Property2 s2 Q) ~/ ]* t( R! l8 w9 g
1857214 CONCEPT_HDL OTHER In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10, ?9 T* }' J5 E! m9 g
1821982 CONCEPT_HDL PDF Pin number shown in PDF published from DE-HDL
& r. _: l, k8 R; ]! g1848615 CONCEPT_HDL PDF PDF Publisher shows incorrect pin text values for parts
8 n8 k3 E9 r) R2 b" X: z1845996 CONSTRAINT_MGR CONCEPT_HDL Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'
- M' K9 E" E" q9 A, U- h; S' Y1854190 CONSTRAINT_MGR CONCEPT_HDL 'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016
) i- @( W) R% @1854868 CONSTRAINT_MGR CONCEPT_HDL Match Group getting deleted after upreving the design to 17.2 and removing the signal_models
' r" m" O; z: E2 b9 \3 q( {$ A1854872 CONSTRAINT_MGR CONCEPT_HDL Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2
3 j5 K% d5 g4 P6 Q/ q. Q1822624 CONSTRAINT_MGR ECS_APPLY Cannot copy PCB net schedule from a net to other nets4 f, a, l/ ~% K. N5 Q6 O) R
1854883 CONSTRAINT_MGR ECS_APPLY Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
* [1 F+ C9 K' K, i- @. L( L1855893 CONSTRAINT_MGR OTHER SigXplorer extraction crashes PCB Editor
/ E, a2 W9 t6 g6 S( W) b @1855917 CONSTRAINT_MGR OTHER SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM! ?1 ^/ A' K9 t/ i
1855350 CONSTRAINT_MGR UI_FORMS Constraint Manager significantly slower in release 17.2-2016, Hotfix 031
& G* x) n1 w; k7 A: {1855860 EAGLE_TRANSLATOR PCB_EDITOR Cannot invoke a CAD translator in PCB Editor- p% K+ }2 F! U7 M0 S5 A
1857745 EAGLE_TRANSLATOR PCB_EDITOR A CAD translator does not invoke in PCB Editor4 Z" [% U8 W D ?/ D
1859005 EAGLE_TRANSLATOR PCB_EDITOR Eagle translator is not invoking at all
6 ]" b; ]3 r2 P8 ], A7 q7 m9 @' G9 c; l1843091 F2B DESIGNVARI Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016: R5 F3 W$ A* S- k$ N
1719059 FSP DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently
3 S. ]. f/ k! w" O+ R1823419 FSP GUI Net Name Template not visible in Change Net Name in Windows 10" A7 G2 b* w* i6 R$ E
1480035 ORBITIO ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout$ D U* E+ [& H- |! h
1853331 PCB_LIBRARIAN SETUP CPM file not updated from PCB Librarian setup
, R; g7 Z! E( n$ r3 a' t1841308 PCB_LIBRARIAN SYMBOL_EDITOR Symbol not updated in Library View; @/ l1 t' ?) z1 { R. n. G
1831269 SCM OTHER Blank properties of associated components are being filled with NULL
# t! X2 n- B" a0 N1719057 SCM SCHGEN Pins off grid for voltage nets' O/ M7 g* u6 v; t* K B) S
1719060 SCM SCHGEN Pull-ups and pull-downs showing upside down in view! A. H- \9 @/ d0 |7 V: a3 b, l
1732687 SCM SCHGEN Schematic generation deletes IO ports; says it's placing them on last page, but never places them
8 B# F1 {$ ]4 k$ Q5 [1855932 SIG_EXPLORER OTHER For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm4 ^% H% |$ _6 B8 b+ r- B( I
1824035 SIP_LAYOUT WLP SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck4 G9 D" |& }; _% F% {2 Y% N7 M
3 W$ s8 Z/ b9 O. h6 F0 ?6 v
8 a9 q6 o, i) }, V% G( iFixed CCRs: SPB 17.2 HF031
% Y; L* ?# y% K- G12-8-2017
! E; B) s8 ]& H- v7 B! j======================================================================================================================================================== Z3 d1 n' C2 i5 i) L- X: d
CCRID Product ProductLevel2 Title+ }" x2 P2 j% [- w# l
========================================================================================================================================================8 Q" h! U7 h; k
1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
* b2 F" ~+ d* u, S* {1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase8 y1 j/ `& ~# W: j6 W D
1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor
1 J* D# K; @# y7 a9 b( y) g4 V1807410 ADW LIB_FLOW Checked-in parts not available in database4 d% g6 w) h2 E4 P/ A+ h. T9 ?
1797408 ADW TDA TDO crashes without displaying exception during check-in
+ \2 q, p; i/ K% o+ }* s) U* v1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra
: r( \+ X. i' g% _* X: J. a9 Q1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024
" F4 ~6 Y, p1 W9 T8 R: a1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'/ j5 D L1 |( E
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC3 k* m4 C# Y8 \
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins6 h( i F( u+ p. s! _% I. G! N
1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
! w3 S- Y! X1 ~7 O4 T1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names' R `, @, r# R% U
1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap" g3 f, d3 d: ?. d
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled7 I1 v: t5 x6 l# x6 g
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog
+ t/ N5 C$ r. _* S) K1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters+ _2 m4 M+ t3 ]/ T' |1 o
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes8 {0 P: q" }" C
787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
4 R6 c! e9 c. ]# u793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region
( c0 S( O k( X. D9 N6 k797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed; i2 z/ Z& R6 v$ A& ~- m
865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value. b. Y2 e) H/ z) w
912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
& ^# B- Y* Y h/ j7 S: V965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes
+ ?- {' n- f4 Q- `3 M968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value |5 K' K D$ d( w1 J
974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
2 M0 e9 ^+ d, ^, Y, e0 J. A. q; h1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region$ x5 {2 B% h3 W2 M/ c6 R7 Y
1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes
e1 R: F9 d4 _6 w1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
) c; {# G0 ]5 w1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region+ J3 t2 u0 z. C# Y
1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
0 w/ H, H8 n, ]% N/ d/ o) h# b1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value) @' Z( ^2 t8 {
1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.
( l2 y& [. ]3 K( a6 F* I3 _, C1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
" A- H- i2 Q) ^6 N! I1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
. C+ ^ n4 k4 i6 `& }1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region Q6 A. q& }3 f+ R r( B7 A8 ~
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules
& T2 Q& j' w* |9 A7 m5 a1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region& r, F9 s! B7 G! V+ R
1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
' C5 {) ]/ s: \- t1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly# S$ B. B" ]2 b
1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value! |6 u. Q. h2 D& U" D
1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region. ]6 @* q# b% G
1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
3 K8 L, b6 P8 _1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape: f0 l5 P1 M4 k- \6 p
1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints5 j1 l/ |0 d) i8 U( u n
1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu2 i; H$ \+ |% {8 s c
1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
! b5 c k8 p3 E: @3 k3 n$ E" p1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
' |" {( V! Z1 y6 L" J1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
8 u7 L5 _0 e1 N! A% r; T1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing2 m. ]5 L/ |0 s* C
1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components$ P4 k5 X2 i' B& y6 F P& |' _
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib9 B) P# U( L4 t# o( Y0 O6 x0 l
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA5 y$ n+ Q$ F5 {3 C3 j7 m
1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016: I' w4 r: C# k' T9 [
1735506 CAPTURE OTHER File menu is missing in Capture, c$ L3 v. P/ T/ F
1766663 CAPTURE SCHEMATICS Capture crashes during part placement
' \8 {# C1 S5 Y1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
* a& d. A+ b1 V/ G/ z9 g7 h- M, g9 C1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
3 p% F8 ~7 P6 a6 R5 I9 T3 s% i1759424 CIS PART_MANAGER Unable to save the link database part from part manager" k5 M2 w. J9 r9 u: n$ U5 A
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block) S7 U; O5 U, e |" m
1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case
5 |1 c" \& T" V O: ^9 J# g8 d0 S. L1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue- p( c( x. ^# c7 y6 w) a
1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input
6 l% j; z( ?/ i) N9 D1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse, [5 L |' e/ Q+ f5 P* j
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on s) F {; O8 B, D/ R$ F
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
7 e: \$ }* ]4 Z( G7 _8 @1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
7 C5 D& W& b1 d, N1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window4 ~9 e0 A G1 K: A( H, s
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors
, ^& @( @4 I( W, m Z% J' L) u1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
7 D7 P1 r' ~, r9 O1 j7 J1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL' S7 I3 p, @6 h; T4 a
1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots
2 B( `, Q$ l6 O- `+ z4 r1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
1 K/ R, P6 I2 R! a1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
) _. ^) z2 |7 q1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown' l) V( M2 H+ Q7 r6 K6 S
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session
/ Z8 J0 m+ a& |6 R! @: @1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'$ V$ V4 }3 c9 e; N( \
1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct) T! }6 @& w1 x0 C- O
1801790 PSPICE LIBRARIES SAC model giving errors# [! G+ Y* U% d( f! z* Y
1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
! R6 e- X1 B6 Q$ G, \) W6 c3 U5 l1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6- d/ g' h- X/ M% T( N4 ]; [: W* G
1803407 PSPICE SIMULATOR Getting convergence error on a model
& O0 E K' ~1 B7 l4 w6 y1814759 PSPICE SLPS .INC file is not working with SLPS' v( n6 P9 r9 T, Q
1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
4 s* u5 r, n3 I0 u- f1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings G w" ~5 J8 b' S! X$ f R/ L
1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
, y. W: `; V; A. I7 f( g+ P& J1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.; g; t3 Z- T5 L c/ d
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced- {2 N; V3 x C) n& i. l
1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern% U% e5 e1 S4 ?% D/ p3 U! W9 `
1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out4 n. U7 d' b# G! ]
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
* H6 x- `! @, w& u( G% h4 F) D' C7 L
( ?+ ^, l9 L$ `5 q: n1 K; ~
Fixed CCRs: SPB 17.2 HF030
& Y* u6 N" o3 V) S _11-17-2017
9 `- p0 ^0 @6 H========================================================================================================================================================
) }/ j* I: A$ T7 I: u& z% C9 i! PCCRID Product ProductLevel2 Title- g! z2 m; D5 |+ F2 z% f
========================================================================================================================================================" T3 p% s( e9 _7 w9 q1 {6 ?, O" J3 J
1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist7 T& w$ v7 |& C" P+ G- Z
1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin
3 z3 G$ C1 ~( W' C5 T' F% O1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher
$ H1 i+ z$ [5 P* q: s9 M6 O- x1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected
* }: h3 B. ?% |$ [2 ^: M L1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF
+ |. B9 }& e1 @( S4 ^1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models; t3 m! I3 N, r; e3 m |5 x
1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline." B- K4 \# D- p; D" A" K
1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill) F* K4 O4 f( m! D
1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape
! J G8 ]% w4 `1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals) e9 `0 s2 w+ @
1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation2 p0 s$ y% {/ f9 ?" f
1831200 ALLEGRO_EDITOR PLOTTING Incorrect PDF output for traces: W/ J W, N2 j2 x& h; f
1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short
6 g8 j/ ]4 n: g2 E1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box ~2 X; R- \' j) q
1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly
0 L* M3 B) s. n. G1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor+ K Q, Q$ [" z
1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected2 r, f* V2 c" f# D
1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work
" D! C6 \ F/ G1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library
1 h5 p0 t$ G% R7 q/ }$ W- W1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window
1 Z0 u" R, n5 _# j1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant0 f& E4 E% c) r! O
1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
7 `2 p# ~1 F" \5 x; `1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part [/ L2 o0 H' i
1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design7 B4 Z- D# K0 e4 ^2 n
1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form3 ]7 V- U+ D0 h1 V6 o
1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid
# t; M+ \2 v2 x8 M# {1 |- O1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks: _) h. ^9 O' N9 N0 \" Z3 |
1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models
1 G; N& H. y+ B1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist
8 b# `% y ?% x; X8 j0 v1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect# [0 h- M0 V3 ^1 e, c6 J3 N
1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets
" S; L* L. e$ [$ O3 ?9 T1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output. \/ d) V- x% s. B. s& W
1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory/ X4 h/ k: t$ I7 z' s
1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design/ y' N2 e) B& F; i O8 {# j
1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable7 S1 ^3 a: I! C4 s4 {" t
1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016; u4 ~, j) j) Y8 R
1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands
- i( C1 }9 p9 r n, J4 a5 V/ Y$ a( j3 \) \8 o! h: t
/ R/ c" A7 w" H, `' h% x
Fixed CCRs: SPB 17.2 HF029
o, ~. q5 W& B) ]: s5 @11-3-2017/ D/ U# b5 F# [5 c
========================================================================================================================================================
0 B# ^1 V& }, G3 P2 {CCRID Product ProductLevel2 Title d. Q" x. F2 Q0 ~) j; l d
========================================================================================================================================================) [4 ~( T' u0 U/ F, E+ _5 y
1814597 ADW DBEDITOR Associate part classification is very slow in release 17.2-2016 of Allegro EDM% ^# O: F" Q# {; L b' g: M
1733482 ADW FLOW_MGR After installing QIR3, Flow Manager prompts with Java Help question
8 u+ x- }# h( a5 |6 A9 }# H1814789 ADW PART_BROWSER PTF shows data in old component browser but not new component browser2 z+ y2 t- ^& a6 u# k$ p
1808620 ALLEGRO_EDITOR DFM Missing graphics in new drc browser.
. o O0 L! o( x1 E1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section# ^: e) R, U' v0 l" x' x H1 p
1807996 ALLEGRO_EDITOR EDIT_ETCH Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region
5 A% u: l+ o6 ]) n2 T1747929 ALLEGRO_EDITOR INTERFACES Cannot import logo/bmp on a .dra file8 k; d# E$ ?/ S# P8 S
1820142 ALLEGRO_EDITOR INTERFACES pdf_out command not supporting UNC paths for the output pdf file
/ T; L9 K+ L3 G3 h% `, Y2 s1671865 ALLEGRO_EDITOR MANUFACT Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error* I2 L& d) |5 j$ C. g
1710032 ALLEGRO_EDITOR MANUFACT Adding Artwork prefix gives error for illegal characters# h1 \- v& T, X( o' a9 V
1714911 ALLEGRO_EDITOR MANUFACT ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form8 _/ m8 V, G# p1 T+ t7 i" i9 L
1813950 ALLEGRO_EDITOR MANUFACT In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed
: Z* z: B7 d- _7 p5 T. p5 v0 J1820970 ALLEGRO_EDITOR MANUFACT IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
& g# x6 Q$ Q2 u7 Z1 T% k; v2 P1822045 ALLEGRO_EDITOR PARTITION Shape fillet becomes static shape and loses fillet attribute after importing partition8 P8 ]) ~$ ~% ?+ L) j; j
1776181 ALLEGRO_EDITOR SHAPE Placing via arrays around a differential pair places vias only for one net
, @! m7 G% i1 ]3 r, k1817283 ALLEGRO_EDITOR SHAPE Allegro PCB Editor Show Measure Air Gap shows a very large number
. c( ?: \ k/ r( B2 [1815595 APD DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets4 j$ V0 l& w/ r$ `! T2 O# o
1785116 APD SHAPE Big size die performance issue
: d: s% e# P/ j. l) E) M1811134 APD STREAM_IF GDS stream out with 2000 precision has sharp edges along shapes.) E, ?# E) W4 V) ^" u' T1 s
1811882 APD VIA_STRUCTURE High-speed via structure refresh fails) T1 ?. [% w3 @6 @0 D: }
1814878 ASDA DARK_THEME Part Manager: Difficult to read black text on black background% f- Z4 W v. j. d
1814889 ASDA DARK_THEME Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
% S* X: U' V) s) g3 a: Z* ]1817355 ASDA PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
* X9 A9 i% u6 _0 x1817964 ASDA SHORTCUTS User Preferences shortcut misspelled
/ w- o$ c7 a8 w5 ~1820247 CONCEPT_HDL CORE DE-HDL crashes while saving a design
: a6 Z/ j; m2 T+ D6 z1823187 CONCEPT_HDL CORE DEHDL allows editing of the locked component's refdes using change text editor. e; @% \- F! H
1824052 CONCEPT_HDL CORE Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic
( }2 I9 d% R2 b1813987 CONSTRAINT_MGR OTHER PCB Editor crashes when Constraint Manager is closed, {! ~3 D% u& e' W. m8 x
1821129 CONSTRAINT_MGR XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols
2 X- d7 S$ C2 _/ | c) R7 x% @1814725 PSPICE PROBE PSpice Measurements crashes PSpice for a digital simulation2 g1 J: s' q# R+ E( q/ T4 U* O
1808672 SIP_LAYOUT INTERACTIVE create bounding shape command options: 'Min Area' and 'Sync with shape layer'
' O3 P% x% |0 L9 p* H# C3 A# ?1817458 SIP_LAYOUT MANUFACTURING Error in DXF conversion after updating SiP Layout from Hotfix 066 to 082 in release 16.6! @; X9 Y& ?* b
8 j8 O! V8 @+ ?, x( K6 G- g! j
# t, P4 M1 J3 \5 _5 O
Fixed CCRs: SPB 17.2 HF0288 r7 N2 k, t/ o- \6 ~3 y9 [
10-14-2017
3 w5 C# u+ F' M( t========================================================================================================================================================
' G( B+ f) e _CCRID Product ProductLevel2 Title
( R" i5 b5 W& n- j: H7 T1 i& K========================================================================================================================================================
( y4 V9 p/ T. X' g4 B8 E1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design
; s, B3 j4 m; c6 S2 K1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016
: X& N3 h5 P3 Y( x1794116 ADW FLOW_MGR LRM fails to run on project
- z! n4 c8 V0 V; T; Z9 {1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log
5 S9 |2 \" w$ z0 E& J; l3 V( W1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks9 q7 i! S* x8 B5 O4 g4 C
1771851 ADW PCBCACHE Problem in packaging upreved imported block2 O" r I/ _$ z6 P% G& i
1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer" ` |7 d; i# e: |0 y
1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 10
- h9 A. \- Z7 r% [$ {1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup
. i5 a% R! A* j; x) T+ A1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel1 P6 Y0 u6 c7 T/ c0 h
1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor# }6 {. k1 u5 f* d; p( v
1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder
; C/ v$ c: l) }1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database4 U& x- y) t/ F' u; O- E8 j2 _
1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version
; B' P5 F+ C% _# l# s1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database* S* e. X) {. S& {2 Z! p
1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board# o& X/ Z! {& u9 B
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-20164 a& l, E& u" @5 r z1 ]/ c
1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element
+ ]4 h* t0 D+ D6 _6 F1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020
+ b# b" i f! m1 q# Y, c% s, _- B1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank. j! T& w) x- V+ r3 j8 N* u
1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
5 V' ^+ J1 @# b$ x1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 0245 N- a- Z0 E2 M* V) u2 S" h
1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set8 F$ {1 A* @- r. k
1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-553
6 d6 E3 D" p5 _. A3 U# B4 r0 M4 M3 n1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow
~! W5 G2 i& T8 U' F% z+ K1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design% r8 T; v( A' e
1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net
( i$ d1 T) B8 o1 G2 x1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
: y( M( n4 {1 l2 Q1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class
: Q$ R ]! V& b- N) v% L# C1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues, o) [! W3 w6 J2 }5 Q
1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined# S/ {. ^. M! q, F6 P+ S$ m1 X
1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 0261 [3 }: V3 ~4 Y4 y3 o4 e
1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL
! h9 f* ]/ m7 t" v" K1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout
, @6 g0 { D2 g7 B( }- F. T1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs: \1 S: {' v+ ]3 I7 u( S( n
4 c! r4 P2 i" ]2 ]% x Q a0 F* O- O
i! `# o0 z" l" q, {& k3 o% k5 t3 qFixed CCRs: SPB 17.2 HF0270 |& f9 k1 P. _+ a& D
09-29-2017
* M8 H4 O6 U' J4 E5 @========================================================================================================================================================2 l/ C% V, P/ v; e
CCRID Product ProductLevel2 Title
$ y6 I9 V; t, y========================================================================================================================================================+ z! d2 A* c9 c) K2 G
1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt0 @1 X( g7 s4 A% F
1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
# p+ D1 v3 G# e5 n: |) T( e1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.
4 P* A$ S6 ?% p! A# |& W9 y8 x h1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer
0 b1 i. U6 T' S, [+ |. }( f1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design
X( ~0 P7 B5 ]/ `' g! y6 q1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues7 ~9 q6 p' b- e8 k9 G' c" E# b) c
1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size
: u% T; I" i \# ]3 c1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403': q1 l" K' Y/ p; u
1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components7 `. m- ?, z6 r% F
1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025) U$ W9 ~+ T; a! v
1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error
! _5 [% D( _- |2 v k. [% N1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.
6 ^+ L* m2 H# }1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found, z0 m2 ]; O3 l- ^( @- I! A- R9 j# t- e
1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design
9 q2 k q) c- L* b* P9 U1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design2 M9 `5 {9 x- X/ `+ ]& w
1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error
% P& m3 ^1 V# i# f( D1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape: w* m* V# P1 X! u
1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly& L9 [* X$ c p# u; [# c$ j7 z
1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist4 I5 S) \( ~. ^
1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025
' }7 u `/ a- ~9 l+ v1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option$ ?0 a9 D* a4 x$ X( Z$ d
1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry. ]2 {8 F9 v% q0 F/ K) z* O
1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence1 L, H. h/ S0 U( \4 E+ U0 C. q: `
1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
1 O& ]7 U6 y/ N% I; I9 q1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search1 d! \# ?1 L, L% E
1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components- x l. ^: X/ p/ K7 P4 p/ x6 v
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block
1 N+ v, }' ]% t9 G; O1 F5 R W1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set
8 v- X2 L# k' {1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016# ~ @& ^* e$ ~
1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403)
- }( F M2 Z8 L( _+ E6 d3 y1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation( S& P9 ?5 P, b% ^
1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue
- M' M( F9 h" C6 s* K6 f7 H! z, G! [1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality
+ [; \8 N' X6 z3 X8 @& n1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.
6 P6 F# r3 x/ G2 H8 F: }1806978 CONCEPT_HDL CORE Cannot mirror a group of objects
3 p& ~! d3 T, c1 T( Z5 x& w9 s1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved, F( n1 Q$ ^2 }! f9 O
1812811 CONCEPT_HDL CORE Schematic group mirror not working g/ b) s' B B" u: j9 \
1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name
5 S1 w/ O/ W: D/ A4 q6 u& [0 B1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish8 W" ^# f& W0 O! Q0 Y
1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors& Z* T* s, i' h4 X
1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project" C7 n/ t: B! ^7 F; D- q7 |5 d3 L
1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor# q& @$ B( P$ ]" Z) |
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
: f/ Q$ J/ a0 G/ Q6 I2 o1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
& s8 D6 X2 E3 L5 t! S1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import
* u+ G9 ^3 \, {! [1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size0 l o' c# N; K8 R! R! r" X" n. o/ z
1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails6 }! O/ C! b* k; c! \* z [$ x1 b( H
1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted
E7 q) C- u6 d/ b0 o# s1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size
* M; T* g* \ y* I! Z1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)3 ~& f" q& [7 ?/ z. c: ]
- E( \* m7 [7 h9 {) D6 m' o* a: D! [; P9 ], {
Fixed CCRs: SPB 17.2 HF0266 p; n+ W" X0 J. `
09-15-2017
' ~1 k% R H' Z% d; r========================================================================================================================================================
, n2 b! v% ^( T" b' VCCRID Product ProductLevel2 Title
' B/ Y; Y% T0 ` q========================================================================================================================================================! z* P9 T" p/ k$ G5 T2 C9 u$ g3 B
1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange: w# l6 f; J+ U9 i
1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information
' O9 m. A, ^% J- P1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
, J' Q6 u( g, @* G7 a& d& C1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins$ A! s5 A( g7 Y
1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-20163 Q- l* k* }; }; D k) A
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu* s' r! f7 V1 p
1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu% V; w& A$ D2 {3 J# L
1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components
/ C: @! L: B5 D5 p1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping
0 w D' O0 B$ q& s# S1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly
5 N! F& x) g5 m( E9 d3 }1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'/ g0 B6 g# `! W' U. P* c6 A" ?
1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves
' F# B* J" C. o) L. h2 r( I1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently4 t2 w* u- f) ~' l
1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached
3 U& M0 g" A7 X" `1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF; B$ A8 U( _ k/ s" f) s' C/ H
1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.9 C/ C; W/ }$ g7 z0 U- _6 S9 b
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape., U5 v' f8 r& ]0 a# N, Q
1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only @8 Y) ^6 }# c- v4 L
1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
) @5 a* L3 k: N z1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6
7 e' ^# B$ |7 a, D) {0 F1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via9 C, S* I7 _3 d8 Z1 O9 J1 v; V2 `6 V
1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup
: f9 b( s6 g& o& R! [- a2 y1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly9 m3 A+ a @ p' m$ h% @4 ^
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
5 r. m) c, Y# X1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name
( ~3 a. d9 k2 K$ Z3 E, o: Z1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance
0 z+ ]5 ?' @$ }4 q1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
7 A' P2 }% j% Q8 i1 f" O/ {) ] R; F1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016& k$ F" p8 t. @5 K
1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
1 u) e0 `8 Q4 p( @1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly# `1 n& f- [2 O3 [0 Y( X
1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016
$ \ \) x! C8 @0 r1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window
: R8 M& y8 v/ |% Z% c* b4 {1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager, L0 W! u+ _# b3 i$ S9 ^
1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file0 p4 Q' v' I7 \( x2 g+ a4 k
1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
5 B+ B& M- p* y* ^$ c1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish4 {6 q- u: ?0 Y+ w6 A+ ^
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file2 a7 G* K" L2 Z
1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager2 B% f& r3 {' |, G
1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names
3 B/ F# U1 r9 t9 b6 ?1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
6 s3 y: a* l3 H% m C" B1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI$ r" A3 l" \1 |3 b) v% K9 U
1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
( _" d9 y' e# ?, I; O& q V& J1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time
) O4 g4 k/ r; D6 M1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance p" }, o/ d0 s3 J) A
1770174 PSPICE MISC Issues with DMI Template Code Generator! u$ s8 D: L" {8 @; B; s
! P1 u+ M+ ?: b( U8 C7 a& ?
- H8 \) e, |$ f2 y+ _7 @% kFixed CCRs: SPB 17.2 HF0254 I7 b C1 c$ [
08-25-20178 `) O$ [- Y! P) m" @
========================================================================================================================================================5 Z' Y6 G8 b6 J2 E) E e1 H
CCRID Product ProductLevel2 Title
K. ~- D5 d1 [========================================================================================================================================================' C- Y% x4 L1 v* o; J
1258913 ADW ADWSERVER Copy project message: Unable to locate tools.jar" z; L! q2 w; @. @7 v7 w& {
1760866 ADW ADWSERVER Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix
2 m: l* d3 \9 g( h1055946 ADW ADW_UPREV Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
1 t( v$ {$ e1 x1508163 ADW COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree& F2 `, p" b1 J
1774164 ADW COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View
5 Y; E' z# Y6 t1345018 ADW DBEDITOR Database Editor does not catch empty mandatory properties if no changes are made to the part1 { w" C6 b6 Q! G, ?# M# ]6 `
1586858 ADW DBEDITOR 'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor3 H$ J; A% V- B; P7 s" t
1754185 ADW DBEDITOR Max Height value in DBEditor is different from PCB Editor
- |0 _4 I: ?1 m. z8 H4 |1719260 ADW FLOW_MGR Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 0142 X5 v: A) o$ e u0 F* F
1743730 ADW LIBDISTRIBUTI .lis file error in install_model while using MLR.2 p1 l% b$ {- w1 k' d
1757178 ADW LIBIMPORT back-end libimport failed, crash and existing flashmodel not found$ M$ R: y6 M9 f4 D& r
1648609 ADW SRM PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078
6 p% T( h* k) J# x* d+ @5 ?$ e$ b1731152 ADW TDA TDO coredumps after a new object has been checked in as minor and deleted.; ~+ I4 J# z# `) B& c, y- S
1766998 ADW TDA TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design
2 H& v/ p6 V4 F0 Z4 T2 Z1695240 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol7 g; l) m( }, P/ {9 F- f4 q5 r
1698148 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Viewer crashes on Windows 10# F" k" S. L* O! i( i
1738655 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes on Windows 10
( c8 A% f; f! Q5 t, O$ O# p# O1750001 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D Canvas crashes on selecting in symbol view# c: ]3 {% I0 P( Z! m
1751796 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas shows component placed at wrong layer for Embedded components
* x) a# E2 R) g* G3 {1768775 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked
. g, q# S8 D# k$ K1695025 ALLEGRO_EDITOR ARTWORK Artwork film show shorts. g6 w$ b9 u6 X6 Z5 g
1708674 ALLEGRO_EDITOR COLOR Dehighlight all should disable the check boxes in the color dialog/nets
. ] x) s8 k# e4 g7 w1735522 ALLEGRO_EDITOR COLOR In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.
; W0 e7 r2 b' ]1764475 ALLEGRO_EDITOR COLOR Allegro PCB Editor hangs when selecting OK on the Color Dialog form: J( N: l2 l+ w* n0 g3 _, N1 d) O
1718438 ALLEGRO_EDITOR CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.& n6 q$ e4 m. ?8 ?
1765387 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses
' y' d7 B' @+ ]! K3 A1714910 ALLEGRO_EDITOR DATABASE PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
4 |8 a# ]/ _) q# ? }0 w, `9 C0 [1769534 ALLEGRO_EDITOR DATABASE DBDoctor unable to delete invalid subclass
3 g" f! Y |1 x9 k) g! M6 C4 f1775705 ALLEGRO_EDITOR DATABASE Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'2 ~0 ^+ X! [1 b4 g3 r! @3 p: i$ @
1778608 ALLEGRO_EDITOR DATABASE Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer
. }* `/ k# C* R5 P9 w: v6 @1778644 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes while trying to place dimensions
; S$ X! j# B) K' l2 r' P1698695 ALLEGRO_EDITOR DRC_CONSTR Line to Mech-Pin DRC not displayed' g8 \" W4 d# C# T" \0 Z1 k
1705214 ALLEGRO_EDITOR DRC_CONSTR Shape to drill DRCs not getting void and 'cns_show' does not report constraint value& t& `( C+ Q/ G. O# L- B
1722841 ALLEGRO_EDITOR DRC_CONSTR Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask7 J: S2 ]& R2 e% ~7 k: D
1736116 ALLEGRO_EDITOR DRC_CONSTR Shape Voiding and DRC error on layer with no hole or pad definition }' H3 k) w% I$ C- r" l
1744248 ALLEGRO_EDITOR DRC_CONSTR Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
3 f* S( R4 q. Y& X1 x1776848 ALLEGRO_EDITOR DRC_CONSTR Negative plane island DRC reported in release 17.2-2016 Hotfix 23: R. m& v- b( c: U( h
1730806 ALLEGRO_EDITOR EDIT_ETCH Element 'vias_allowed' is not valid for content model adding high speed via structures/ U9 q/ T2 Z( g' i( {5 y% e* K) `
1745332 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern
5 `1 Z$ O$ l* b1765555 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during contour routing
5 d r; b3 z# D6 M3 I1644401 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on running the z-copy command
+ ~: `+ S: z3 d/ g4 U6 V/ f& M1657621 ALLEGRO_EDITOR INTERACTIV Copy cline and via cause redundant vias" X# w& S1 D9 I! b
1688556 ALLEGRO_EDITOR INTERACTIV Limitations with editpad boundary
+ a1 D, G* ]! f7 U. a: ~1704901 ALLEGRO_EDITOR INTERACTIV Changes cannot be done when 'Design outline' is selected
* z) L. I- D# s9 B1710731 ALLEGRO_EDITOR INTERACTIV The Edit > Change command does not select or change the text on a block' c- A9 p7 s4 V/ b/ k1 N' b
1714855 ALLEGRO_EDITOR INTERACTIV Placing two objects on the Design_Outline subclass causes PCB Editor to crash
9 ~! @* a- m" \: h% i, f. \: X7 w1725736 ALLEGRO_EDITOR INTERACTIV Edit>Change cannot change silkscreen line to a different class, but works in preselect mode q1 G" q9 _" x1 \
1728004 ALLEGRO_EDITOR INTERACTIV Text cannot be edited if the Design_Outline subclass is in the selection box) K$ I3 f; w$ S9 J& \
1728794 ALLEGRO_EDITOR INTERACTIV The Oops command and the Esc key do not work when moving components in the Temp Group mode7 k; U/ D0 @2 e0 {
1738070 ALLEGRO_EDITOR INTERACTIV Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'# |, k6 G# T6 G
1750696 ALLEGRO_EDITOR INTERACTIV Add notch angle option fails to update if changed while add notch command is active.
2 u, Z' R2 |) f' Z0 Y( Q' `1755240 ALLEGRO_EDITOR INTERACTIV Copy via does not work4 `, |% j0 Y6 X7 B7 v
1777416 ALLEGRO_EDITOR INTERACTIV Running shape operations results in database corruption
" |! ~/ K+ o; \1715835 ALLEGRO_EDITOR INTERFACES When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses
4 D* l9 w- [& v7 g4 G6 k0 g# ]1744111 ALLEGRO_EDITOR INTERFACES Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor
8 g3 y/ _1 R3 [' R# e3 {$ H3 R1736045 ALLEGRO_EDITOR MENTOR Third-party import crashes PCB Editor with error stating that .SAV file will be created! o/ q- l% x: r, Z
1751914 ALLEGRO_EDITOR MULTI_USER Find Filter options get disabled while creating symbols0 O9 g [. \( K# I; U( c H
1770811 ALLEGRO_EDITOR MULTI_USER In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting9 j) `0 [7 Z2 f0 Q
1736545 ALLEGRO_EDITOR OTHER Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor
8 H! N. c8 j9 k* U1761610 ALLEGRO_EDITOR OTHER Dynamic shape is not voiding as expected.
4 P: `6 c) _: q+ B( ?5 d9 ~; @6 A1702535 ALLEGRO_EDITOR PAD_EDITOR After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file5 l3 s) d$ h* v) N
1713461 ALLEGRO_EDITOR PAD_EDITOR Padstack editor default geometry not working when cell is preselected+ m v- C/ t2 h( v
1715702 ALLEGRO_EDITOR PAD_EDITOR Donut shape is lost on cutting the pad shape of the donut pad8 y) J7 p' ? H9 L: x; [
1720300 ALLEGRO_EDITOR PAD_EDITOR Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016* O2 h J1 d1 t
1724896 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'! N; v6 _% k6 k+ a0 Q* v
1714839 ALLEGRO_EDITOR PLACEMENT Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group" Z2 ?" r* p, K- j
1781502 ALLEGRO_EDITOR PLACEMENT Quickplace by room crashes Allegro PCB Editor9 X. a6 t' \7 E& F% h
1699690 ALLEGRO_EDITOR SCHEM_FTB 'view_pcb directive' no longer working as expected
% ` l2 H& D7 E t" ]( ?1758796 ALLEGRO_EDITOR SCHEM_FTB PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive
7 {5 S, K4 l: x1761101 ALLEGRO_EDITOR SCHEM_FTB On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder
' B, }* C; ] X# R$ _2 u1761394 ALLEGRO_EDITOR SCHEM_FTB Working directory for PCB Editor changes after import logic
2 \2 G2 {; @1 R. B/ ?* ]1714922 ALLEGRO_EDITOR SCRIPTS Running script in the non-graphic mode runs the tool graphically! _' K& f6 X: l; A: k
1726550 ALLEGRO_EDITOR SHAPE Shape failed to connect to pin G$ ]9 f: R3 [4 X8 V% ^, ^1 n- U% t
1754945 ALLEGRO_EDITOR SHAPE In release 17.2-2016, Delete islands fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems: |! ?' H. v9 e0 F4 @
1766280 ALLEGRO_EDITOR SHAPE SPMHGE-300 Polygon operation failed because of an internal error/ |& t2 I! E( f! v6 Y5 O' i) S8 c
1768307 ALLEGRO_EDITOR TECHFILE Properties defined in the technology files are not being imported in a new design
# I( M% ^7 S" F. q1771584 ALLEGRO_EDITOR TECHFILE The tech file import command does not update user-defined property immediately1 N w7 m) b. v" a1 p3 V7 u
1730104 ALLEGRO_EDITOR UI_FORMS Change description of Title bar option variables in User Preferences
9 S8 |# f% c) y/ N1749272 ALLEGRO_EDITOR UI_FORMS etchlen_ignore_pinvia variable needs to be updated3 l P9 g% j1 s* s2 Y- g4 a
1649254 ALLEGRO_EDITOR UI_GENERAL Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
8 n. c& D- g: r1685985 ALLEGRO_EDITOR UI_GENERAL Funckey not working for Display - Measure% h1 Q/ g3 d$ W% ^' B5 `9 _
1687073 ALLEGRO_EDITOR UI_GENERAL Show Measure command shifts focus to Search field in result window after selecting first element/ f5 |. _% T5 P, U1 ^" ^/ w
1699272 ALLEGRO_EDITOR UI_GENERAL File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled ~4 j! L( w# j3 D! b
1711321 ALLEGRO_EDITOR UI_GENERAL Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()6 Z, ^! n6 G# {1 Z: g
1728468 ALLEGRO_EDITOR UI_GENERAL The Show Element window takes the focus away from the PCB Editor window
9 l- S/ a$ e! h6 v8 s9 o- ^1733690 ALLEGRO_EDITOR UI_GENERAL Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 017
R, ~7 ?8 Y+ S1734176 ALLEGRO_EDITOR UI_GENERAL Unable to sort padstacks to open in the padstack editor using wildcards) i' _& v- ?: \8 v1 C* n
1735733 ALLEGRO_EDITOR UI_GENERAL RAVEL checks slower in release 17.2-2016, Hotfix 017, p% t. y; v7 `5 w
1737545 ALLEGRO_EDITOR UI_GENERAL axlVisibleSet is slower in release 17.2-2016
9 c$ c( t* j0 g L3 F1744655 ALLEGRO_EDITOR UI_GENERAL SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6. L' Q5 C/ J9 G7 F
1759380 ALLEGRO_EDITOR UI_GENERAL axlLayerPriority API changes layer visibility and colors
9 Z \1 c. K: O1775071 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL( h0 a# j7 I- S- e, ?6 A1 _
1708554 APD GRAPHICS MCM shape lines are almost short and different with DXF and Gerber files
" P% u& L K3 m! X1 N1678824 APD SHAPE Updating dynamic shape fails to void all elements on layer L2.) G8 ?, t& {6 ~
1742335 ASDA COMPONENT_BRO Libraries missing from new Component Browser
b# L9 P8 Y4 I7 X+ M, X1779777 ASDA CONNECTIVITY_ SDA: Net name and physical net name are different
, W; @' R2 D& i5 [1 X9 p( E1721919 ASDA CROSSPROBE Cross-probing a net from the .brd file highlights the entire bus in the schematic% `: s" o9 ~0 o8 r
1714313 ASDA EDIT_OPERATIO Filter does not work correctly in the Change RefDes form
7 Y/ Q4 n/ W6 @4 f1730809 ASDA FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly* z/ E# T; m! j# W
1747397 ASDA GRAPHICS Pop-up DRC descriptions are too small and cannot be read+ n0 i. g9 o8 i+ Y! `$ G) u/ ~) V
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix
; O; s3 U; R$ T: i# T1723535 ASDA MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands7 q. t; N5 ^, O$ v3 k2 d
1699936 ASDA PAGE_MANAGEME Page gaps created while moving pages
0 x1 b- u Q u w5 v: |1737180 ASDA VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA+ d8 }# {( ~! l2 I
1763247 ASDA VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.1 M! q" e% `, n- ~
1733971 CAPTURE CONNECTIVITY Auto connect to bus not working in the attached design9 c& G) F" N6 c2 q; u7 d
1236010 CAPTURE DATABASE Capture is very slow in processing designs.
5 K: P, o, ]) x) K/ g5 }1 V1518560 CAPTURE DATABASE Large schematics are slow to respond
& m7 V# c1 T+ Q4 [1705592 CAPTURE DATABASE Capture hangs when switching between schematics that contain nested netgroups
) Y2 R, R3 x4 U1770687 CAPTURE GENERAL In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error
1 g! d F3 `5 Q; B1692435 CAPTURE HELP Version Info Window is empty$ F }" H- C/ G1 V G" E
1767374 CAPTURE NETLIST_ALLEG Capture crashes on canceling the netlisting process
1 X( d, v( _% w" L* s1719613 CAPTURE OTHER Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash* U9 `9 M* `$ Y; y+ t4 E
1746663 CAPTURE OTHER Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018# B7 ?& f" p5 }0 G5 ~7 V
1709179 CAPTURE PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.- @1 B8 z* c% y d
1714121 CAPTURE SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property
- N- Y6 S/ h, t" A1729861 CIS OTHER The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon
6 z0 n' I C8 N% D1333600 CONCEPT_HDL COMP_BROWSER Sort the sections numerically in Part Information Manager7 b0 C* k6 d. z# ?% B" r& s' b1 ?
1758761 CONCEPT_HDL COMP_BROWSER Incorrect Version showing in Component Browser in 17.2) M9 f; T' q0 G) J1 }0 V
1769591 CONCEPT_HDL COMP_BROWSER Modify Component / Project Information Manager (PIM), parts take longer to load in EDM
6 I* L: _' v# h B+ J# ]1479711 CONCEPT_HDL CORE Mirroring symbols causes alignment issues
1 O% R4 h1 Y6 D1 q1696208 CONCEPT_HDL CORE Display issue with the grid visibility after a save hierarchy
1 P" R4 v& X1 N1 _- f P1698802 CONCEPT_HDL CORE Pin number overlap with the pin stub when the component is mirrored.
( r( C9 ~6 l3 \0 m" X8 h6 b# O+ r# j1708917 CONCEPT_HDL CORE nconcepthdl crashes on a design with a core dump
& v5 X$ l8 [; X9 S1 E7 v+ B/ z# S1744815 CONCEPT_HDL CORE Deleting a page crashes DE-HDL
# T! h* | } z- \! X I1751863 CONCEPT_HDL CORE 'Move' does not move body but only properties of selected part
& f- f! D7 B/ s6 C1763556 CONCEPT_HDL CORE Component Alignment and other graphical feature not working in Windows 10
, c) }) { e4 E: S1 k8 S3 b' Z1725121 CONSTRAINT_MGR CONCEPT_HDL Audit report of ECSets reflects some gaps in certain columns* I( S7 L5 q/ n6 D
1758740 CONSTRAINT_MGR CONCEPT_HDL Extracted topology does not populate the gather control used in the ECSet
% x2 A; i) ?* G/ i- Q1759580 CONSTRAINT_MGR CONCEPT_HDL Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix': l. Y0 F q: E9 M8 z. M
1759590 CONSTRAINT_MGR CONCEPT_HDL Unable to create bookmarks in Constraint Manager7 Y) S5 _7 r0 S5 {
1764597 CONSTRAINT_MGR CONCEPT_HDL Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.
0 i) B) C, L7 ?* E; R R6 ~1771427 CONSTRAINT_MGR CONCEPT_HDL Decimal units specified in the precision settings are not applied correctly
v9 }' i& q# `1700402 CONSTRAINT_MGR DATABASE Parallelism violation DRC not reported until cline is moved
' b3 x; p& l1 J& a x" F4 }9 }1700370 CONSTRAINT_MGR OTHER Constraint Manager: Expanded nodes collapse on restart% k# G4 |2 A8 A g6 C/ t
1735636 CONSTRAINT_MGR OTHER Inductors are extracted as resistors in the topology; D) A! p+ k. j" R; X" E$ X, ]
1776917 CONSTRAINT_MGR OTHER Creating advanced formula causes the tool to crash; x; t! A+ ~* U2 n
1762979 CONSTRAINT_MGR TECHFILE Constraint Manager does not retain values after importing tech file0 I' N: u) S9 R
1699275 CONSTRAINT_MGR UI_FORMS Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order( g7 L3 i1 q# {9 [2 v+ t( x/ k2 m5 Z
1699312 CONSTRAINT_MGR UI_FORMS Typing *.* in the File name field does not display all the files in the Import Constraints dialog box
, K; J, f) |- N1 w: @1742134 CONSTRAINT_MGR UI_FORMS Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected
# C$ \8 U% E" F- a1755576 CONSTRAINT_MGR UI_FORMS Constraint Manager: Physical CSet filter not working correctly
" ^+ Y# H2 j" i; {- g1775333 ECW DASHBOARD Activity Log is not accessible to ECAD_Integrators if they are not part of the project team, {9 A3 M) T/ F' Y7 E2 K5 l
1749220 ECW OTHER Remove 'Role' column from Users web parts/ f5 z! v$ P5 l9 {- E
1716527 ECW TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout
9 r' |& w5 P, N' D7 F1724195 FSP SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor# h4 y2 N2 d. }! k C
1725479 INSTALLATION DOWNLOAD_MGR Download Manager error prompts user to close downloadmanager.exe
3 C% U+ r5 K/ x' ^% \8 N1738952 PCB_LIBRARIAN SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows) I1 p* ~1 j) b9 I% T5 p
1638740 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
% |3 G/ o, C2 s+ r9 y. P+ }1699822 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
+ n% o( W' k1 W4 {2 v* d- l1652265 PSPICE MODELING_APPS Cannot place PWL source from PSpice Modeling App
, g5 W1 O) ]8 C1685967 PSPICE MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App
7 a3 |: I. z; p) g1716313 PSPICE MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 0144 e5 G/ E5 O- w" Y6 F
1738747 PSPICE MODELING_APPS Inconsistent file type for PWL part in modeling application and source library8 a! G( R2 ]% n* T) h* o, a) y
1762202 PSPICE MODELING_APPS PSpice modelling app Tcl issues
. _6 Z* t7 |) x! G1736605 PSPICE SIMMODELS BSIM4.6 model parameters incorrectly handled by simulator+ x* j( p# Y, X8 p4 C
1442623 PSPICE SIMULATOR Bias points are nor correct in attached circuit
( A, ^6 w* b0 B! w/ i; g4 K# c( R& \1618815 PSPICE SIMULATOR Bias Point calculation appears incomplete
7 _" I% O% _: R! S) x4 d1723039 PSPICE SIMULATOR PSpice crashes when curly braces are specified for the ETABLE parts+ \: Y% a: u/ `& M; m( o
1782353 SIG_INTEGRITY SIGWAVE SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023
; p% p* n1 o1 ?! e! a1745940 SIP_LAYOUT DATABASE Cutting a part of a tapered cline does not remove the connectivity on the dangling cline) k, m1 Y- _2 f2 a6 W/ \9 i* B0 C
1780072 SIP_LAYOUT DIE_ABSTRACT_ Export->Die Abstract File causes a crash
+ W7 w& H4 f% D1736396 SIP_LAYOUT SYMB_EDIT_APP 'No such child' error message when deleting pins in symed
1 {! B5 T1 h6 W, g$ }1769728 TDA CORE Default policy file needs to be fixed
+ d8 Q6 s/ g9 \) A+ W. L* F1735682 XTRACTIM GUI XtractIM translation is incorrect: adds anti-pads
% V& ]# i" z- o' P0 T& n- u3 V% x$ l4 M2 x4 O1 @( p/ T9 O9 X
5 t% L: A0 c; Q# Q
Fixed CCRs: SPB 17.2 HF024
D! [3 o/ V+ j Z {: t! w0 B/ e07-28-2017& @# S2 `8 N' U6 P2 h0 i# H/ Y ?
========================================================================================================================================================4 \% T0 W N. a
CCRID Product ProductLevel2 Title" I2 W5 ]0 b+ z$ s1 |% n! N
========================================================================================================================================================9 B3 W L7 c% K) C/ g4 p/ L8 y/ Z
1762143 ADW COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property
* C# S( Y- S4 Q7 |. u: {1765790 ADW PART_BROWSER Fail to extract component part number and footprint information8 }" n% z w* w! @1 R2 ~+ _2 u% X
1757719 ADW TDA TDO and Windchilll Work Group Manager out of sync at times
' P; [' s. O1 H, p2 ^! n1760607 ALLEGRO_EDITOR DATABASE Value for number of decimal places changes in Pad Designer in release 17.2-2016- p# E0 u) U8 l0 `" H
1775160 ALLEGRO_EDITOR DFA Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016
: j8 l8 L+ M, L; y! v U1765984 ALLEGRO_EDITOR OTHER Cannot view System Info5 ?# T1 K0 q& j \
1729350 ALLEGRO_EDITOR REPORTS Net loop is not listed in report
5 u3 e& X( R! z3 ]: d1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
: _! R. C* h# C' f1754402 ALLEGRO_EDITOR SHAPE Illegal arc radius error (SPMHA1-85)2 S6 j7 Q) `/ k% }0 K) J! s: B4 l
1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids
! m, ~( w; m* h! _0 H/ ?. ?1769188 ALLEGRO_EDITOR SHOW_ELEM 'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
( C# O7 {- S" Q4 I1767690 ALLEGRO_EDITOR TESTPREP PCB Editor crashes when running automatic Testprep4 U- G* O8 ?1 C* K r* ^
1737337 ALLEGRO_EDITOR UI_FORMS Pinned Show Element window closes when opening new design in release 17.2-2016
- t9 V2 P+ ?3 f$ f1736642 ALLEGRO_PROD_TOOLB INTEGRATION Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox
! \( p$ C9 m& y1685216 ALTM_TRANSLATOR CAPTURE Third-party translator placing symbols off grid
, F; I V" p' x% B0 Y, v3 }1738679 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
1 i' W5 Y! [1 ^) Z- w3 V R1738705 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
; V! e: _% s+ ~8 s+ d1748583 ALTM_TRANSLATOR CAPTURE Crash on importing design using third-party translator
' Y! P, t( T# U3 G0 R3 R1679310 ALTM_TRANSLATOR PCB_EDITOR Third-party translator should fix off-centered connections8 i8 Q/ G4 \& D$ y' r
1686845 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not place parts after successful translation
- y, q% O6 W& p1 V4 c1723141 ALTM_TRANSLATOR PCB_EDITOR Placement outlines are rotated in third-party translator- l* u5 f0 b' ~7 m0 ~- f- n& l
1723164 ALTM_TRANSLATOR PCB_EDITOR Third-party translator creates board with missing data: vias, traces, and so on
) K3 Z9 f) K P1 A% h/ `! k# D1723190 ALTM_TRANSLATOR PCB_EDITOR Third-party translator changes design origin6 {% {, x+ I' ]# \+ Z& ?/ _
1750496 ALTM_TRANSLATOR PCB_EDITOR Third-party board with arc tracks not correctly converted to arc clines
" ]9 O1 ?' m; V/ l1769624 APD DATABASE Attempted symbol delete crashes APD
9 b. R( \5 u N* Z( P( }1727206 APD SHAPE Merging two shapes results in an incorrect shape
9 a- N- l' W! {3 B6 V g1707756 ASDA VARIANT_MANAG Scrolling in Create Variant closes tool4 I3 z+ l2 u) z. H# \
1753699 CM RELEASE installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed
$ v8 N; w+ d" t1741534 CONCEPT_HDL CORE DE-HDL freezes when selecting a net that contains many connections
, }5 v9 y# m% x# e, c9 k n1752687 CONCEPT_HDL CORE The move command changes the connectivity of the schematic4 e/ _7 ?- P* O: x7 q5 Q& D, u w
1763525 CONCEPT_HDL CORE Genview crashes when generating split symbols
& V8 R+ L9 M/ o6 h' e1766797 CONCEPT_HDL CORE Schematic not refreshed after using the clear xnet overrides feature
' W9 ~9 d( G9 T- k4 H+ t! a1770852 F2B PACKAGERXL ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
. w& J6 ?3 ?" S1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
9 k' ~% a( u( U3 r. n1748106 FSP OTHER Create protocol from existing protocol error message needs clarity: h' Z( \, O; G9 V" H
1724201 FSP SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor
. G( H, ?$ w O5 Z4 T0 f1772429 ORBITIO ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor
$ k2 ?7 R* L' l' O' g a0 F# P& y1725759 SIG_INTEGRITY OTHER PCB shape/plane capacitance' m* H1 e7 I k
1760924 SIP_LAYOUT DIE_STACK_EDI Package height of die .dra file reset to 110um when placed
8 N$ q8 C$ k; J: K3 U1764385 SIP_LAYOUT MODULES Embedded components are unplaced in created modules (.mdd)
8 G& o! }/ @! b7 e: l! i; m1733679 SIP_LAYOUT OTHER 'metal density scan' does not use select window z2 f$ t: `- @" V. F# Q v
1763707 SIP_LAYOUT OTHER SiP Layout exits with error message in release 17.2-2016
\# h7 r! i/ E1763515 SIP_RF DIEEXPORT Virtuoso writes incorrect width for 45 degree path segments in XDA file" j+ O7 o5 {/ _/ m8 |
1772397 TDA DEHDL DE-HDL crashes if license is not available for team design$ O) _% L' D: l
1 u& D' @' c4 z7 }+ ]4 i) s) M8 W2 z$ E6 v' G, z
Fixed CCRs: SPB 17.2 HF023
4 h' M% _4 E2 F7 u! d07-7-20170 C$ F* H' J- `2 b @/ a3 p9 d
========================================================================================================================================================
6 o' r4 y! V/ E3 rCCRID Product ProductLevel2 Title
* |' S) o! ^+ N. Z6 h8 \$ I========================================================================================================================================================
! Y, g, o l$ Q2 d- L1 ], }1 q4 K9 u1703281 ADW ADW_UPREV Design_init needs to support the -cb command$ n" t0 q- z0 [2 n
1762238 ADW COMPONENT_BRO DEHDL crashes without reason
* U" c( S$ A) ]. Q1759467 ADW DBEDITOR DBEditor does not recognize that 1.10 is a higher version than 1.9
* U5 q; k, S1 q& C1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
5 S7 q, G" A" V1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager9 h( R+ n1 D: {& Z3 \
1757443 ADW LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file
6 `- v' R; G4 v; Q1752126 ADW LRM cache not getting updated with std models when moving from 16.6 to 17.2
- O+ ]4 X- W. m8 u1754444 ADW LRM Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."% j Q4 W; u9 Y7 l+ B, @
1715861 ADW SRM symbolrevchk.par has incorrect variable name for SRM to ignore the tool version
, F }$ M4 j4 l# P5 D7 f" F1628403 ADW TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts
8 G: c5 e o q$ [1759250 ALLEGRO_EDITOR DATABASE Flex-rigid placement does not move bottom pads to nearest layer, n$ i3 o: y5 a& r/ y
1762782 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating artwork
* J- L0 K5 A9 O) w) L! @7 D1746665 ALLEGRO_EDITOR DFA Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only
0 [9 ~9 w8 [) ]/ C8 M7 {1750084 ALLEGRO_EDITOR DFA DFA spreadsheet disappears from the DFA library if hyphen is present in the name O. q. U4 S' u+ W
1697155 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measurement windows not saved in PCB Editor' c1 X A3 Z$ E2 x4 l! l( g2 D
1734282 ALLEGRO_EDITOR GRAPHICS Placement of reports and pop-ups not retained in PCB Editor' u8 T' [) q! d" t/ G
1740863 ALLEGRO_EDITOR GRAPHICS Show Element and Measure windows do not retain position
- @' u) d( K8 h- a- r# v% E3 Q1749687 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-2016% E3 h. {. s! ^) a
1764124 ALLEGRO_EDITOR SCRIPTS Replaying recorded script file crashes PCB Editor
; F5 z: t: @& r& _( X+ N/ _3 u1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids, L" N' V9 o5 n2 Y; X" @' ]
1763619 ALLEGRO_EDITOR SKILL Incorrect text block name when extracting text parameters using SKILL
3 k% R; O* x8 X; S4 `- `8 B6 {3 D1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas1 s% W7 {* n$ i( A
1733552 ALLEGRO_EDITOR UI_GENERAL Although F1 is defined as an alias for another command, pressing F1 opens help! j- S' W8 i( v; p. E& O
1735098 ALLEGRO_EDITOR UI_GENERAL axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016: R) I- K5 ?: _& i8 e5 ?; M
1753430 ALLEGRO_EDITOR UI_GENERAL 'Tools - Quick Reports' opens only one report at a time
3 P3 v r! R% X- M" @. |4 c1754283 ALLEGRO_EDITOR UI_GENERAL Call multiple reports from a function key
2 W' a& j0 y5 ^& Q7 u4 S1742822 APD STREAM_IF Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270
6 A/ @' n8 j- Z7 Z2 h3 M$ @1762284 ASDA COPY_PASTE Copying testpoint crashes tool and eventually the operating system
- \7 ]9 \0 |- z9 I1 ^1655057 CONCEPT_HDL COMP_BROWSER ADW Part Manager and Component Modify hangs
' j! o' W3 j1 T3 X( `* x1689740 CONCEPT_HDL COMP_BROWSER Bad response time using Dehdl component browser. H! u7 D( p0 [0 B! Z! @
1735332 CONCEPT_HDL COMP_BROWSER Sort in mathematical order Symbol list in Component Browser
. i: e9 \4 Y6 i; x7 D6 ?1739197 CONCEPT_HDL COMP_BROWSER Part Information Manager can`t sorted symbol version2 v& C% @% @) H2 D& Q2 E) ^
1764605 CONCEPT_HDL CORE Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'
8 F: I# j; w# T) i) r1761706 CONSTRAINT_MGR CONCEPT_HDL cmDiffUtility has a typo in the usage statement; |: j5 w: s3 B/ W4 O
1758426 ECW DASHBOARD Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart
8 }+ N8 w T7 `1764096 ECW PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page
% v) j; p+ l1 x9 K1764070 ECW TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure
) Z' x" P) C# O6 n4 z1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes( v* p% n; c2 X5 |" ^; L
1724124 FSP DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window
3 p/ m- k u G1726548 FSP OTHER Unable to open FPGA system planner if username/log file path has Cyrillic letters% J* A, v* ^7 K# Y* K' y
1719133 SCM SCHGEN Voltage symbol not getting placed for some of the voltage nets2 A7 q5 j4 x' K
1680989 SIP_LAYOUT ARTWORK Artwork film set-up: Match Display including invisible layer
d# Y7 o2 j6 m1 s0 f' |8 A3 @1732218 SIP_LAYOUT DEGASSING Shape will not degas as needed - not all voids degassed& a: Y! ]7 [! L1 M
1763280 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda0 A# T7 c. p; o% o- Y
1762992 SIP_LAYOUT OTHER Saving a design after adding a solder mask layer in the cross-section crashes tool9 q) r' Z3 I% j1 I \
; J" w6 u$ o1 f2 |4 z, S* ~& E) }0 `' m( T* W) q9 i4 \' A4 @$ l- ~
Fixed CCRs: SPB 17.2 HF022# ^5 K* l/ Z- ?8 E
06-16-20179 Y3 G5 Y2 y' i" S: q+ y
========================================================================================================================================================
0 B; q" y# t8 OCCRID Product ProductLevel2 Title
|0 j) N% C* ?9 `! h9 q* W& F9 m========================================================================================================================================================
6 k: C4 z' v9 p1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
% d% T# i+ I, A; M5 t5 Z. Z( X2 u1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
/ m; Q* x) v( ]. l. |8 B* o' t1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
R9 k& h+ |$ o! r( ~* h) v9 l, ^6 q3 r1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
. T) w ^1 y: e1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
( t# `: [+ d! R) f! |' {, J2 R# L1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
* _+ j8 J' b; \3 E1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
- K. L4 [( J6 L8 o8 z4 D& P; i' }1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it3 l; l" y: h1 _
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
7 {2 | ?0 o3 O' I" y, q) w6 y+ ?1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor
. Z4 y$ {2 |8 L1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
1 h6 Z3 R2 X: h. H1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
- {/ w- O: j2 X o+ ~3 u1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
8 ~5 R* d# C$ ?' [. X1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.2 e5 j1 ?, ^# {4 I; w9 E
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
8 j/ }* `8 ^% j1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
# O. n6 n) w% c; X9 j( x1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture0 R& O) f. I( G& N& [ L! ]
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool7 {/ j9 C5 I0 x0 M' U0 a
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
9 Q' w- c6 T9 B$ _7 L: [6 c: k1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
, f0 `# M K$ }2 B' h1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails
6 }0 R/ C6 j( T2 X- M1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016- r$ u, G, S/ d% M
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
/ l8 M/ D; K3 y- F1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias6 l% E8 l: _4 W w) z
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
D+ q' z+ [7 ~+ K) i6 j1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
0 O7 i( Q+ _/ d: [' F& a; ~$ U7 Q1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
# p! b3 e6 B% T- w1727206 APD SHAPE Merging two shapes results in an incorrect shape
4 I3 [: M; q! X9 v! T' Z1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
1 Y# z$ \2 T$ ]- s1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic- P" R P+ e: w6 w( C* K; Z
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
! Y1 A) }4 b5 k( u1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
* P( v4 J1 J# f8 r1 C; Q1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option% f' @" {0 B; k& A k- f
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
9 Q( |0 x9 q+ W; X, b" g8 n. j+ I1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
# W- X ^6 P6 P! w. ?1719105 FSP GUI Tabular sorting not working in FPGA System Planner
0 R, n0 q8 t9 _+ y& U1 [1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
' C! B8 V( `" n% ]1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
, @* P% ^- n2 C7 o! _1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window, T) V' C/ x& i, q0 |7 }# a
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files- ^# Q: I8 C, L$ |% z+ v# K
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
' g3 f/ w4 B, \! j! ]* m( s" q- l- M
- |( ~7 f3 X1 Y8 p2 F! x& V& p
Fixed CCRs: SPB 17.2 HF021
; J2 j/ \7 X: H% x% H06-3-2017
' x; ]6 P" X/ i! e+ x========================================================================================================================================================: F% T$ }+ a' y/ p- f2 r) g
CCRID Product ProductLevel2 Title6 j& i3 M: Y' b
========================================================================================================================================================
. a1 H5 L l) k1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
% m5 O# q' P4 X6 i3 f% M* M0 { C1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
' q1 Z6 n" {, v1 g3 r5 {1743997 ADW LIB_FLOW Match file for standard models is incorrect3 F* ^4 u+ x8 g% f8 v( I$ I
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property6 h& q- _# B) c* O4 U u
1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer
9 R* _! L5 c; U( |0 D& S1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
4 u E: ]. d6 ~4 {; S! F1 W' H2 Z1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command0 k y+ I. p1 E- R! J
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
+ J b, H& x( B- ^1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops: a0 M! N3 N$ b1 I/ d t1 L
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets) ]* d$ I1 Q0 _/ v
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty3 N& Q) p6 I. u1 Y. b
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
# J( {* _, v7 U# H1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
Y8 ]7 M* |! k7 e9 e1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database: `- P: h! v7 `& X
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry% L: J; \5 @. n; `$ R9 z
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol$ w1 {; u. Y) C- T
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
1 O3 v% N3 R$ a7 }* t( m1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
0 q: q- r) @$ b3 N1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016/ ]* |2 v9 ^% j0 N- J
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors3 I9 Q8 `5 B; Q& _& |( x
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
& S8 `9 N( @" q0 l! S. A4 B1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
# u1 B# d K4 w1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working
' O' h% S( t; ?( K4 ^1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
* l1 B$ h0 T7 @% o6 y0 Q+ [ z: x1750182 APD STREAM_IF The stream out settings are not saved
2 V; b. W8 y) o. s0 Q" E1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report
( z" x0 b' d7 v' L2 K1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version4 G7 O* X" L# j7 I) x4 o6 w0 X
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser* t `* F/ o! h, }! G$ \
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint/ y, ~8 W' `8 o9 ?8 {! f+ Y
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic' l3 D" X( H2 j9 E5 a8 c: l2 S
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-20169 t" F& Z0 Y: M$ y$ v' q1 L
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
) V3 b9 D! H# h( H6 F7 K, b' b1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
; K' s: ^+ K( F1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
; l6 A( s. M+ ^6 A, M. U( |2 G1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
. R* ?3 T1 n, x8 K1753010 ECW METRICS Metrics not getting collected due to old license in use
" ]: S% S' V6 s1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
' G5 @# ?' p4 ^$ k) V1719099 FSP GUI Net naming wrong after building block
% \+ G2 x/ U U: |/ I' V8 \+ v( G1719105 FSP GUI Tabular sorting not working in FPGA System Planner$ F. E, M6 b% R+ c! Q
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems# q6 m6 g7 k+ {9 H, ?4 s
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
- Z$ T" b4 F. K% P, S; R6 @ K1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
$ c3 f% D8 U8 o1 N1 [9 R$ A) X1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing7 u( d* L# E9 I, a0 |( i
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
; v' c, ^' N- H" e# X1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets" G: q9 D; \1 N1 H0 T- ~& q, x" E
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
1 ]! I* T% [2 r6 W
" r, M" u- Y- E, V/ t% ?: t; S! N) t% b' J% g; o+ P2 l m. R6 I
Fixed CCRs: SPB 17.2 HF020 W; C B" c7 D1 [: ]$ d
05-21-2017
/ G, k$ J0 x& W========================================================================================================================================================& P R5 }. p5 G9 D
CCRID Product ProductLevel2 Title
& t4 S7 F. D" J* E( @0 W========================================================================================================================================================! |& N+ Q1 s9 K
1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised3 x* ~! R, b0 e, A
1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016
. o/ u1 ~! i2 V8 \6 u1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
+ ~; i, `: p9 E* g1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash- a0 S0 V! f: k9 d& N
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts
1 Q. l5 {1 ?2 ?2 v$ U1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness
- {! ~7 |% K, [: U) `! u1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
4 ~6 `( y6 b! Z6 w/ {9 R. M- N1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor, `/ U; f: r* |& y1 U m* B* D
1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working.6 L& { D( G( \% E5 A2 Y# P5 r
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations8 l% B2 \8 b6 f
1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 17
; ]5 R7 D% W. }; w7 l4 `& d, I, ^1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file( [9 @) w X- S' ]. O
1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run- L- x" J! q$ Y* W
1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
( D* R1 q1 {8 o$ ^: O1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
% ^2 f+ `+ w3 I5 d: @. S. P( u% ?1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function' n2 h% w8 A( N8 n
1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows# g/ ]! W6 }( i u# {" [
1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
8 r# F" u2 x" U9 t0 q2 p1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2+ ^3 n3 U7 A5 b5 v/ A' O) ?
1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18
% ~! C0 Q7 P8 j& j0 v0 k m1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape8 {& j9 }1 p/ B, x' _
1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected
* x! j% [4 r" [: v( [2 n a1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2
! x) c1 \4 S! b& E( N; g1 J e1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol! `8 z3 e: t% S& z6 d" j0 O
1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol& P1 V) f; n0 O, q$ z
1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts2 h0 k8 G+ B& b& X" ~/ G9 a
1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager' E" J! }3 O9 w8 N7 b7 {
1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP5 [) \0 F# N9 B7 Y/ f
1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer
, r4 N9 m3 k* R+ f8 l1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles
# z& Q8 r! ]( t/ ]1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.21 ]2 o" ?: G+ n* H
1735354 PSPICE SIMULATOR Access to custom nom.lib is not working as expected/ L2 P9 _- o) l1 b$ ?3 G1 B
1716523 SIP_LAYOUT COLOR Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.+ d9 O+ q3 e5 J- M: q% K
7 q, J) x- L. @' J( ^, |
9 ?3 H3 U* I% c: Q
Fixed CCRs: SPB 17.2 HF019; N2 T% a9 ~7 S4 Z, A
05-6-2017
6 P1 R2 P5 @; ^; C+ s========================================================================================================================================================
M6 o+ n( J6 Z( fCCRID Product ProductLevel2 Title4 G9 `/ V! j5 x/ l/ y
========================================================================================================================================================
. ?. E8 `3 i, V& a/ w7 M( }1701785 ADW ADWSERVER Getting 'Unable to locate tools.jar' error while using 'Copy Projects'
' |# w4 l) k3 K: V9 h, P8 x) f1706782 ADW ADW_UPREV Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'
6 b* A% t- h u1508159 ADW FLOW_MGR Flow Manager 'Open Last Project' option points to a deleted project
, S* Y$ F- C% t9 S- B2 |1690903 ADW FLOW_MGR Flow Manager library project list empty after 'Remove From List'
1 F7 w* Z2 W, G2 h. h" o1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
, R, B) f2 \$ `6 }1672037 ALLEGRO_EDITOR EDIT_ETCH Add ZigZag Pattern crashes PCB Editor
+ K% U; U P: X% ]2 O8 Y" W) i1695711 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10
* r2 W$ J4 H! C. e1706522 ALLEGRO_EDITOR INTERFACES DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline( f+ C/ X+ J8 V1 B! [' \
1716336 ALLEGRO_EDITOR INTERFACES DXF file is not correctly imported into PCB Editor
H3 g) y: ~6 X, z8 n H1720290 ALLEGRO_EDITOR INTERFACES Incorrect rotation of padstack after dxf import
1 \9 z2 ]* S& Y6 n. k' t1724683 ALLEGRO_EDITOR INTERFACES DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation1 z2 M+ s8 D) P7 t9 c- |6 |
1732587 ALLEGRO_EDITOR INTERFACES Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6! f: ~3 n( I0 Q; K; j
1737516 ALLEGRO_EDITOR INTERFACES IDX Import works differently for placed and unplaced parts$ w- i6 O; b+ ]% M" y2 R; E
1715152 ALLEGRO_EDITOR SCRIPTS Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'
! ^9 C4 @7 T( |7 N' D7 c; s5 K940699 ALLEGRO_EDITOR SHAPE Update shape to smooth fails to void a few clines.
* C6 g1 u0 `# D; `0 w) h [1 `1 @1706581 ALLEGRO_EDITOR SHAPE Dynamic shape void clearance errors with vias w9 k% S8 h( }9 b* J3 I& h) n
1638300 ALLEGRO_EDITOR UI_GENERAL Version information set in $cdsversion truncated on title bar for some tools
6 c3 Z% A: P# J0 j5 I l$ y1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
% l3 f! v& X. y0 t7 q1729510 CONCEPT_HDL CORE Changing the name of a split block adds pages that are part of the page gaps
& x) e' a: z" R& a* U1721065 CONSTRAINT_MGR CONCEPT_HDL Physical import errors on changing plane to conductor in stack-up- X. k0 _8 c0 W/ u
1734875 CONSTRAINT_MGR OTHER 'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context
0 V2 A0 b$ P) Z4 _9 w# e+ {+ n$ v1473104 ECW PART_LIST_MAN Pulse does not filter capacitor values correctly
$ p% i- s- U* K W$ b3 M1736580 PCB_LIBRARIAN SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor3 y, Z: \! y) t
1738955 PCB_LIBRARIAN SYMBOL_EDITOR Need ability to edit Symbol Properties2 b9 n& M* c+ |
1735215 PSPICE FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working# y9 [! p# V' D" u0 M$ W% m
1733198 PSPICE PROBE Probe crashes when exporting trace expressions with multiple plots to CSV files/ Z7 S* Q C2 v6 U" u1 v
1737060 SIG_INTEGRITY SIGNOISE signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
3 p1 c) ^7 Q) V9 ]7 M( d1707443 SIP_LAYOUT WIREBOND Moving bondfingers violates spacing constraint
1 v- C8 H* N' c. ^8 `
# r! V, h$ Z' T7 S
- ?$ c: s/ ^- k2 }2 H1 C) V NFixed CCRs: SPB 17.2 HF018
% A2 d4 Q& R1 U6 z04-23-2017
" n9 S8 P- C2 N========================================================================================================================================================* H" J. _0 B4 O
CCRID Product ProductLevel2 Title
5 l9 P9 Z' u' h% f) T# W! S+ G========================================================================================================================================================& b$ i5 y6 Y k1 Z" @" L7 c, A
1721773 ADW ADW_UPREV adw_uprev updates all versions in history log to the new version. Should only insert note about uprev. E0 t/ u# n$ X3 c) f
1684346 ADW LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server# o- m. f, \9 M% @
1696632 ADW LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
4 V# p" t1 `7 c1 T/ y; X1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016* W% g/ t. t2 c* ^1 U. H! l+ U' R
1721017 ADW LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
' d" l4 z8 ?. Q& S# Z1711373 ALLEGRO_EDITOR COLOR Cannot interact with Allegro PCB Editor when Color dialog is open
3 ]1 G4 B* _" ?$ M, g1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
) ~4 z+ z1 c* o8 l { z2 o1725621 ALLEGRO_EDITOR DATABASE PCB Editor crashes when moving a group of components or clines$ q9 |! W2 C& H3 o0 F6 v* ?
1699796 ALLEGRO_EDITOR EDIT_ETCH AiDT fails and reports there are no timing constraints even when propagation delay is set" S. y5 u5 }+ Q
1726483 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashing when converting corners to arcs
9 s. y2 H) L+ }: c7 E8 N1726678 ALLEGRO_EDITOR INTERFACES IDX copper layer export does not export all pin pads$ q9 N5 y; e* g Q
1691036 ALLEGRO_EDITOR MANUFACT Fillet not centered on trace& C$ \7 @; N) D9 O( e- p
1732304 ALLEGRO_EDITOR MANUFACT Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
2 p2 f: w+ u o9 u' _( ~1719564 ALLEGRO_EDITOR OTHER Cannot open PDF published in release 17.2-2016 in third-party software
- E5 q9 j- n/ B I) P% z1723065 ALLEGRO_EDITOR OTHER PDF out does not print the outline correctly
( s. \( U7 C$ R: w' }6 n2 h1729247 ALLEGRO_EDITOR OTHER Cannot delete shape on Route Keepout layer9 H+ |2 o/ B6 @1 w* V
1722747 ALLEGRO_EDITOR PAD_EDITOR Option to enable 'Connect by Touch' in Pad Editor9 N9 l5 j! |. T' z9 D3 _& @! O
1731643 ALLEGRO_EDITOR PAD_EDITOR Changes to secondary drill are not saved on padstack update+ k$ \2 D, p& m3 Z
1727303 ALLEGRO_EDITOR REPORTS The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016/ L \! H* s4 [7 }% W- b9 w! ?
1695879 ALLEGRO_EDITOR SHAPE Dynamic shape priority error creates shorts.
# J) Z& m. s6 x1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations5 H% A( z0 t, f
1588769 ALLEGRO_EDITOR UI_GENERAL Alt+key shortcuts are not available in release 17.2
3 p8 W# c' @5 p9 i7 g1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2$ S; {" u3 Q @! t# Z
1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands
( t- j5 i' @' _: C1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response
3 S" I. R5 i' Y$ Q1647271 ALLEGRO_EDITOR UI_GENERAL Preselection is not working for docked Find window
2 ]' g" ^. Z; @7 ]/ _1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2
1 M4 v- s8 h3 H1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key
) M1 C% e a. \2 a0 B) h1 @+ k7 C B d1679964 ALLEGRO_EDITOR UI_GENERAL Many dialog boxes are blurred in Allegro PCB Editor: Y: T8 [. j4 Z) w+ f. V
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2$ J7 f U% A$ d, s# B: i. U4 o% Y
1693055 ALLEGRO_EDITOR UI_GENERAL Reports with html links end with an extra > at the end
. |8 u) T2 {( n2 S+ c: f1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports$ G5 ?) q4 _( B4 x6 f
1698840 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue2 p5 p i' d7 i$ D& k% g, b
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
8 K8 M" A4 x0 Q5 ~9 p. \. Z1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
9 A m7 q- u" k1 `, h; R3 C$ G* D1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
, `* v h5 h9 t: _7 `7 Z1711203 ALLEGRO_EDITOR UI_GENERAL Color does not change for selected coordinates in reports and Show Element
5 {. j R: Z2 G% x1711724 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, custom interactive menus stop responding when invoking another custom command
, F8 X# g; g* R( R6 s$ W1715613 ALLEGRO_EDITOR UI_GENERAL With undocked Options window there is a mix up of entered text and funckey
: [$ H' C+ H7 V& l" B1719301 ALLEGRO_EDITOR UI_GENERAL Selected coordinates do not change color in reports and Show Element7 U V3 o2 \) v
1724197 ALLEGRO_EDITOR UI_GENERAL Short cuts and hot keys not working in PCB Editor in release 17.2-2016; r: [; j; z7 T+ q% m
1728724 ALLEGRO_EDITOR UI_GENERAL Funckey is not working in release 17.2-2016
( u! }, y$ L! I" ?1673703 ALLEGRO_PROD_TOOLB OTHERS Design compare not reporting the Top and Bottom layer differences
0 u3 @" f% _; x2 r; I/ y1704474 ALLEGRO_PROD_TOOLB OTHERS When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied/ q$ Q- L$ U2 ]; h! z( k
1571035 ALTM_TRANSLATOR CAPTURE Circles in third-party schematics not getting translated into Capture
6 _0 S$ l$ r6 u4 y8 k8 I1588911 ALTM_TRANSLATOR CAPTURE Capture crashes when translating, project and libraries are empty0 W% A+ [* r+ y! a, O- U
1589394 ALTM_TRANSLATOR CAPTURE Schematic getting shifted off the page after translation7 j$ I' s0 M, `
1631294 ALTM_TRANSLATOR CAPTURE Errors while translating third-party design when original design is in metric units
* V, b3 s0 i1 E- I- y1663176 ALTM_TRANSLATOR CAPTURE Only first sheet of design getting translated from third-party schematic into Capture* }/ @ ?0 a8 {
1694363 ALTM_TRANSLATOR CAPTURE Capture is unable to translate third-party designs
3 d& D# I0 d3 Q4 j* Q$ S1539739 ALTM_TRANSLATOR CORE Capture crashes on importing a third-party project
" v: h! y' o x, }2 e1542860 ALTM_TRANSLATOR CORE Capture crashes on clicking Translate after selecting a third-party design6 Y+ j; R9 I' n
1551642 ALTM_TRANSLATOR CORE Unable to import third-party schematics into Capture
$ H" P3 w4 ? C1572929 ALTM_TRANSLATOR CORE Footprint names getting altered during translation
( O Q0 h0 U/ y R1568436 ALTM_TRANSLATOR PCB_EDITOR Unable to translate third-party layout data into PCB Editor
9 ?' i1 O' G' j6 l9 m8 Z4 f1629256 ALTM_TRANSLATOR PCB_EDITOR Getting empty symbol and devices folders when importing into PCB Editor
2 E6 s# _- }2 S3 T4 L+ x& Z# c! d1664120 ALTM_TRANSLATOR PCB_EDITOR Import from third-party to PCB Editor is not translating data correctly- ]0 t- V7 l2 u* l9 k. \
1701537 ALTM_TRANSLATOR PCB_EDITOR Import does not complete and reports errors
0 x1 B! q* a( G6 ?# `1698706 APD DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin
' O) c+ G6 }0 ]1714528 APD DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry8 L7 j' |" G- u6 q' [
1714532 APD DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes, r7 z; _2 U+ n; C" ~
1734310 APD MULTI_USER Symphony server mode malfunctions when die layer present.0 m6 b1 t6 C3 {5 G& x/ N0 J/ ?
1725506 APD SHAPE In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short4 b$ l- j4 _, [3 ]% g! f
1724395 APD WIREBOND Running axlBondWireDelete returns error message6 s! v1 H e- [; }% P) l
1726609 ASDA CANVAS_EDIT Paste should not be allowed in the Current Refdes column of the Change Refdes form& z) b v; I y! i4 G
1719754 CONCEPT_HDL ARCHIVER Path stored in the compressed file starts from /home instead of the current working directory
0 X: x2 Y" H* C/ \1 b! N1726570 CONCEPT_HDL CHECKPLUS Checkplus crashes on Windows 10
: P0 G( x! x0 |) k. C; S1697977 CONCEPT_HDL CONSTRAINT_MG Differential pair disappears when it is packaged
2 L! K& B! O/ C2 X& t5 J. Z1679575 CONCEPT_HDL CORE Page numbers are duplicated in Hierarchy Viewer when editing page names
* M. Q3 {) | H; u$ a1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
: ^( O1 x# @+ w2 M- w/ @( c* N1711564 CONCEPT_HDL CREFER CRefer crashes while processing a hierarchical design containing subdesigns& I6 Q; J. q9 g! ?2 V6 I
1730736 CONCEPT_HDL OTHER Crash on generating BOM from design
& q! \- l- d/ S: f1608350 CONSTRAINT_MGR CONCEPT_HDL Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer1 D! a, o8 o {1 l
1715803 CONSTRAINT_MGR CONCEPT_HDL Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer
) U$ H1 t: L; J) d# P' |& j1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
* }) d# ]1 x! m# \0 ?* I+ F1720886 CONSTRAINT_MGR CONCEPT_HDL SigXplorer does not extract assigned model from the schematic
; l( o3 C- P. J% \. k% U1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
% b( X: s0 ]: i8 V" d5 u1722306 GRE CORE Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs
0 a: h$ z5 X2 w& |1710049 PSPICE SIMULATOR Functions are not taking parameters in correct order
& Y0 ?0 o2 {8 X! j6 L, |1693021 SIG_INTEGRITY OTHER PINUSE is not updated correctly at model assignment with specific steps
6 I Q9 k% y7 Z E( H0 j1730854 SIP_LAYOUT SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode
1 `7 }2 D. [3 H" @4 z! F1 I( x2 o8 _( b$ {
4 c7 ?5 c' W* C5 G2 e
Fixed CCRs: SPB 17.2 HF017# |* C. ^. E' { ?
04-13-2017: s; Q5 n4 `" h( M0 v1 ^
========================================================================================================================================================! O9 u4 ]) U' ^, B+ `2 \
CCRID Product ProductLevel2 Title/ x" j2 N; s" A- P' y5 s
========================================================================================================================================================
1 B% `5 h! K2 I1732877 ALLEGRO_EDITOR SKILL The 'axlXSectionGet' function fails in release 17.2 Hotfix 016
9 k- J+ z5 _3 m. D8 C( [5 m; N4 o; a& ?
$ {8 L9 n6 W Q2 t {& I
Fixed CCRs: SPB 17.2 HF016
& ?: |7 \# u' J; W04-6-2017
$ x+ p$ x7 k& `" K========================================================================================================================================================
9 O* O! Z# s& `! b9 K4 Y ~2 bCCRID Product ProductLevel2 Title; m5 p0 G% g; `; a
========================================================================================================================================================1 e' V0 z0 `1 t4 U3 Z' i! j( R$ l
1673128 ADW COMPONENT_BRO Directive is saved in project CPM
# S4 v3 z, {& b4 M; @2 N8 _; u+ ~1673510 ADW COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results
% J2 I3 v6 R; R: [1604734 ADW DATABASE Parts displaying non-key properties and values in the Component Browser in ADW
i) O3 h. B7 m5 k5 R1142957 ADW DSN_FLOW No Help available for schematic design verification
" _- s1 Q9 m" S9 K( J1609186 ADW DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini
# B0 u, }. W; L+ ~3 H% L8 O U1591757 ADW GENERIC_UI Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736
0 a) _. A) }+ |$ e6 w ^$ c- F+ ]1588111 ADW LIBIMPORT Library Import fails with Java errors while processing .csv files h7 A0 [, d% B! z
1642367 ALLEGRO_EDITOR 3D_CANVAS Component height is not correct in new 3D Viewer! q1 K/ w, C0 s. ]7 O3 |. d
1642668 ALLEGRO_EDITOR 3D_CANVAS The new 3D canvas does not show STEP model of the drawing (.dra)( h! Z4 M. `& m+ A6 W; U
1653247 ALLEGRO_EDITOR 3D_CANVAS New interactive 3D Viewer shows wrong placement9 q" e1 j/ L0 K! ^
1658275 ALLEGRO_EDITOR 3D_CANVAS Components on the bottom side are shifted in the new 3D view, ?- V6 i$ s$ S" T
1639244 ALLEGRO_EDITOR ARTWORK When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable# b( P. [9 C& s% J' L6 _
1658173 ALLEGRO_EDITOR ARTWORK ARTWORK: Value of Scale factor for output." p- d/ _' d6 T# N' R/ w5 f
1661760 ALLEGRO_EDITOR ARTWORK Import artwork to Design Outline layer does not give error in Allegro prompt.! O9 X( S* K0 o6 P
1667778 ALLEGRO_EDITOR COLOR Add option to set FORM mini dehl_retain_color to NO
1 V7 j9 a) U! [3 N4 \1669462 ALLEGRO_EDITOR COLOR Changes made to the Visibility tab are not reflected in the Color Dialog window9 `8 H3 X; ^3 y$ `: E
1641265 ALLEGRO_EDITOR CROSS_SECTION The differential impedance value for a layer is not getting updated* d% e' i& |+ u& C* _6 h
1648149 ALLEGRO_EDITOR CROSS_SECTION Getting warning when calculating impedance in mixed stackup
! ?! J% l4 Z3 n1 ]1671441 ALLEGRO_EDITOR CROSS_SECTION Enhancement request for cross section dialog box
, E1 M/ P, m% L1673320 ALLEGRO_EDITOR CROSS_SECTION Diff impedance calculation fails
! k* @& }! G) w4 V5 d. w3 b1690021 ALLEGRO_EDITOR CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection
( l0 M" H" O' {, C! p9 V1703831 ALLEGRO_EDITOR CROSS_SECTION Calculation of Diff Z0 fails in flex designs
6 ?+ o3 M" E3 ~. s0 v" t1711484 ALLEGRO_EDITOR CROSS_SECTION ShowAll Column does not retain its status
% i( `5 W) V/ _1672841 ALLEGRO_EDITOR DATABASE ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch
+ Y r! ]7 y; x4 P1673613 ALLEGRO_EDITOR DATABASE COVERLAY_TOP not present in the Non-conductor section of Color Dialog window0 |" c# A5 g- S+ u) e" X1 a% w& T( y
1688123 ALLEGRO_EDITOR DATABASE Drill Plating Issue0 B1 h3 t- H, ?6 z
1701995 ALLEGRO_EDITOR DATABASE When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE
( m' Z1 a# a! _9 e7 ~; }1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
" Q. v, i; h" R3 P' \1713335 ALLEGRO_EDITOR DATABASE Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error
' X% W% c+ N+ E }9 w( a3 T0 p1693289 ALLEGRO_EDITOR DFA File - Save As script does not save the DFA file1 ^+ q! H6 v- A8 y- u6 z/ m
1644004 ALLEGRO_EDITOR DRC_CONSTR Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin" \1 K* r. o# z ^3 m( J4 j
1651425 ALLEGRO_EDITOR DRC_CONSTR The .brd file crashes when moving text controlled with minimum metal to metal constraints7 p' E1 r3 \6 g* S9 L
1663494 ALLEGRO_EDITOR DRC_CONSTR Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs
( O: ]8 j0 M- |' U: y1687049 ALLEGRO_EDITOR EDIT_ETCH Create a Via Structure disconnects nets
, q/ O0 J+ [, V0 s' I1704296 ALLEGRO_EDITOR EDIT_ETCH Asymmetrical fanout created for BGA Quadrant style
" d# [& @' T" s5 f3 P/ Q: \( ~1686873 ALLEGRO_EDITOR EDIT_SHAPE Merge static shapes deletes both the shapes selected.
# b; E' }. g. a1629925 ALLEGRO_EDITOR GRAPHICS Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.04# i. S2 P1 X9 S& ~/ U
1628895 ALLEGRO_EDITOR INTERACTIV Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property; x2 n7 f. _+ D2 O/ S
1666379 ALLEGRO_EDITOR INTERACTIV Place replicate is not working on the attached test case
1 }5 C: G6 w4 y; g7 l1668282 ALLEGRO_EDITOR INTERACTIV Grid display incorrect for repeated grids
* Z" y0 K9 |" G, W0 D) R1675531 ALLEGRO_EDITOR INTERACTIV Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working% A; M7 e$ U: N' ^2 e# v
1694470 ALLEGRO_EDITOR INTERACTIV Update description of variable padstack_nowarning_display# X! U+ f# J6 y! H' T- T# f$ I
1696855 ALLEGRO_EDITOR INTERACTIV Mixed grid setting is not displayed correctly on Define Grid screen.
8 n7 B8 x" K6 s/ c9 z1698192 ALLEGRO_EDITOR INTERACTIV Deleting and replacing a component causing database corruption in Hotfix 009# ?+ n2 M2 q) H: |1 I& j; t
1703671 ALLEGRO_EDITOR INTERACTIV An error occurs when defining grids with zero increment value
5 f; U" Z% K, W# R& D. r" p" |1703812 ALLEGRO_EDITOR INTERACTIV Crash during move when using the 'snap pick to' option set to symbol origin
% f$ i- l# s$ u- g5 d* R# U1719276 ALLEGRO_EDITOR INTERACTIV Setting variable grid for 'All Etch' displays an error in the Define Grid form
( J* z \& G: I# {8 R1663422 ALLEGRO_EDITOR INTERFACES Shape loses group membership after importing through sub-drawing
* `) e- w0 P5 b3 f. v, J1637959 ALLEGRO_EDITOR MANUFACT Thieving uses different clearance values around the route keepin.
) r$ u7 g# k: V/ S; A' V1716431 ALLEGRO_EDITOR MANUFACT Test points generation stops due to an error
g( q5 n! C6 g7 n) }/ B. ?1641994 ALLEGRO_EDITOR OTHER DB Doctor: Incorrect spelling of 'eliminated' in the log file messages- ~& |- G( U+ O: {
1660496 ALLEGRO_EDITOR OTHER SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity7 N2 d3 g0 i; a" x. g( p, ?" F, T
1685464 ALLEGRO_EDITOR OTHER The 'alias ~S save' command is not recognized when set in the local env file% }/ W# @. T" W
1696486 ALLEGRO_EDITOR OTHER STEP export results vary between releases 16.6 and 17.2
; p, K' I) ]6 Q. q* `) O1706623 ALLEGRO_EDITOR OTHER axlBackdrillGet crashes for invalid argument' O1 Z& F! C4 d; _4 F" e$ q5 _7 k
1586957 ALLEGRO_EDITOR PAD_EDITOR In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab
, m5 T6 C" r' r' C. N+ d5 Y% Q1610984 ALLEGRO_EDITOR PAD_EDITOR Geometry set in tabs not read, only initial value set in Start page is used
2 y0 ^" ~4 r4 @2 |! n0 B B3 N/ h" ?, h1614015 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor in release 17.2 does not auto fill geometry in design layers, D. O3 D- l, s8 s7 {
1636012 ALLEGRO_EDITOR PAD_EDITOR Keepout should not be allowed if antipad is not defined for outer layers
( A4 W6 C) _" d) Z+ m: |1641973 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch
9 J: k2 F+ o9 J, d7 a) `; e' a- v1642789 ALLEGRO_EDITOR PAD_EDITOR In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file" p# ^7 J4 x6 j
1646914 ALLEGRO_EDITOR PAD_EDITOR The 'Save' button is grayed out in Padstack Editor
6 G* p& c! C4 h) X6 D) @# Y7 t1657553 ALLEGRO_EDITOR PAD_EDITOR No possibility to specify Padstack Editor default library path at invocation5 ]. @9 X. N. j
1657609 ALLEGRO_EDITOR PAD_EDITOR Changing Tolerance field in Padstack Editor does not activate the Save button
9 M o) K, j/ T( ~1662225 ALLEGRO_EDITOR PAD_EDITOR Padstack editor dialog message doesn't match available options/ Q' f! s$ b/ @* t j# U
1667062 ALLEGRO_EDITOR PAD_EDITOR Padstack editor does not retain the decimal places from the previous session
& @+ @0 i3 O" }% r1672774 ALLEGRO_EDITOR PAD_EDITOR Pad Editor graphics appear to show offset incorrectly9 k% J5 u: o/ s0 a
1674157 ALLEGRO_EDITOR PAD_EDITOR Update Symbols does not update Pad Type Information
" ~ e2 Y% L# X. t1675438 ALLEGRO_EDITOR PAD_EDITOR Drill hole size warning for the SMD pad! b* w% B- L' |% A6 X! d
1684376 ALLEGRO_EDITOR PAD_EDITOR Pad Editor issues with settings, such as decimal places, layers, and so on
9 b$ e( O6 n6 c3 _% E& L1690376 ALLEGRO_EDITOR PAD_EDITOR Variable padstack_nowarning_display fails to suppress warnings
2 \5 Y" s5 k9 y/ h8 Y- X9 u0 c( q1694649 ALLEGRO_EDITOR PAD_EDITOR Change Cancel button to No in warning generated when updating padstacks in design layout
k' B) \+ N. R+ m9 L, V: u8 r939242 ALLEGRO_EDITOR PLACEMENT Cross probing between Capture and PCB Editor is inconsistent5 T" c% t8 L$ ~% R+ l
1103945 ALLEGRO_EDITOR PLACEMENT Place Replicate Create does not include the etch connected to pin( f3 k* A, l* O$ z, {( ~$ k6 Y
1233019 ALLEGRO_EDITOR PLACEMENT Allow cross probe object selection apart from highlighting during place replicate
: A% Y0 W& [. [8 ]1643078 ALLEGRO_EDITOR PLACEMENT PCB Editor flags an error message when a module is placed at a specific angle7 b; O1 w1 ^* K5 F9 b! t1 v4 \
1696932 ALLEGRO_EDITOR PLACEMENT Inconsistency with Snap pick to when selecting Segment Midpoint% ]$ d. |6 U$ F, O9 @# I5 c
1654500 ALLEGRO_EDITOR REPORTS In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set
1 B5 c( w4 t7 b! j; Z1643992 ALLEGRO_EDITOR SCHEM_FTB Export Physical fails with the 'netrev.exe has stopped working' error: o2 Z% ]3 z6 y T1 f
1653400 ALLEGRO_EDITOR SHAPE Dynamic shape does not void a via.
. M, ^: o1 ?: W# E# [1 Y1668262 ALLEGRO_EDITOR SHAPE dynamic shape does not void custom route keepout with arc
3 F/ J* V! {6 E) g, r+ @, s1682569 ALLEGRO_EDITOR SHAPE Variable 'dv_squarecorners' not working correctly.
5 v% [. Y3 h$ q' `# x1696240 ALLEGRO_EDITOR SHAPE SKILL error when merging polygons0 p4 k/ `& X7 k* _
1709968 ALLEGRO_EDITOR SHAPE In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape
( B% D/ w1 E% L2 ~# w2 k: h1632505 ALLEGRO_EDITOR SKILL In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save) U; p4 R4 t1 h: _' L4 _# H6 Q
1651701 ALLEGRO_EDITOR SKILL Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command6 ^/ k0 Y# \8 K5 O6 A
1658419 ALLEGRO_EDITOR SKILL PCB Editor crashes after running SRM4 C7 m- c: G% |" {* L
1658948 ALLEGRO_EDITOR SKILL axlIsLayerNegative() is not working in release 17.2
8 Q9 S, Y3 g/ i( W+ v1670956 ALLEGRO_EDITOR SKILL axlIsLayerNegative() always returns nil( d" h$ e& |. e2 W. s4 t
1687239 ALLEGRO_EDITOR SKILL Problem with SKILL function axlCNSGetPhysical - incorrect parse string* f7 b5 P l P/ T; U
1692345 ALLEGRO_EDITOR SKILL The axlGetParm documentation example for deleting an artwork record is incorrect.
8 p) u4 r9 c# C& I2 V/ r1707878 ALLEGRO_EDITOR SKILL Object rat_t does not work with axlDBPinPairLength.
/ C' G9 T7 q3 r) Q4 Z1598061 ALLEGRO_EDITOR UI_GENERAL Adjust menus to allow side by side view4 B$ P! W- S8 d% a' y1 R5 O' v
1599901 ALLEGRO_EDITOR UI_GENERAL Color Dialog box is not updating according to visibility tab.
6 u: V0 ~: S1 A6 S9 o1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2
2 _8 M5 ^0 O# ]1 {: n6 J( z1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands
/ k" I; Z' p/ g B$ ?1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response- ~6 ]# ^# J. c6 q' R( O8 t
1614763 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor
' a$ R, e& y* `$ T1 u1 `6 l1619873 ALLEGRO_EDITOR UI_GENERAL Command Window scrollbar does not reach its end- c/ `$ F' H$ a
1624617 ALLEGRO_EDITOR UI_GENERAL Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"7 M' ^+ s) E" Q; i1 o `
1631646 ALLEGRO_EDITOR UI_GENERAL Visibility pane not retaining the correct layer view( ]* }$ O* f% e4 t. {$ r
1637062 ALLEGRO_EDITOR UI_GENERAL The last line of the floating command window in release 17.2 is hidden behind the command window frame
4 }2 D5 s0 l" b5 f" |5 ]: m1642645 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor
: Y- {8 a# c0 f& p: b6 r- Y1645335 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed! Q1 J7 r& a5 _( w4 y% j9 l
1647520 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes after installing release 17.2 Hotfix 005
2 z8 R1 l" B8 O8 S1647541 ALLEGRO_EDITOR UI_GENERAL Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch9 N! J: W% k- Z& L3 s. ?
1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2
, K ^/ n* Q& y1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key% Z8 J' W5 j$ O
1652423 ALLEGRO_EDITOR UI_GENERAL Using the F1 key does not display the help document
& }1 u j1 b* } [! }1654600 ALLEGRO_EDITOR UI_GENERAL Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"5 w( x3 i5 Y- _1 v1 U& ?
1654777 ALLEGRO_EDITOR UI_GENERAL Reports UI does not work properly when writing a report file.
- A" H) `) K S& W1655500 ALLEGRO_EDITOR UI_GENERAL Visibility selection ignored after color change+ f5 ]. W# ^' L X9 j! M! o( J' z5 u
1655514 ALLEGRO_EDITOR UI_GENERAL Artwork Film is available in the View section only after you restart PCB Editor
: ]& R1 `- ^# |0 C8 A" ^1663819 ALLEGRO_EDITOR UI_GENERAL In release 17.2, SKILL function, axlOpenDesign(), does not work as expected7 b/ H+ T' ?. t
1671334 ALLEGRO_EDITOR UI_GENERAL Design outline is not shown in 'World View' window% M3 b: s# k; `
1672148 ALLEGRO_EDITOR UI_GENERAL Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release) \* w( B' I: `) `) Y; ^; I2 b
1679418 ALLEGRO_EDITOR UI_GENERAL On choosing Edit - Move, the 'Symbol pin #' box is obfuscated
) M) c, f. L2 [* i# r1679761 ALLEGRO_EDITOR UI_GENERAL Choosing Edit - Spin hides 'Symbol pin #' partially
9 N. l! v$ Q- }" r1 e8 x0 q1686887 ALLEGRO_EDITOR UI_GENERAL Hyper Text no longer selects coordinates for easy copy
0 l9 |- k: i5 t) O1687286 ALLEGRO_EDITOR UI_GENERAL In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner/ l" ]/ O1 w* X6 E$ X
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2% @8 E9 K7 `. {5 I
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports
2 C: u1 U9 @8 Y- F. I* p6 z1702420 ALLEGRO_EDITOR UI_GENERAL Unable to maximize reports viewer in 17.2
, k- W, D3 f8 o) }) `# v% U1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected. w" s4 W, Z; o$ }# u5 W0 y8 H
1703107 ALLEGRO_EDITOR UI_GENERAL Scripting using regional settings for decimal separator
1 e6 |/ j% n b5 Y: F1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor- o& r$ F- [: J- K* ^9 M
1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
5 L7 ?( P. j" v* v- z& c. g8 m1639896 ALLEGRO_PROD_TOOLB CORE MFG collector does not move files to subdirectories* \1 c- Q0 g* [5 b# S7 ?
1608804 ALTM_TRANSLATOR DE_HDL Translation issues in symbols with multiple physical pins mapping to a single logical function4 x0 w; g4 Y( c0 j8 o
1658525 ALTM_TRANSLATOR DE_HDL Invalid characters in pin names
5 i( T5 Q/ J; M: _1658536 ALTM_TRANSLATOR DE_HDL All cell names should be generated in lowercase letters
9 F- J6 T; A7 q! Q* }' [- r. Y1609962 ALTM_TRANSLATOR PCB_EDITOR Errors reported during design translation
9 H/ ?3 H- c& F# k, j1661562 APD DRC_CONSTRAIN The wrong space calculation on finger to trace
' R3 m* Y3 E6 T2 r# h7 g6 m1682398 APD SHAPE Deleting islands causes out of date shapes: I- Q5 g+ T2 U# t. W
1638112 ASDA CANVAS_EDIT Unable to rename multiple selected buses using the 'Assign Name' command
: @! m, Y; r" q& O1645571 ASDA CANVAS_EDIT Various routing inconsistencies with synonym bodies on the canvas
+ l- `0 X1 q) y2 `! ?1656336 ASDA CANVAS_EDIT Presence of illegal characters in the net name removes the entire net name
# W* K! E3 U$ G1667176 ASDA CANVAS_EDIT Unable to add the port symbol in a specific scenario9 K: c' S; c& H- X
1641473 ASDA CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive
( H! S4 c: f. V: N1661350 ASDA CONSTRAINT_MA Unable to create physical & spacing class from the docked CM: o v6 F; L$ C8 r
1645557 ASDA IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets
0 r' g! j8 s M$ m8 E$ h+ e4 l, E) B1652753 ASDA MISCELLANEOUS Tcl command window should display correct casing for autocompleted command
: l, ]% F$ a" p! T, e: e1654973 ASDA MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list
& ]/ x3 X* F- F# Z, S# I" x1652718 ASDA PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted0 Q2 w, _2 x! w& T
1699454 ASDA TABLE In the table object, cursor skips a cell on the first use of the TAB key) {3 R+ w( E4 X% L! @6 H# a2 S: ?0 ~
1702702 ASDA TABLE Copy-pasting table objects to a new page fills the headers and rows in black+ x; y# J: a2 D7 ?9 V$ z% k
1668877 CAPTURE ANNOTATE Using Ctrl+drag does not preserve the reference designator value
8 z* C. d8 e3 d' I. B0 l1665454 CAPTURE NETGROUPS Incremental copy for alias does not work anymore.& Q% Q. k" ~& q3 S3 Y6 k, P
1634598 CAPTURE OTHER The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option1 s0 r0 Z& w1 r: W+ L/ D
1636090 CAPTURE OTHER Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files9 |% F+ o9 D9 j8 E- z
1650029 CAPTURE OTHER Crash while archiving a newly created PSpice project without adding simulation profile, W/ D' n" q6 u( h4 ~% \
1659602 CAPTURE OTHER Saving CIS BOM via TCL command window
$ N( Z3 N0 V) i0 ~1678715 CAPTURE OTHER Capture.ini [WebResourcesMenu] is not working in release 17.2
2 W: b" ], g$ v4 Q1 V7 Z% v1619449 CAPTURE PROJECT_MANAG Search not working in a PSpice project
5 y( f( I0 x5 j( S* e1670133 CAPTURE PROJECT_MANAG Start Page showing wrong Software Version
$ M* s8 @, {" |- S7 }/ A5 B1670766 CAPTURE PROJECT_MANAG autoreference does not work properly7 `7 p* @0 J$ {0 _7 {5 m0 N
1676095 CAPTURE PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed1 }4 Z' |, Z9 n# ?* s& e
1658315 CAPTURE TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture
T S! J' ^8 D1 U' i+ X, \7 m1642601 CIS OTHER Design Entry CIS: SQL server password is required each time the tool is launched
% _3 y7 n4 Q I' k1712279 CONCEPT_HDL CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016. y$ d9 O6 E* Y: Z
1665449 CONCEPT_HDL COPY_PROJECT Copy project fails with error COPYPROJ-77. A" `+ Q2 k0 P' G" ~3 D* c% q
1661778 CONCEPT_HDL CORE Advanced Find will not find pins with the SIG_NAME property attached
& R& y' {1 ^2 B. E1666084 CONCEPT_HDL CORE All user-defined properties are not listed in the Customize columns in Variant Editor
9 E5 @6 |5 {/ L& f& i( B' P1667043 CONCEPT_HDL CORE Incorrect information in cpm.log file
2 N9 R2 G6 f8 G" `1670659 CONCEPT_HDL CORE SIGNAME text off grid when pasting copy using ctrl+v.
; j( p- l6 b o7 C* w$ U1697732 CONCEPT_HDL CORE Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla; G* V1 V8 i# s, K w
1697955 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net7 a0 {. t6 W/ n# y0 ?7 G' D
1711635 CONCEPT_HDL CORE The arrow keys do not work as expected in Windows mode
7 x: G3 c4 S$ W- |0 v1713091 CONCEPT_HDL CORE Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.2: j# q4 r& O5 j: @$ z
1708820 CONCEPT_HDL OTHER In a board cache flow, component bodies are missing when importing another board cached flow project.$ O% L( y0 i$ a# ~
1639928 CONSTRAINT_MGR CONCEPT_HDL The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation
* q- u0 E* s9 `1657048 CONSTRAINT_MGR CONCEPT_HDL Unable to navigate through the search results in the CM Reports
" A% V) W9 Y- n1 S1 A1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
) e8 ~/ z. y4 Q: {* U8 Y- f8 w! P1717336 CONSTRAINT_MGR DATABASE Netclass members change during logic import; it's a toggle switch5 g. B7 S C7 {8 I% t" F
1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas2 n5 V* F2 f1 \3 E
1682885 CONSTRAINT_MGR INTERACTIV Constraint Manager worksheet switching does not work correctly in Linux* i% _% w- q' {: b6 n# }5 @- r
1669523 CONSTRAINT_MGR OTHER Select is disabled in Constraint Manager when a command is active in PCB Editor
0 D) i2 K& r. r4 Z- v$ t+ G3 q- s1670802 CONSTRAINT_MGR OTHER Selecting a list of nets using the shift key does not work in Spacing and Physical domain
) N, N' ~1 v5 f7 ?, B9 g1670922 CONSTRAINT_MGR OTHER Title of the Layer Remove window is Constraint Manager
- ^& F) |4 i1 c) h/ \0 e3 B1678235 CONSTRAINT_MGR OTHER Select option grayed out in Constraint Manager if a command is active in PCB Editor
+ z% E$ q; l. R1 U; s" p1680917 CONSTRAINT_MGR OTHER In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active/ l# k4 i7 K6 Y% A( P$ K$ I
1691125 CONSTRAINT_MGR OTHER Highlight command no longer selects the net in CM
3 @& c! t% X+ i% X1703791 CONSTRAINT_MGR OTHER Cross highlighting and assigning color to nets between PCB Editor and CM does not work
; n7 n" _5 F& i7 j1649603 CONSTRAINT_MGR UI_FORMS Expand and Collapse commands do not work when multiple objects are selected
* e) u% [$ ]5 K; S( K$ w$ c8 W1654931 CONSTRAINT_MGR UI_FORMS Expand, collapse only works on one of the multiple selected objects.. L7 f0 _# `3 b9 H: \+ g+ W, m
1668794 CONSTRAINT_MGR UI_FORMS Incorrect via name shown when filtering via list
, z+ S$ @4 B5 ~! w/ U% n0 y1678305 CONSTRAINT_MGR UI_FORMS Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area
1 W" d" r0 f. \: j2 K* Z) l1679909 CONSTRAINT_MGR UI_FORMS Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet
& K4 K1 e+ m q( ]4 ]1691906 CONSTRAINT_MGR UI_FORMS Display Issue: When you use the filters, the horizontal scroll bars are duplicated
: A! \0 z* m$ u6 h; X v, D0 g1 l1677893 ECW INTEGRATION Integrations list update is not working as per scheduled time
9 a# o: v! C8 a/ P1652707 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
) `7 _9 ]# i" V( p. Y% a( F1654512 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart! _9 k2 c4 }- K. n
1668953 ECW METRICS IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart, ?2 B/ v4 |1 `) M1 {8 a
1677443 ECW METRICS Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project
# F( c1 I$ `3 G6 F$ ~1 R1663676 F2B PACKAGERXL Physical net name (PNN) errors in the log file, X0 N% P5 m" {7 h- {
1669583 GRE DETAIL AiDT always fails push when there is a connect shape attached to the cline being tuned3 V" a% S* ~' C1 g8 }" r
1686350 INSTALLATION SPB InstallDiagnose fails to repair some errors. a K- K- L, X% a. p
1672369 PCB_LIBRARIAN EXPLORER Cannot create a New library build in Library Explorer./ O! f. h: U/ Z1 w
1631034 PSPICE ENVIRONMENT When simulating the design in release 17.2, Capture crashes but works with release 16.6
! N- G2 h& r( V1648284 PSPICE ENVIRONMENT PSpice project crashes when a design is opened in release 17.2& c. W5 j" V3 }' w# U) ~. P) n
1663336 PSPICE MODELEDITOR Ibis translation not supporting paths with spaces, U9 _7 \4 J D/ E+ o r$ P
1679376 SIG_EXPLORER OTHER Topology created in OrCAD PCB SI license cannot be reopened with the same license* D% [1 ?% K: ?* ~! m
1666484 SIP_LAYOUT CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.8 M) u7 y8 R$ `) l& {
1687988 SIP_LAYOUT DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name
) h' V# d/ {! _1715016 SIP_LAYOUT DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up
{" n3 w* U, [6 L* A! x1620601 SIP_LAYOUT MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database8 {5 |% _% Q1 q; g# M- ]' g
1705963 SIP_LAYOUT PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save
; Q" v3 \: {) N: N1713767 SIP_LAYOUT REPORTS Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6 E( O. ^" F% | ]) F
1696218 SIP_LAYOUT SKILL SiP Layout crashes on reassigning nets
+ I7 q/ F6 H& t+ X; C1695885 SIP_LAYOUT UI_GENERAL Visibility Tab check box: unchecked "All" disables access to "Shp" check box
- J. p4 c/ A& r" k3 d1639838 SIP_RF DIEEXPORT Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export
. P' r# }( y9 S6 Z# l1653894 SIP_RF DIEEXPORT Redundant error message for die export, when view name is other than "layout"
+ ^1 T. H/ H4 @* m$ R1681332 SIP_RF OTHER Running die export causes Virtuoso to crash6 m% I* \: k& o) [' N; a% }" h
1679336 SPECCTRA LICENSING Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional
8 h; V, i: W, Z) B% a" r% _) w) ?& j. U' X' k1 ^% @, Q H
5 q9 p' B3 D# p5 Z! V/ PFixed CCRs: SPB 17.2 HF015
& Y, y5 q5 b6 N( Z03-16-2017
5 m" a& j$ b) v1 _ Z9 R========================================================================================================================================================
+ X; X v* \) X1 P- ACCRID Product ProductLevel2 Title
; Z! h( q. ?1 s========================================================================================================================================================
% \! _! k& d4 D' ]6 x& x1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
% A) N+ y: K: L* @* [1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
6 ~# l0 l* ~: S5 E. d" _1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
: k# i+ I5 g' T: c! U* i1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
6 X& _& f r) ~% A* b$ U/ R( Q1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms8 _( A5 n$ E% I& b _
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design) q% ?# i: U( h' d
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
" l6 p& d4 t- q% O1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.# g) a/ X4 H! N: U
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
, J! p, G* a! M' d1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor& f/ m. l" x3 c8 s
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not) a- F# X# p# P$ r, h
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
$ p, @; Q- Q- b3 x% C( _8 l1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places& b/ g1 }; `" ~2 X& Z
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
) z, b$ ?/ W1 a2 |2 C* V1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically: J1 C& c: M$ I) ?. T
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
# N) @. `( g- N1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
& ]8 A! C2 X: [2 q) G+ j& |1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file6 M( z$ s* y! u K, R6 _
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 0848 P( C; j1 ~5 e+ y1 Q
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
" H8 b8 w; q& [9 {2 B# e m1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net4 z, \+ L6 ^9 Z5 }
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
z7 @; A% c. y1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
% z1 S7 q0 }3 i) e% N1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
+ j9 I% p% L# S7 q- w1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode0 ^, L" l, I- x8 r' {% \! i
' b8 v G3 O7 t. x: O$ g3 |
& D5 R* P( \8 \, L+ p
Fixed CCRs: SPB 17.2 HF014. G9 A4 m9 {6 \7 } Q
03-4-2017
4 t& d: J% K8 s: @% b* I9 W========================================================================================================================================================' \/ f4 t t) a3 e
CCRID Product ProductLevel2 Title
8 W+ { v3 F3 U. ~6 p========================================================================================================================================================
8 v) f( y: Y5 E ?4 v) \/ N1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships! m* S) U8 x! W0 F0 F' n
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity9 J# Y+ Z/ l5 z# s
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
5 V' M7 i& Q% B! }+ h) r1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data# w+ T! @7 l. L4 q2 U
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
# c, M) O- ^) w3 ]# J8 y1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
0 ^$ p8 ^, c9 X: d1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
+ {7 H W$ T- q6 r, `4 U1 X4 \) Z! @1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted1 o& n& f1 q! i1 I! \3 `
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location0 j5 X1 u. j$ _
1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam) U$ I6 i' f3 }, K: s }
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
2 M6 D+ m3 w1 i% e+ R1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.64 q* d1 A$ s1 B' K% g
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one/ W; T/ S. n5 _! f* ~* a7 V
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled/ j" @0 Y; W& j3 q& v& d
1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
' N4 g7 H6 @( m& k1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components% Y# C$ t4 y$ t0 J; e
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers( I$ W5 x! Z T" t) g0 s
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
3 c5 P6 i, h# g# y1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement7 ^ O L3 I. E% E$ b7 n
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
& m% C i1 W5 g( g% q' u1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
! J& H# N- G: A1 R+ M; V/ m$ Z: q1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2. j& n9 i8 P/ w: |# w1 _3 ]
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
0 V: b; D, u' ~1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
: {/ P/ h6 X2 n$ x9 \' F% g6 l1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design+ U* B0 [& n8 r: M3 A3 \$ P1 d
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors- E& w. [& z3 k9 z( T' u$ U
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters* G5 U# l, Q( E- }: X+ K
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP' H' w) ?7 u" F) [- c8 t8 ]* d3 B% ^
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'2 c! j& |% R0 ]2 [" D
1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
5 G( y v, S: I2 x3 p1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
5 {: j; W1 I2 x! @& m7 H: u3 x* L0 C) W% X- j9 ~; K9 }' t
. l7 B3 U0 M/ @9 }$ F
Fixed CCRs: SPB 17.2 HF013
' q1 T+ j- S. q/ Y9 H02-17-20177 C0 m% h0 T, x2 W L) r
========================================================================================================================================================5 k3 ]; ` T5 v. ]1 l% L, F
CCRID Product ProductLevel2 Title5 S) x; N( a7 w: y6 @' F1 a
========================================================================================================================================================
! |( \1 n/ I5 P1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm) o7 E" i. \4 f
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer" B+ ~( ~5 V$ _: D( Z) {
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
5 V, t; ^( i* D2 ]' X$ |) C9 l, p3 k `1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated+ S: q7 z9 z$ A- E, N! z8 _
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated8 I m( w' X5 b+ L3 f
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
0 N4 J: S& r( W* j* ~! ~1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor3 J$ ^4 u) `0 M+ ?
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
$ h4 l$ Y) J, ]$ K- M2 |+ A; n1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not. X( @5 `0 B! j: t" i/ q* P
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
/ {0 y6 o* V7 P! \0 |- Y* r1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components" v- a$ [3 G7 b) h# | L0 I
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
) ^7 [ N, | J! r8 d5 O- s1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
9 q2 f; o0 \5 r7 I$ i1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF- U! ^8 F U% e( `1 U" f5 B; }
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement& o3 p7 G; Y7 F# ~) J6 P7 s# e
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
# U; }# g9 | G! o- c1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file
& h1 H/ u9 o# r6 R1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.! r) p% n3 a8 T3 Q7 F/ l T
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker2 L7 n, R$ W! Z2 \& ~! B$ D
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates, z$ K7 c5 f% Z. g, Q; O& c
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes( y$ k, o/ V$ k0 }. B: Y& k6 U* ]
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.6 d. K! ^5 k g8 L! k' e5 e
, U7 V+ r9 E c8 Z
0 B q9 U( S1 W: B3 @7 |
Fixed CCRs: SPB 17.2 HF012; S$ m3 z$ N; u# C* `
02-3-2017/ f: H" n. {: Q# s% b/ e/ O
===================================================================================================================================; V5 V3 m) C' Q& _
CCRID PRODUCT PRODUCTLEVEL2 TITLE; i, P1 n2 g7 ^ `1 I5 a
===================================================================================================================================4 I# L3 c% k3 F* _! K2 c
1659641 ADW FLOW_MGR Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager3 E6 c3 }9 S5 d9 i4 T9 ?
1661632 CONCEPT_HDL OTHER Page skipped in DE-HDL when navigating using the Page Up and Page Down keys8 B$ L" t( d+ Y
1668325 ALLEGRO_EDITOR SHAPE Updating shapes to smooth creates erratic voids.
' z5 k" P" k7 r6 }1670082 CONSTRAINT_MGR ANALYSIS Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.2
4 ^' y# N3 L V$ h1674231 ECW METRICS Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots- D, t) ~2 I. f2 R0 b0 l
1674338 APD SHAPE Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'
- k. U7 p9 l/ k0 F6 g" j7 G# D* }& R1675677 ADW DBEDITOR DBeditor Issue-Searching by using the Properties method& o3 s5 O }: d% g% [
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers% \, l/ H' k6 n# \
1679351 ALLEGRO_EDITOR REPORTS Missing Fillets Report is not showing missing fillets on the bottom layer( l6 T9 g. J+ k& M9 o
1681002 ALLEGRO_EDITOR OTHER 17.2 STEP output fails to produce an output similar to 16.6
) a6 J+ V" k9 A: W6 Q2 p1682287 ALLEGRO_EDITOR EDIT_ETCH Auto-interactive Delay tune (AiDT) rips lines that have been routed
9 A6 S% g! \! H- | v1 A1682900 ALLEGRO_EDITOR PLACEMENT Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor
' @, \) p' A. B2 J! F6 n |1684117 CONCEPT_HDL CONSTRAINT_MGR Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas
) v5 w, J7 @+ {& [3 X+ p4 u: \6 {" n, j1686803 ALLEGRO_EDITOR INTERFACES PCB Editor crashes if the 'ipc2581_group_drills' variable is set.! s- E/ @, r" B B- e& ^: U; m, v' J
1687816 ALLEGRO_EDITOR PLOTTING Export PDF Vector text option does not work5 O2 X! T* D; t
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.0 H& T( C* |1 R8 B+ C. v+ i
1689881 ALLEGRO_EDITOR DFA Record and replay script for loading DFA spreadsheet not working
2 h4 ?* B) g' u1 t& c1690958 ALLEGRO_EDITOR SKILL SKILL command axlDBDelLock is not working as explained in the documentation
+ L3 y3 E1 T1 }- ?+ M& e3 B# Y1692166 APD DATABASE DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design7 i4 P( c3 A/ f# y
1693431 ALLEGRO_EDITOR SKILL Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section9 U* y* H; i! n7 J X
1693719 ALLEGRO_EDITOR MANUFACT Incorrect suppressed holes information in the drill file created
+ x6 b4 F. |( Q$ I! e1693846 ALLEGRO_EDITOR MANUFACT PCB Editor crashes when running the gloss command" f* X4 @ z, Q$ P1 q
1694151 CONCEPT_HDL CORE Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.- H2 F! ?6 M/ U% M
1694867 ALLEGRO_EDITOR SHAPE Void is deleted by the shape merge command. O+ [0 o8 @+ j/ W3 c
1695131 ALLEGRO_EDITOR SKILL PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function: j5 t/ L9 ]( ^1 R! _
) U# i+ l, ?6 l8 h. U1 Y' p- ~' o, S1 U
Fixed CCRs: SPB 17.2 HF011
' {: y, d7 K, c1 V5 q6 X6 n01-20-2017
+ b3 s P; `* J===================================================================================================================================
: y# T9 n! M, Z! ?/ E% HCCRID PRODUCT PRODUCTLEVEL2 TITLE
# p7 U- n" w- G" {; e5 u===================================================================================================================================4 d7 G5 G* j3 A; k
1618986 CONCEPT_HDL CORE Information required about the DONT_FORCE_ORIGIN_ONGRID directive; j/ u {3 h) I) m
1629696 PSPICE PROBE After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces7 r1 s; N* M2 u+ O m. S: X9 b
1667213 CAPTURE NETLIST_ALLEGRO Tools - Create Netlist stops responding on Windows10
7 M0 s0 w( y5 X1667599 APD OTHER Wire Bond operations taking longer than expected to complete
+ x8 E& X1 E- H# Q7 ~. i+ T6 l8 `6 [1667678 MODEL_EDITOR PARSE Signal model assignment creates ESpice models that do not pass Model Integrity checks
; Y+ @- f2 i8 Y/ o! \# B; u1670120 ALLEGRO_EDITOR UI_GENERAL In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner
~; X! y+ H5 F6 r! M6 g+ n& c1670927 ALLEGRO_EDITOR DRAFTING Using zcopy to create a Route Keepin results in database errors
+ V9 I2 Q/ q' Q5 X3 ?( k. z+ n1675359 ALLEGRO_EDITOR ARTWORK Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off
4 d6 C5 O) V5 i8 L( U( s3 M$ P$ Y1675619 ALLEGRO_EDITOR MANUFACT Differences observed in IPC-D-356A between releases 16.6 and 17.2
% d, j5 y6 ?: h1676161 ADW FLOW_MGR Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error5 c! L V9 j" x7 ]* {! Z
1677405 CONCEPT_HDL OTHER When moving a wire with a dot, the dot is not removed directly
9 C0 S9 l' I( c7 f) \# O% a1678061 PSPICE SLPS Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash: w% L* C. V" ^5 D% E
1679347 PSPICE SLPS SLPS crashes when co-simulating without opening OrCAD Capture or PSpice9 N9 h5 D. B' r1 \
1680113 ALLEGRO_EDITOR SHAPE Irregular void created on dynamic shapes- V: h6 e+ \0 P7 y2 a, P
1680802 ALLEGRO_EDITOR DATABASE A 16.3 database locked with disabled export of design data should be view only in 16.6
c9 n( J, d; N( {1681129 ALLEGRO_EDITOR DATABASE Match Groups in the DE-HDL design are not getting transferred to the board file7 T9 L0 v2 z# k, t
1681514 ALLEGRO_EDITOR UI_GENERAL Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009
# j c, \# |; ?! x' m1681727 CAPTURE NETGROUPS In 17.2, Capture crashes when closing a design that has assigned Netgroups
5 x8 j' w5 } K: p$ t0 j1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version5 L( ]' F' ]# x7 l |7 E# g: B4 {
1682447 CONSTRAINT_MGR CONCEPT_HDL Extraction issue on differential pairs in the given design
' \: `; t4 n/ f! w% J2 s1682454 CONSTRAINT_MGR CONCEPT_HDL Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property) R4 C8 A" Z: s! B6 ?
1682469 CONSTRAINT_MGR CONCEPT_HDL Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL8 K% i: z8 d. R1 L
1683919 ECW TDO-SHAREPOINT Site Minder integration for login from TDA not working after SSL certificate update
% p$ d& g5 E0 l- b* q. Q1684111 ALLEGRO_EDITOR SHAPE Dynamic Shape not voiding overlapped static shape
% e6 }/ T* u; `: V* D) z) W! e1684508 ALLEGRO_EDITOR AUTOVOID Allegro PCB Editor stops responding when deleting a via4 n! s/ s: l: ]
1685540 ALLEGRO_EDITOR OTHER If text is attached to an object, the object is also printed in the PDF9 U% P1 f( n8 X+ d! s& @
1685810 ALLEGRO_EDITOR PAD_EDITOR In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads
# ?6 l3 Z/ \! R& R1685986 ALLEGRO_EDITOR PADS_IN PADS Translator-generated output shows incorrect unit for the soldermask oversize option* a, H, r2 r4 w; D4 b/ t+ D7 ~6 X
1686127 ALLEGRO_EDITOR SHAPE The void of shape missed in artwork.
( {, H! v" K0 \9 e% q/ h; |* n1686791 ALLEGRO_EDITOR OTHER Searchable property unavailable on bottom layer pins in the generated PDF
o5 w$ w# ~( m3 U1 X) Z; R# G$ T. [5 |0 n! q
. L) m& x8 e1 @% F: k, WFixed CCRs: SPB 17.2 HF010
: _2 S" K; F/ s; M! e01-6-2017 & O" c. f5 ~$ T% G' ^0 E
===================================================================================================================================
# I6 z6 k! m! j: m7 |* ACCRID PRODUCT PRODUCTLEVEL2 TITLE
+ c# t7 z6 d: J% W+ E===================================================================================================================================- M1 g1 k- v4 {
1524700 F2B DESIGNVARI Variant file cannot be loaded
/ A& @/ J8 b3 o% ~3 z4 R( K1597787 CONCEPT_HDL MARKERS Save As in Marker dialog causes DE-HDL to crash. c* x5 b# K c) a
1599843 CONCEPT_HDL INTERFACE_DESIGN Moving NG causes extra elements added to it to move
4 v0 T1 f: [3 A/ p" I1620017 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
+ p+ D% h$ _9 @% z; J1632977 CONCEPT_HDL INTERFACE_DESIGN Connectivity error when moving NG members) U! F P5 M# T1 |" T
1635941 ALLEGRO_EDITOR INTERFACES Shape created by IPC 2581 for negative film is not same as the shape on board- ~) _; G! P+ n. Y% O o
1656357 CONCEPT_HDL CORE Pasting a signal name across pages causes the name to overlap with the wire segment
" i2 h! f9 v* x# J1657346 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output
5 E4 b$ b; K4 G& ^% }1 V! X0 E1658048 ALLEGRO_EDITOR COLOR color_lastgroup is not working in SPB 17.2' |# y; G1 N+ R; G# _
1658874 CONCEPT_HDL CORE 'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON
& T6 h. }+ L6 Y! l6 J/ u, C1659030 RF_PCB LIBRARY Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols
. H3 V" x8 ?4 F- t# W) j) n8 v1659097 CONCEPT_HDL CORE Mouse stroke fails to be enabled on startup with left mouse button (LMB)
4 b6 z5 [/ O$ Y; }( f3 I1659532 CONCEPT_HDL CORE About Import Design command with the CONFIRM_WRITE directive
) d9 F4 z. G# i3 B/ n/ i: w1659929 CONSTRAINT_MGR UI_FORMS Using wildcards in filename for Import Constraints does not work in 17.2
8 y+ r5 v0 I7 \8 R( s1660200 ALLEGRO_EDITOR UI_GENERAL Move by Sym Pin # edit box is obfuscated7 D1 Z5 ?2 b+ w( U* }7 w4 e
1662821 ALLEGRO_EDITOR OTHER Cross section chart does not show stack vias in 17.2
& x# g) w+ @) U( v% b1663641 CONCEPT_HDL COPY_PROJECT File - Copy Project in Project Manager creates two designs if there are dashes in the design name
% [1 U( v0 P- k* w% e; c1665652 ALLEGRO_EDITOR SHAPE Critical fillet and shape issues in 17.2+ v4 R# x* c5 B7 d9 x9 j! m* v: E
1665918 CONCEPT_HDL CHECKPLUS Error (100) Program Internal Error 'Create_flat_node' with checkplus run8 j* i8 q* I. B3 T9 i, i
1667056 ASI_PI GUI Power Feasibility Editor does not list capacitors connected to selected nets/parts0 \! o! d# T+ i& I* E- u8 ^
1668137 ALLEGRO_EDITOR SCRIPTS PCB Editor crashing when running Script Replay j- o3 t6 }# V: V+ a4 D- u, _
1669651 CONCEPT_HDL CREFER CreferHDL values are invisible
+ a/ x; E! m% R: w& V1 w) K1669707 CONCEPT_HDL CORE Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property) B& ^' b! i; I1 Q6 j' X- O* J8 `
1670339 ALLEGRO_EDITOR OTHER Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.8 l4 y1 v/ {! f. H+ H' J. q
1670564 ALLEGRO_EDITOR MANUFACT Exported Gerber file cannot be imported in brd
9 x- I, G" O* G# r7 @2 M; d1670687 ALLEGRO_EDITOR NC nclegend.log reports missing columns which are present in the NC Legend
( j" b0 y6 d. o) U1670811 PSPICE AA_MC AA MC Plot settings options
5 M+ F# F0 r5 B- k5 d1671428 ALLEGRO_EDITOR UI_FORMS Display origin checkbox position changes in Step Mapping dialog
; q) s1 x0 L2 E6 |1671728 CONCEPT_HDL CORE Option requested to reload preferred_projects.txt without re-opening DE-HDL# D4 b/ v$ _. y& C3 e
1671901 ALLEGRO_EDITOR UI_GENERAL Toolbar and menus are locked or greyed out
7 A4 q2 c6 e/ l! n. J3 \4 R% m1672477 ALLEGRO_EDITOR DRC_CONSTR DRC generated by Dynamic fillets' ^: q+ M K1 |4 ?, c
1673499 ALLEGRO_EDITOR DATABASE Drill table title issues of backdrill designs in 17.2# U( U# q5 w& E \. e
1673681 ALLEGRO_EDITOR UI_GENERAL F1 for Help not working in PCB Editor 17.2
+ A) _1 X# ^7 |, s1675499 ALLEGRO_EDITOR DATABASE Running the Gloss command causes PCB Editor to crash...
9 C0 k* v7 e& z2 m( l/ o) |- F4 c% q1676480 ALLEGRO_EDITOR MANUFACT Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing
0 A, F+ i4 L0 J+ F! I& H1677431 ALLEGRO_EDITOR DATABASE Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
X' Y+ `: P( O6 a% l1677651 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crash on design after successful packaging
: L+ }5 p$ I+ K5 B ~1677672 CONCEPT_HDL CORE Whitespaces in URL links are not resolved correctly on Linux with Firefox) a; z" L* }( c4 G3 P
1680837 ALLEGRO_EDITOR SHAPE Updating the shape makes the shape disconnect from Thru pins of same net; f9 F$ }: ]* M% P' ^+ i6 v0 L6 q- L
1681059 ALLEGRO_EDITOR SHAPE Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.2 d( G J- B8 c; L
1682312 SIG_INTEGRITY LICENSING Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix
# t; W& w$ O% N; |9 p- H3 }1 ], e7 q# D
# Z, U3 k* g: D# L5 Y) F- h
Fixed CCRs: SPB 17.2 HF009
* ^7 V4 `, d: K# b% T' s6 p3 ~12-8-2016 7 t6 P! q+ i7 e# D
===================================================================================================================================! F1 ^' T7 Z8 m8 U& I! s8 S
CCRID PRODUCT PRODUCTLEVEL2 TITLE' m1 R0 {+ o' ~ G+ E
===================================================================================================================================% ~$ N# f5 G2 U+ g! G q0 f0 d" o
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file! s5 l1 {: j) F- g
1311687 PSPICE MODELEDITOR Timeout error while translating IBIS model* m$ ?$ [- ?8 y0 @- a
1327174 PSPICE MODELEDITOR Log file should list error details during IBIS Translation
1 J& s% k9 J0 D2 O1499665 ALLEGRO_EDITOR INTERACTIV Offset Move depends on move setting.
# A2 r4 j/ P$ M" _$ w4 ?1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
, _; Q, D {, k7 J- N$ c1565795 ALLEGRO_EDITOR UI_GENERAL Search does not work in the Defined Variables window
/ `& \% E% t, E) P/ M1568817 ALLEGRO_EDITOR UI_GENERAL Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8: d0 W c: W, U4 A" N* U
1569272 ALLEGRO_EDITOR PLACEMENT Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit; b C$ F: m/ c" M( g$ C: Q
1577379 CONCEPT_HDL CORE Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
/ a, q m% W7 u& T0 ?, c1578523 ALLEGRO_EDITOR PAD_EDITOR Library Padstack Browser does not refresh preview5 w# t5 R0 c( Z) g' H' ^
1578533 ALLEGRO_EDITOR PAD_EDITOR New Padstack Editor does not automatically update the geometry* Y; y2 o0 r, n/ h2 X
1581129 CONSTRAINT_MGR UI_FORMS Unable to dock the Electrical worksheet in Constraint Manager& A6 C( H# R) j* P2 P
1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data$ [. W0 K! ^0 @ C. }9 W9 A8 F+ w
1591027 ADW LIBDISTRIBUTION Library Distribution redistributes previously distributed models# r3 A( D3 J' F& Q& M w2 |
1592026 CIS VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design& c- P/ u) C, |. }) L% c7 k2 d
1593389 CAPTURE GEN_BOM Include files in Tools - BOM not working5 q! H a8 s# C) o* d. V
1593404 SIP_LAYOUT EDIT_ETCH Slide command moves via toward the object
$ I( y7 i6 ?: G6 Q' Y1595872 CIS PART_MANAGER Capture CIS Part Manager PCB Footprint update case-sensitivity issue
6 y% b) ^8 M! [# @/ k+ H1596955 ALLEGRO_EDITOR EDIT_ETCH Scribble mode is not working as per expectation.2 z4 h8 u$ D, D4 P Z& i/ s
1600936 ALLEGRO_EDITOR INTERACTIV Pin DataTips differ between 16.6 and 17.2
( G$ X3 f& y! i1605961 ALLEGRO_EDITOR COLOR Wildcards not working in the Filter Nets field of the Color Dialog window' L0 F4 z! b3 b1 x: p/ d
1606392 ALLEGRO_EDITOR PLACEMENT Filmmask not shown when component is attached to cursor+ ?0 Y( `; v. {& N
1607016 ADW TDA TDO crashes after LRM update during check-in hierarchy# J3 ?/ l: q3 @
1608059 CONCEPT_HDL CREFER Removing crefs from top-level design also removes .csb files from lower-level blocks
' Y6 c8 G7 ?/ n2 B$ c# E; a+ H$ m# K1608278 CAPTURE OTHER Crystal Reports: User is prompted for ODBC password to create a BOM report `" W1 h" }% l1 I) l) v. X) M9 i
1610377 CAPTURE PROPERTY_EDITOR Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property0 J9 }4 @& e O' {$ ]0 H7 F
1610456 ALLEGRO_EDITOR DATABASE Strip design and selecting user defined subclasses results in database corruption.. T, M& \) L9 m# d/ j. `; {
1612793 CONCEPT_HDL OTHER Pattern-based auto-distribution of split symbols not working if there are spaces before commas$ n+ n/ D5 m2 k% t5 \" L
1613442 CONCEPT_HDL CORE Signal names are not horizontally centered when the wires are added using different methods
! Q9 u6 H8 S$ `' a4 z1613559 ASDA IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported" i6 K- ^ c4 G1 N" @
1614093 CONCEPT_HDL CORE Import Design window has artificial 64 char limit for path - prevents access to some locations: s$ ?( U+ y- `' W$ I: v
1614372 CONCEPT_HDL EDIF300 OFFPAGE symbol is exported as PageBorder in EDIF300 schematic
T, `! r$ D0 t% [( P. \1615075 APD LOGIC Netlist-In wizard fails to import the net names, but gives a successful completion Info message
3 R6 ^( Y6 H2 k+ w: \8 `1616131 ALLEGRO_EDITOR PLACEMENT While placing a module, the Mirror command in the right-click pop-up menu is not working6 |/ u/ |: Y( E8 [
1617377 ALLEGRO_EDITOR UI_GENERAL Visibility pane does not retain the correct layer view U( B6 c( R4 |( S: b& P/ ]$ ?
1617404 ALLEGRO_EDITOR UI_GENERAL axlUIMenuChange does not work as expected in 17.2
! Q8 A7 \+ i% c$ |4 H. a! h1619412 ALLEGRO_EDITOR INTERACTIV Script to create new padstacks from existing padstack is putting in wrong values for a regular pad
7 n& B( K9 y) `: J; Y, O, ?8 @1621842 ALLEGRO_EDITOR PLACEMENT mechanical symbol without placebound will not place in QuickPlace0 B8 W. W w" _" x
1621874 ASDA PRINT Print - Save as PDF uses the default printer options only( ~8 x- K+ [# w0 i) W
1621887 ALLEGRO_EDITOR INTERACTIV Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option' y- S( Q3 I3 Y0 @
1622680 ALLEGRO_EDITOR PADS_IN Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message# R4 U' E( C3 ^4 f: H
1623832 ADW COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073/ I: m, E2 Z0 V6 E9 z; M$ p
1624813 CAPTURE GENERAL The Value property is always left aligned when placing a symbol on the schematic
% A, f/ [. O# W1624953 ALLEGRO_EDITOR UI_GENERAL Custom views in 17.2 do not return to original
) X6 U0 m _' H; G% u( _/ ]( V1625000 ASDA CANVAS_EDIT File - Save Project does not provide any indication of saving or progress bar
' B b' C$ `/ V* W" g1625163 CONSTRAINT_MGR OTHER There is no status for the analyze command in the Constraint Manager in 17.2
9 h3 N6 \ e' c2 h/ u1626647 PSPICE ENVIRONMENT Capture crashes when loading a design with two hyphens in sim profile name( e6 \5 U H: G3 y
1628357 CONSTRAINT_MGR OTHER Constraint Manager shows differences if exporting and importing constraints on the same board.( n1 N, r' b( x- z! j$ x0 ?
1628409 ALLEGRO_EDITOR PAD_EDITOR Pad Stack Editor does not remember last used directory
5 r0 X- |. p5 p' M1631443 CONCEPT_HDL ERCDX ERC reports warning due to lower-case value of some properties in chips.prt6 z* x) I7 ^3 c1 S# t) a
1632195 SCM OTHER 'No known page border found' error in cref.log
9 B& c; ~0 o2 u$ r4 x1632365 CONSTRAINT_MGR OTHER Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2$ j4 o. q* ]( s# U9 a* ]& \, G
1632462 ALLEGRO_EDITOR 3D_CANVAS 3D View (new) and PCB Editor crash when checking collisions
7 k7 h( Y; H" S; d6 @- D: l1632590 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when 3D View is open and more 16.6 boards are opened
. }. W3 U) r2 ]2 D. v; I$ G- B' k1633433 CONSTRAINT_MGR UI_FORMS Expand - Collapse feature for multiple objects not working correctly
) _ k; k1 Y* F/ s5 }5 B1633454 ADW TDA TDO crashes if DAO throws an exception, N! N; c$ L& u# V% P9 B
1633526 PSPICE AA_PPLOT Spaces in Simulation Profile cause error in Parametric Plotter
2 o5 g9 U1 j' b5 i: P1633608 ALLEGRO_EDITOR COLOR 'Retain objects custom color' should not enabled as default.3 u% K, E9 B, L( W- D# T/ C
1636216 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device1 G D. T3 N8 J# j! E
1636899 ALLEGRO_EDITOR 3D_CANVAS The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.. d$ G* }& x8 ~. g
1638185 CAPTURE DATABASE Opening CIS database locks all part libraries none of which are open
0 h/ t m. }0 R1639409 ASDA CANVAS_EDIT Handling of MAKE_BASE property from DE-HDL designs imported into SDA( L3 b3 J& M# d+ j0 a
1639541 CONSTRAINT_MGR OTHER PCB Editor 17.2 crashes when making changes in Constraint Manager
9 U% b* F# A4 v" Y$ X, ^3 }, z1639613 APD STREAM_IF The stream out command has created sharp angles in the GDSII output file
: D) z. L/ ~; T C( ~1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix( `" g K: L% L. s4 ^& M6 t
1641118 F2B DESIGNVARI Some DNI parts are not identified in the variant view due to the BLOCK
4 G7 A P! U7 u! t1 M" V1641410 ASDA CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet& y2 P; I* O/ [% ^+ a8 R' ?
1642891 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes randomly while working on Constraint Manager: I0 h4 ^4 I) Z
1643003 CAPTURE PROJECT_MANAGER Start page shows latest as S004 after installing S005
1 \6 P/ ~$ v5 x1643532 ALLEGRO_EDITOR OTHER Strip design command fails to delete symbol text in the attached design9 N3 q5 b) t, D) t* J
1645529 ASDA CONSTRAINT_MANAG Unable to delete the diff pair from the nets
9 ?3 B9 r+ E3 r' E1645639 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when the XNET_PINS property value has a trailing comma character
4 h7 C" T) L1 F/ ?1646354 CONSTRAINT_MGR CONCEPT_HDL Cannot select Design Instance/Block Filter from the View menu in Constraint Manager
( s3 x) e" R( ~; V& Q+ }1646612 PCB_LIBRARIAN CORE Generate Symbol option crashes Part Developer8 [# V9 B/ q' m' X
1646932 ALLEGRO_EDITOR MANUFACT Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
) G& X: |4 P# F# n6 Q }$ v8 q1647190 APD REPORTS 'Sorted by Bond Finger' report shows incorrect wire bond connection& E9 X F5 P7 m7 A- i
1647673 ASDA EXPORT_PCB Two Physical folders are seen after installation of QIR* n9 H7 r1 ^5 a) P5 ~; t+ r: ]
1647729 ALLEGRO_EDITOR SKILL axlFillet returns t when fillet is not added.- L Z' N- t) G8 j
1647779 CONSTRAINT_MGR OTHER 'Software Version' in the cmDiffUtility viewer does not show the correct version
) Q( X1 ^3 i6 C( `2 K% c1647843 ALLEGRO_EDITOR ARTWORK Misleading information in command window when artwork import fails% T3 u- g/ i1 ^
1648575 CAPTURE OTHER Suppress warning setting must be written in capture.ini file
h2 e, ^5 k# e, M! V. u1649060 CONSTRAINT_MGR CONCEPT_HDL Rename dcfx to dcf process results in error in log file and dcf not updated
. t& E6 ]! A! E; p& \1650106 ALLEGRO_EDITOR 3D_CANVAS 3D canvas rotates mirrored components in unmirrored angle
0 V, G/ j+ Z0 ]$ `3 k5 @( i+ j6 @1650238 SIP_LAYOUT WIREBOND When performing 'Adjust Min DRC', the reference bond finger should not move.$ Y" R8 V4 ^5 K- D
1650734 APD SHAPE Shape on L1 does not flood properly
, |( M1 v5 {2 H1650793 CONSTRAINT_MGR CONCEPT_HDL Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly
0 C9 x: j+ k& J2 m: c1650801 ALLEGRO_EDITOR SCHEM_FTB Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe
5 A+ s! T4 U: D- N( F1651011 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D viewer shows mechanical symbol mirrored6 y0 l% r. J# g; D( Q
1651063 ALLEGRO_EDITOR CROSS_SECTION Cross-section preview is incorrect: q7 x* }6 E1 N: j
1651066 ALLEGRO_EDITOR DATABASE Pins not connecting even after running the Tools - Derive Connectivity command2 p: P+ v! p8 F) ?0 Z
1651700 ALLEGRO_EDITOR SKILL Running axlXSectionModify() on a layer removes the value of the material# u# n0 t, y7 b, z& @
1651925 ALLEGRO_EDITOR ARTWORK Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output5 K$ H& L8 g3 v- k P& D4 w5 d
1652230 CONCEPT_HDL CORE The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols
# y1 A1 V$ r: e* J2 z1653080 CONCEPT_HDL ERCDX Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5
. u# h: w5 z) W% _' k' W: @' m, b1653422 ADW LIBIMPORT Classifications not linked to a Part Number or Cell Model are removed during Library Import
# l5 ~# m" h4 ~& T) `! C1653526 ALLEGRO_EDITOR DATABASE Via padstack keepout is not displayed on the canvas when pads suppression is enabled.
, \. n9 ?0 v( q# I; d) R1653951 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message: \, T: c0 m+ f# X; R, W* D
1656224 ADW FLOW_MGR Copy Project wizard no longer allows dashes in the 'Name of new project folder' field
4 R$ p$ J3 z; o9 }1656581 ALLEGRO_EDITOR OTHER PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected$ i4 D W, E2 p- W/ X% B
1656608 APD REPORTS Incorrect calculation in the metal usage report
& @6 e7 Q9 `( f8 p# n7 N$ M1656726 CONCEPT_HDL CORE Interface command always disabled in the Wire menu
: M0 o+ ]; Y" b+ s% N! L! v1656841 CONSTRAINT_MGR UI_FORMS Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
8 D) A- k1 R; k% D1657220 ALLEGRO_EDITOR SKILL axlXSectionGet() returns Primary list of layers and not All stackups5 n8 T) {) w' \2 _
1657257 SIP_LAYOUT EXTRACT When using extracta, custom layer names not getting retained( ^( h; @; c6 c3 ~. v
1658440 ALLEGRO_EDITOR PAD_EDITOR The location of a drill in the .pad file is different from the .dra file
/ v* T0 B+ A8 c: R- x1658445 CONSTRAINT_MGR CONCEPT_HDL When DCF file is converted to ASCII, no further updates are allowed./ \% K8 s- f% g9 W$ p/ e- s4 k
1659473 SIP_LAYOUT WIREBOND When moving wirebonds they are jumping instead of sliding
# m; J# j, m5 D# y) a& \4 m1659498 ALLEGRO_EDITOR INTERACTIV Unable to turn off line on Etch Wire for Jumpers, u, w/ i: \# C$ S" E
1659644 CONCEPT_HDL OTHER Predefined nets are not listed if 16.6 design is being opened in 17.2! F/ w6 c* Q+ O# n* p4 r
1660475 CONSTRAINT_MGR UI_FORMS The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
7 P1 b! H# f% T+ l1660492 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes when using multiple desktops on Windows 10 o' Z O- J5 B3 D+ I* R
1661133 CONSTRAINT_MGR ANALYSIS PCB Editor crashes if comma is used in the Value field for Analysis Mode
: p/ [9 [# w! }1661307 CONSTRAINT_MGR CONCEPT_HDL Prevent creation of diff pairs on VOLTAGE nets
& L. |1 j6 Z/ N% `5 S" N1661357 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using Route - Connect2 U9 l7 a& ^( {6 I. R. A1 Z# `
1661874 ASDA DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page# `; z* v' P. J" s( V# X
1662799 ADW SRM Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager
- \: b$ {/ z3 L/ D8 R4 }' `1664797 SIG_INTEGRITY GUI Unnecessary coupled interconnect models were generated during View Waveform.9 E) _/ E6 [+ z$ I+ \, M4 @: w2 P
1664858 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during Auto Interactive trunk route.2 A6 h. K" o' a H5 v; Q
1664911 ALLEGRO_EDITOR OTHER PCB Editor freezes after DRC Update is performed, A% {4 [0 L1 e
1666329 CONSTRAINT_MGR OTHER SCM Import Physical process crashes cmfeedback
% ~/ [! T( T% h* O1 `1666551 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option separates imported artwork to different XY locations' T$ m2 p& ]+ G2 U$ i) k7 h
1666723 ECW TDO-SHAREPOINT TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML
( G& a+ D% J. x, |& y1 Q1667068 ALLEGRO_EDITOR SHAPE Update shape removing the shape voiding+ q" w( Q2 M/ e( Y
1669828 F2B DESIGNVARI Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops0 x, a4 e5 l; N9 U
1670221 ALLEGRO_EDITOR DATABASE Non-recoverable corruption error is reported when saving the board after adding a layer
3 f, k' ^# v5 `5 N; j; k, }( Z: H1672134 ALLEGRO_EDITOR ZONES TDP needs FIXED component override& o( f% t9 Y0 q! A) m& Q
2 X/ k8 s0 `2 X0 |8 b; N
Q; P. r9 m$ j/ i0 e6 w |$ {Fixed CCRs: SPB 17.2 HF008
% o; u5 f3 A$ d6 M7 h9 @10-29-2016+ V7 A. J; Z# P* Z4 r7 l: {& H
===================================================================================================================================* L4 t# n! J8 g! s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( Q6 {7 {' ?) Q/ M===================================================================================================================================
, O* _9 I3 Y' q! ?0 w1644406 ALLEGRO_EDITOR SHAPE Alternate symbol placement results in illegal parent identifier error
* m# z* g& q7 L$ A$ c2 T& P1647098 SIP_LAYOUT OTHER SiP crashes on symbol copy and rotate
) _) K# G1 x$ ?# C9 W2 [( }; ~1647154 APD OTHER Disconnected Clines not working
) R. T' k, o Z% h& R; A+ m1 i1648817 GRE IFP_INTERACTIVE Allegro PCB Editor stops responding on adding netgroups to a nested netgroup
3 D- ^( n9 T8 F* C1649829 CONCEPT_HDL CORE A delay is observed before the sub menus of the File and Tools menus appear
9 ^, x6 Z7 _* ?7 z) n1652930 ALLEGRO_EDITOR OTHER Command-line version of switchversion not working
1 S, L/ r% a0 b1653109 ASDA DESIGN_CORRUPTIO SDA not pulling latest library information for part2 d- E& C3 ?% X% x* T
1655377 FLOWS PROJMGR Project Manager crashes on Windows 108 H" S7 p, D& y
) B8 ?% O( L$ l
9 g2 j- N8 r: N! O; s2 `
Fixed CCRs: SPB 17.2 HF007; t8 M% r4 A1 H# _6 Z' V6 j3 R! f" f- x/ W
10-20-2016
|4 p- ]" c4 G1 ]+ z$ y===================================================================================================================================
\4 g5 W6 m* ?$ ^7 X0 L( T1 nCCRID PRODUCT PRODUCTLEVEL2 TITLE! ]6 d# N, A6 E& ~. \( x3 @
===================================================================================================================================! ]% D* F, E( k s0 S
1582276 CONCEPT_HDL CORE Need the ability to delete an image placed on the DE-HDL canvas
; g& ]& |3 R1 _+ N& m ~- w; B( n1594101 CONCEPT_HDL CORE No error or warning issued on specifying an incorrect unit for voltage2 M& c9 m% f; X3 D. g" i
1611293 ALLEGRO_EDITOR UI_GENERAL If the Command window is floating, it cuts off text from the bottom half of the last line.
' i! F- P; S Q# ]1611652 ALLEGRO_EDITOR UI_GENERAL New artwork film not appearing in the drop-down list for Visibility Tab; M' ^4 _/ n1 J2 j
1618205 ALLEGRO_EDITOR UI_GENERAL New Artwork film added is not updated in Visibility - View
( Z# K! ]! K( j- }' t9 G1631114 CONSTRAINT_MGR OTHER SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names% y) m$ @. q- J, F# a8 w
1633726 ALLEGRO_EDITOR UI_GENERAL Visibility tab not dynamically updating the view list when artwork film changes7 N& ^- }/ D5 z9 O
1636404 CONSTRAINT_MGR CONCEPT_HDL In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
" J: {0 H x/ c0 V1636864 ALLEGRO_EDITOR UI_GENERAL Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file
5 t- C: q, t$ r/ x! X; U9 j+ a1638251 ALLEGRO_EDITOR DATABASE Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version
; h$ K9 ]- ] j L1639483 ALLEGRO_EDITOR EDIT_ETCH Manually routing discrete components with incorrect constraints causes PCB Editor to crash
# j7 ^7 y5 q! d6 r$ P: V0 l) d! j6 e1641435 SIP_LAYOUT IMPORT_DATA Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count
) y+ B' O% y4 u& ?5 s/ i1641483 SIP_LAYOUT WIREBOND SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint
+ L4 Y2 L0 ~ x; }1644131 F2B PACKAGERXL Option needed to package a DE-HDL design with ptf errors into a board file
) d0 x# l" n1 I* V1644807 CONSTRAINT_MGR ANALYSIS Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses& O+ z3 f; S2 H. D
1646228 ALLEGRO_EDITOR UI_GENERAL Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool2 j" s' A5 i: K2 C7 ~: J# Q
1647402 PSPICE PROBE Unable to print on Windows 10 as no plots are displayed in the Probe window1 D \* C7 Z2 H+ z
1648183 ALLEGRO_EDITOR INTERFACES Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes; k) W/ k+ P# a, O
1649222 APD ASSY_RULE_CHECK Allegro Package Designer stops responding on running the Acute Angle Metal DRC
3 d w7 ]+ @2 L' W
& l, Q. a- m/ n$ D/ t o% N& m" D
Fixed CCRs: SPB 17.2 HF0064 P2 J2 q+ U1 Y/ ]2 h. {& w! ]$ M! C
10-7-2016
' p1 \9 w" T5 d; V, M/ \, C; O===================================================================================================================================
: P9 R v; a; d& ?- [( ACCRID PRODUCT PRODUCTLEVEL2 TITLE* l" c' @9 {+ F8 _
===================================================================================================================================
: U' o% }% H' i! r9 `1585203 ADW DBEDITOR Optimize check-in of footprints with multiple padstacks
, ^% d3 o+ o/ v1607954 ALLEGRO_EDITOR SHAPE Dynamic Shape not updating correctly4 o* e% S! O' N' v0 T
1618173 ADW SRM SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003/ J5 b# W: [( d4 a- E' J9 A+ H6 R, s/ I
1618832 ADW SRM SRM marks parts as updated even when they are not updated
- K' \! q4 S8 \4 x- ]3 ]/ C9 k1623823 SIP_LAYOUT WIREBOND NO_WIREBOND property is ignored by Add/Edit Non-Standard
4 [: X/ F& Z0 j: X1626001 ALLEGRO_EDITOR SHAPE Shape to route keepout DRCs reported for dynamic shapes in the attached design! r- q' f. q: f7 Q0 X) b3 @
1626546 SIG_INTEGRITY FIELD_SOLVERS Extra RL elements in via spice circuit model generated by Via Model Generator5 b% l# H: h& T. J
1631792 SCM OTHER The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design
6 }- s/ X0 q8 j2 {8 k1632223 ADW LRM Checking in a hierarchy causes a crash. n2 z" i6 \) `/ [9 b' b8 t& R5 y% t
1632844 F2B DESIGNVARI Part is simultaneously defined as Pref and DNI in Variant Editor with no error9 Z# M- ?! H6 v( G/ I
1633647 ALLEGRO_EDITOR MANUFACT Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design
% p, [, Z4 }$ k; Z! x1633707 ALLEGRO_EDITOR DATABASE Cannot remove Route_Keepout associated with a pin
O$ A9 l# U* c4 I1634392 PCB_LIBRARIAN OTHER Launching Library Explorer without -proj option crashes the tool
' {5 K7 m. M/ Q2 i2 T2 N1635049 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when trying to create layer set from Constraint Manager
/ r' Z5 o8 H1 ?! f. s: F! n) r1635593 ORBITIO ALLEGRO_SIP_IF Importing .sip file reports undefined argument error while processing shapes* |' V1 o* G: b
1635858 ALLEGRO_EDITOR ARTWORK Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers
% g3 x/ w+ h0 ?+ |: `9 f1636097 ALLEGRO_EDITOR ZONES Technology Dependent Packaging footprints not updating in the design
. I8 |/ X& C; `- D5 o9 v1636185 ALLEGRO_EDITOR ZONES Import Placement not placing TDP footprints in zone! E9 A+ G- k4 Q
1636867 CONSTRAINT_MGR OTHER Millimeters shown as mils in the Analysis Modes dialog box
: B: M- m1 w# O1638094 SIP_LAYOUT OTHER Cross Section Editor not seeing updated information
3 d2 f" I6 H3 E. g% u. h' K1639845 ALLEGRO_EDITOR INTERFACES Step file not generated when board is exported to a folder with special characters in name- C$ _3 G3 Z3 ^7 I* V0 z( R; j
1640611 APD SKILL Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM
1 i, q3 z: Z( T' y, ]1641339 ALLEGRO_EDITOR INTERFACES DXF_IN does not show all the subclasses available in the design
! b" W1 V3 S: F9 h8 V& h2 R4 r( E& x& s1641879 XTRACTIM GUI XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor
* Y% F# {6 a6 r: T1 H1642012 CONCEPT_HDL CONSTRAINT_MGR Schematic-defined net groups without any members cannot be deleted in Constraint Manager
- O# W5 O. ]# X7 @1642015 CONCEPT_HDL CORE Pin exists on block but no corresponding port exists in the underlying schematic& ]% H! ?5 D4 ~' L& Q, h# p, B
1642597 ALLEGRO_EDITOR OTHER Importing .tdp file: Footprints not included in the .tdp file are updated in the design
8 j% `& k) L( }1643557 SIP_LAYOUT DIE_GENERATOR Die Text files will not update the design
. N6 P( \/ v4 i) }, q& j9 \1646086 ASDA IMPORT_BLOCK Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'
8 I# d1 B( D5 n/ s, v1647580 ASDA IMPORT_PCB SDA-File Import from PCB Editor has duplicated RefDes on schematic.) M" j! i( }% d# |/ Q% s; \# ]# ~
0 C; h) S2 O* S# S
9 I% _, B% K: R) ZFixed CCRs: SPB 17.2 HF005, \$ f" x: X3 M* t/ b
09-10-20160 i- S3 H( W6 F7 ]6 `
===================================================================================================================================
( k2 C- X$ b1 t9 i% G3 xCCRID PRODUCT PRODUCTLEVEL2 TITLE2 x" r$ j/ k; g& N0 o- z/ m
===================================================================================================================================
" q) S+ g! q' Q8 R0 U/ d1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape+ T( z5 i0 q+ |
1519972 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC at incorrect location
# `. }1 L! p" O+ L+ R1521940 ALLEGRO_EDITOR DRC_CONSTR PCB Editor not recognizing the correct pin pairs of the differential pair& R1 b! F* M. S. R9 l
1536713 ALLEGRO_EDITOR INTERFACES File - Viewlog still checks for brd2odb.log file5 h9 c: ^9 @$ Z
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
5 Q) W8 S$ d7 E# S; F2 [& Q1586846 RF_PCB PLACEMENT Get an error while manually placing RFCOMPIB part
1 `1 W- k- O4 _# i5 P0 Z+ k: D2 N1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2
* I/ R0 M+ X2 B, |, R1589396 ALLEGRO_EDITOR UI_GENERAL Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
0 @) N- p; c' x B. T4 d2 ]1593258 ALLEGRO_EDITOR OTHER Adding German letters to database diary deletes all the entries+ e$ R7 \3 ^. C ^2 j r2 A
1597413 SIG_EXPLORER SIMULATION SigXplorer crashes when simulating with a via that was added to the canvas5 F$ i4 M' H" |; Z6 E' K' S
1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG Documentation Editor crashes on opening a specific database- C5 E' x) A; T
1606682 ECW ADMINISTRATION ECWBackup and ECWRestore fail when data is 1GB or more7 f7 Z9 [2 W9 b2 T6 U
1607250 ALLEGRO_EDITOR DATABASE A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69% J0 t5 f, A% _) W6 ~! j
1607565 ALLEGRO_EDITOR SYMBOL Default values are not consistently converted when adding pins after changing units.
) L4 J' B7 i8 V6 ]6 O1607956 ALLEGRO_EDITOR OTHER Unable to generate the model index file from the command line using mkdeviceindex R( q' u! S7 S
1609794 ALLEGRO_EDITOR UI_GENERAL PCB Editor: Shortcut keys to menus are not available in 17.2( C) w* X* F% o4 i, f) J
1609817 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes on opening project
6 O. t3 h; V" z0 T1611446 ALLEGRO_EDITOR SHAPE Inconsistent break in shape when creating voids in a design in 16.6 Hotfix 69
1 B% [" \; Z8 I3 M7 W1613512 ORBITIO ALLEGRO_SIP_IF Unable to read the OrbitIO database file (.oio) in SiP Layout
% D6 c/ J% s! \( u+ p1619610 ORBITIO ALLEGRO_SIP_IF Some mechanical pins appear rotated by 90 degrees when imported
# I, B) m/ t- k! {1620814 ALLEGRO_EDITOR PARTITION Etch and Via are not imported with the partition
0 X0 W2 q7 w; p7 u) H0 s4 m1621390 GRE CORE Design Crashes during the Spatial Planning phase; g' s3 |4 I0 T- t
1623112 ALLEGRO_EDITOR OTHER SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode; F/ B0 v' N- h3 ] q; _2 c+ _( z5 w
1623113 ASI_SI GUI Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation
y0 f$ Z. F' o5 d2 Y4 J1623231 CONCEPT_HDL CORE Unable to make the Attributes form part of the standard display in DE-HDL# b* G6 i$ j5 U u
1623666 APD OTHER Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'6 _% [, E; B% n. t6 }5 t" I9 k
1623888 CONSTRAINT_MGR CONCEPT_HDL Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object
H. b8 l) j' s+ U1623904 ALLEGRO_EDITOR SCHEM_FTB Logic import fails, but no error mentioned in the netrev.lst file& V7 j' H0 a% W5 N: S7 ^( R
1623935 ALLEGRO_EDITOR SKILL On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated
! g3 Z) p5 M( t1625610 ALLEGRO_EDITOR SHAPE Modifying a shape boundary leads to other shapes losing their voids
: E% J" i+ [" I1 ~1626716 ALLEGRO_EDITOR UI_FORMS Z-Copy menu is not available with OrCAD PCB designer Professional license2 I4 g: { G9 o: P3 H. |% j5 Q0 v9 `7 k% b
1628403 ADW TDO-SHAREPOINT Objects remain checked out after multiple failed 'check-in hierarchy' attempts5 }9 g1 J3 D) f5 \3 t
1630458 ORBITIO ALLEGRO_SIP_IF Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies) o" s6 F4 _' L( U
1632504 CONCEPT_HDL CORE DE-HDL core dumps during Save Hierarchy on Linux- Z3 {& {9 Q* _6 h
1633581 ALLEGRO_EDITOR PLACEMENT On mirroring a part, the cursor moves to the origin of the board* }! d' k& R2 k0 I0 `4 n: P1 m9 W
1633601 ALLEGRO_EDITOR PLACEMENT Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004
1 ~% x, u5 O% R6 [ E7 ]1 l/ f9 v9 H; P/ }0 T- F
/ v f9 w6 i* ]* g6 f& p: nFixed CCRs: SPB 17.2 HF0045 w9 @! i: R% A: V" }* Y2 V% b6 [: K
08-14-2016
! N0 R+ _* s) r===================================================================================================================================! [# J; R( |- |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 J0 H4 b1 }# U. H6 \6 a0 E% y( {* |===================================================================================================================================
1 _% ~* v; E3 h/ v908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
* E0 s* i, d' {1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)
6 R! a @; V6 c* H3 x- M& P) Z1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE value set to question mark) F! ~* j1 Q$ ~! h
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value8 q0 [- g1 Q" a5 q, |7 K
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets
N& M- J, I# Y5 S* J: s$ S, ^1326716 ADW DOCUMENTATION Dataexchange documentation correction needed
, b K! O- y F: n* X+ ^1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large
( {) a6 z( W' X; h7 q1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.# a3 J+ Q6 D/ f3 c' y; o
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file) v0 N( R7 m# N4 }$ L* k" V
1410485 CAPTURE SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design3 o( |- x5 t: ?( U0 Y( ?
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only9 j8 S3 w2 l7 |8 T' h
1413287 ADW LIBIMPORT Library Import converts all Attributes to uppercase when reading CSV6 l$ {# _9 V) M: c8 a0 @- Y$ G
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
& Y" D8 ]- i/ n& s2 O4 N' N1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
& z1 l& r4 [& |& u M& y1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room
: z* H! s* h/ l8 H- }4 i1440509 ALLEGRO_EDITOR PLOTTING Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option2 B% H: K. l; p( {# Z O' ^
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the 'sym1' view are not saved$ T' M, x8 G' ^7 g! L% ?0 w
1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked
& [3 n- U, G% p1 Q9 H# t" O1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
8 v; t- O6 i, j8 C) Z" L6 @' }1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required
7 k7 ]5 V- j7 w5 ~( ]1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set" r _6 `- a! r% I4 `: v( W
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
; R4 A3 o! H: f7 O8 C8 r4 b1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties. m5 N, c9 Z3 C1 c' y7 N
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
& K m4 h0 z, p. u0 c3 R1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
3 w( }1 h9 ]& P% l% B h4 Y1467826 CONCEPT_HDL PDF PublishPDF from console window creates a long PDF filename
2 O, G$ v# ?) S; e, A9 J2 X! c1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively# E& L! h. Y# Z4 s
1471287 CONCEPT_HDL CONSTRAINT_MGR Pages imported from other designs with different units should inherit the source constraint units
9 F/ o$ f$ Z. m1 T/ J0 |) Y8 h1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
% _" ]* F6 m- d* S+ [8 o1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
$ s5 J# `6 \+ ]( ]+ D1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB054/ADW47- L9 H( I+ u- I5 z* o j
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design2 P/ w3 @, Q; l1 K! Z4 m+ s# X# b& {
1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
; q3 {, a4 H3 N7 C& i1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian
5 b: c, b1 J5 j8 [1474066 ADW DBEDITOR Bulk edit performance lags when parts included have a large number of properties; X5 [. P' F5 f6 @; G$ M. J
1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
^) v i; C* t) A% V1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
" L R) b# H4 g1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_' B0 q" B8 p2 ?. O$ ]
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown$ i. x5 c0 F" u! U ?# D
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
! \9 d/ O ~8 o3 e9 ~' P1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups) g! m( H, j( j/ [9 j3 U- p
1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release; H5 h$ A; e; O& W/ D; H. a. g0 K
1478200 GRE IFP_INTERACTIVE PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes3 }1 t8 N$ |7 V5 {/ f* E
1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys5 a0 G; l+ w- o0 g) U# ^
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy- Q( `4 v% t& `) _/ g% K% {0 V
1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon5 K; j) I9 G% l2 V+ a
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
6 m, g* U; c! D7 [% W ]9 f1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
- r* i8 g1 I$ w$ c& J* p; v4 h1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-10531 o& [; |! J6 i, r2 I" g. k9 X
1479785 ORBITIO ALLEGRO_SIP_IF BRD file is not loaded in OrbitIO$ N. Z6 \8 [: ]3 h
1480005 ADW DBEDITOR The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files1 a7 u, V# U( Q5 Q
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error
9 D+ h d5 P$ X$ U$ f7 ~) i' B' g1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition3 t+ {: ]1 w8 M C# \0 V% y
1482544 ADW DBADMIN Hierarchical Preferred Parts List (PPL) is not functioning correctly/ L2 @3 _8 @4 C6 L' j0 E+ q/ `
1483136 ADW COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode4 v7 `6 e9 |5 ^+ L6 s
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles/ ~. K% R% d( c, M& C1 u: k9 W- t
1484100 SIP_LAYOUT INTERACTIVE SiP crashes when copying and rotating a symbol
) y6 p+ z; E! d1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues: E$ t, n* p3 s8 M+ l2 j
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only7 p+ @! v2 K% E9 F; I% A5 B* U
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file) i0 U- N9 ~8 h5 `" S( v- j
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
; ^: y) ^0 g( X& I1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
4 T* ~' e) C" z0 e, A9 @1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager.
. }1 }* g" ^& |9 o0 {1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems( Z3 j b' h4 _& Q
1487125 ADW COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts P. u8 ^: ?/ w" n
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
) P, M! _; v6 h Y1 G1487496 ADW DATAEXCHANGE DX changes checkout ownership when override action is set to remove existing relationships- ~* h8 y; c. V: O
1487656 ADW LIBIMPORT Pre-analyzing a project reports false warnings
+ c( y9 H/ y* n1487733 CONSTRAINT_MGR OTHER Export Physical takes more than two hours to update PCB Editor board. i6 W$ ]4 m( {7 r) u+ @
1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
4 N/ [: F! c: e) I+ l1488758 CONCEPT_HDL CONSTRAINT_MGR Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync i* k" n3 l! V
1490299 SCM OTHER Allegro System Architect does not update revision properly& l0 M2 y) A5 {8 S, _5 A
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
8 g+ P. N2 Y* p* R5 }1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
. r$ D0 l& _0 X, g1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working5 i4 z% S( x: E9 r3 x6 j
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation), {& H# l" k: |+ r
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
4 Z, k" S; C, q. H7 N1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit6 v' y; H8 g8 i! B4 }/ z- H0 Z
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO crashes on importing MCM% `8 @( i" ]: `6 c$ b& E
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL& b8 U0 `" U" ^
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
3 _7 q/ S) p9 J* n1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
b' ]/ P- }5 R% a6 C" ]+ ?1 t9 b1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
6 j. r+ M9 W: E5 {8 V+ ?1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
6 c+ Q6 m/ O& D( A/ v; {, M2 ?: J( Z1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
X: H% D9 Q8 u9 P2 q( O1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
1 s. a {. }4 [5 K3 ^% M1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts d6 q4 c+ J( |2 E
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant1 K, x! d% I9 x$ e- O; w
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out4 g" {4 P9 u# J7 X
1501294 ADW COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 060+ p, K; F. o6 n5 u+ o T
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
1 O! l$ m. P0 F6 ?: L. \0 B! Z1502282 ADW CONF Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message a( N1 `- K" W9 ~ }9 H! m
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings! b4 H8 j2 D7 s V5 `, d( f% m+ m
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized \. v9 ^0 Y i$ u1 f! f% x) ]
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary, c. W+ K7 x, ]" x" B
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
0 c% K* c9 h# A$ l6 y# o1506654 CONCEPT_HDL INTERFACE_DESIGN On moving, Netgroups break. s7 I7 T. J+ [; v# M, k# E1 L+ z
1507497 ADW COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
8 w1 c2 Q0 t- W8 ^. J3 z1 g1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork6 [* J0 Z: o5 f Y9 C
1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
3 @! S, [- N+ K1 u n0 w$ \0 F1510570 ADW DATABASE ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database
4 Z) ^: i% g& g4 ^; d. m1511180 ADW DBEDITOR Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number
# V' _6 b9 g4 J: `% |' {1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
3 c, h4 j$ a* h1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance% i ^9 T5 y1 @3 `. ?7 A! L
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
) c) u6 q) `4 f/ p- p( B. V* T; [7 F1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
- y7 c$ v( v- \5 H. e( ~1513085 CONCEPT_HDL CORE NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor
* v3 R+ ?+ v2 \3 V% I1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib
$ d& K$ i' V& {+ v! _1513737 ADW CONF DesignerServer from a different network domain does not show distribution data1 E) V/ n( k `2 s
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
~3 m/ H5 i2 g, h% h) v1514942 SIP_LAYOUT CROSS_SECTION AIR no longer permitted in stackup in 17.0
\7 D0 ?/ P- g1 `5 a' o9 [1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly8 x6 |; f5 r" w
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol- W# ?* Z T& o5 j
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
F7 r2 u: m- l1 l1518032 CONCEPT_HDL SECTION Error SPCOCN-2009 displayed even when the user has not manually sectioned the design" y" z7 \0 E+ c4 M" A
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
% V) J8 s6 }6 B3 f( S/ m1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.. D8 @. C4 d$ S
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols' L5 V# h9 r8 R+ u0 U6 |
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
: k1 [: Y4 E4 N; e/ H+ K1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default$ f7 U# c2 Q1 C" d, x% {
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net+ B$ J8 N# I: b& A4 D
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist/ q8 h( |+ e2 |( J9 S
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports! u4 ?6 v6 F0 S: r
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
- h3 F. W$ ]$ }0 {7 i1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor: T! N9 G6 Q5 S) S2 X
1521871 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager launched from DE-HDL allows space in the name of layer sets
+ u8 D- ]+ n7 Y1 S5 {3 b1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.8 l7 @5 j. q2 M- K4 N( M& {
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP Layout design
% Z2 J2 n; q8 P1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
& b$ n6 r; l# Q& r! d4 O/ Z* q1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated( c( \) g3 U2 h* T
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine6 b) O# x# k2 B0 D& n7 O
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor5 `3 ~3 t5 H! [# _" w
1525883 ADW DATABASE Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly8 Y; J$ j* w% q6 i1 m
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
6 w; F$ ~( K- E0 }. A- B1 P7 }: g1526914 ADW LIBIMPORT Cannot import to new library database
. [ R0 c _7 w |; n3 m$ G B: T* y# B; \1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63% l* u( _6 V2 |" y
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
b8 j, f& j0 q; b& G1528235 ADW DBEDITOR Running rule 'Validate Classification Property and Property Values' results in property mismatch error: v% H3 O2 X$ D! m1 r& |* K" C4 \5 C
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
8 R' W) S! h! A9 x- L. I- E1528398 ALLEGRO_EDITOR SCHEM_FTB Netlisting of pins with NC property results in error/ g4 B0 |2 I \% W8 W+ [
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
0 h; p$ p/ K9 E' L* F' X0 E1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents the release of the part
; J+ a! L8 \! I1 @, v0 w1529178 SIG_EXPLORER OTHER When an ECSet is created from a net, values are not transferred correctly for PinPairs2 ~/ q3 s U. \- H; g
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions/ G, P6 ^. y9 d: l+ _8 M' C
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
* _% E" I2 p0 l0 w5 k) N# H" H6 J o1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used J, d! U2 G; m; j
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes1 _; x6 D( f% _$ X/ I* P, G
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup* S+ J9 G) o; |4 s' z1 T) a G8 S$ D$ K
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
6 W+ g; c4 q" r2 X9 v1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists7 M% Q. ?$ t, q6 e n: o
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue, W5 F" A1 C( w& @, f
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties! F6 E$ Z) ]# V& g3 W5 I
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net( ^7 i; M- @+ O' g; C
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
$ t" n Z- q3 [" G7 `7 W; i8 t1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'3 Z$ `0 Z& c$ A# ~1 o- o, j) q
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
5 u+ ?) |( A' f- r& ^1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run: V& G( I6 V' `
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error- x* {3 s, a& k8 n) j
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
6 g/ D, \0 m& X3 F! b( k1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
, x& }2 z% a. J: i6 z% b1542949 ASDA EXPORT_PCB The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted1 Z0 @" W+ i$ A5 v0 R4 W, I) _
1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer. @/ ]( ~- Y' m: H2 q
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash0 [7 {& o6 M0 U
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash; \8 G+ O7 K# m, @# g/ O P$ ]
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
9 s3 w& M7 z& p. [, Y4 {1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.
0 S! r8 m9 N# ?5 }1 P. K1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
) q8 V! h/ g$ A; b1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information
8 }4 o" \; H. ~- h5 w# _1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'- }# D, v# b& z, O& a9 z
1549658 ADW TDA An unmapped network folder in the Team Design Authoring option results in an error9 j/ X6 h' u3 x* u) v
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols! ?# M7 k5 C5 d! S1 z: S- x
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects
( h$ Y9 h# y$ l/ x) h3 O& X7 i- j1553027 ALLEGRO_EDITOR UI_GENERAL PCB Editor canvas stops responding for tasks such as resize and workspace switch( {$ G1 c6 K# @: l3 I" q8 s- ?
1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
6 Q/ Y. `/ s$ `' b7 Y1555254 ADW DBEDITOR Text in Free Text search box is removed if it loses focus
8 Z! Z7 H. R: ~: b5 u8 g; n- V8 P1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
1 `! \2 v1 X, v5 f1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export+ |& ]6 S F' ?& O3 F5 y
1580571 ADW DBEDITOR XML files continue to appear in flatlib even after the padstack/footprint models were released
7 s' u$ X' n$ h/ O1580580 ADW LIBDISTRIBUTION The .lis file contains references to old models even after they were purged.% X- f5 \! K/ I+ h6 r& d; A
1582064 ALLEGRO_EDITOR UI_GENERAL User-defined menus not working in PCB Editor 17.2
9 e# c9 z) T% K5 c$ e9 Z/ C1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
, x5 n% {* h. w1 f4 `1582856 PSPICE MODELEDITOR Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created* }* r% W. D5 X' w
1584719 TDA CORE Caching errors are flagged for a board-ref project during block update2 d0 s, x& }+ q' K- j8 u- D
1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file3 {7 C6 k/ m- o6 `$ Y# y0 t2 f
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option
3 q5 l3 \- l" g: M1588736 PSPICE MODELEDITOR The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor8 W; o+ p. S" `' ^/ R$ P
1588742 PSPICE PROBE Browse icon is missing from PSpice File - Export - text+ D, D H! Z0 l) X
1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened
6 p; G* h3 m( Y1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons
) v) Z' z" L7 V" k! t9 E; c1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork8 W$ |8 p5 D7 V4 p# M3 b" X C- q
1592089 PSPICE MODELEDITOR Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator1 d; Y7 ^3 f1 W) B$ V
1593436 ADW DBEDITOR Cursor does not automatically move to the model name cell when creating a new model7 E; o" v! ^, d3 V4 {6 @
1594076 TDA CORE TDO crashes on concurrent check-ins when one of the blocks was not modified.
4 n" G6 e% {( u) r* v1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode
6 J/ C: g% i) F* S* ?1596162 ASDA IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well3 T# d% a" }3 m. Q9 [. [0 H% c
1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.& p* y5 R; K+ N" S* u- `% n3 m+ y
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas" t* L1 f5 }3 `* I8 E" h
1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated& j# Y0 h! y. f( m- d( g* m
1600194 ALLEGRO_EDITOR DRC_CONSTR 'drc update' gives a different DRC count each time the command is given in a multiple-cpu system) {4 h3 O9 m# J% D- n" n
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating. P* G: e/ |; o/ _+ Z
1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
1 z* a$ {! O$ N1 Y; h; p1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.
, h: M8 m" b0 K8 d" [1603377 PSPICE ENVIRONMENT Running simulation with the 'At Markers Only' option does not generate the .dat file n* }7 n# q9 U; e, F; }
1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header
9 [, ~4 j, P" A, I2 j. u9 D4 j- A1604741 ASDA CANVAS_EDIT Tcl console changes the present working directory when you open Project Preferences and close it.
5 d( N" N/ V) f) G* T$ R, z P1605310 TDA CORE Join Project wizard: Random crashes in the Team Design Authoring option
. C E3 J4 ~# N/ z+ W6 h+ U" d1606861 CONCEPT_HDL CORE DE-HDL crashes on Linux during the Generate View operation @$ _. t" S- u& Y
1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset, _/ N7 h z6 W1 F r
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons( t* P" R- n# M, W% b
1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set6 o$ `- I# p$ w
1607568 ALLEGRO_EDITOR NC PCB Editor shows wrong drill legend for Top-to-Top drill; M* Q1 w% V/ z" a/ Q: D+ b( b
1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2
: v- B% W4 G6 G% r" {: T1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
: \$ L: Q- u8 r1609400 ASDA CANVAS_EDIT The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected
' q( A; ^# H( }# m8 W, j1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux
+ q" ]2 N$ ^2 M- ^8 ?' j. G' s" P7 j1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.
7 v3 _" `( H3 M o6 H& C1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
5 T' E% _/ U) D1611226 ALLEGRO_EDITOR SYMBOL PCB Editor gives a crash message while saving a flash symbol2 [0 m! Q) l& n, {: k
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.
" g' b4 J/ u" G" M9 m! u1613123 ALLEGRO_EDITOR SKILL DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'
- w9 b# |$ H& B1 i; `1614000 ADW LIBDISTRIBUTION Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running: O5 \$ n& K. i
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in Allegro Sigrity SI and SigXplorer' s9 q, T. \$ V8 Z% I/ [' Q' i
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error
: X, u& s* L9 t2 G, x1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import does not map layers correctly
8 h/ ]: `8 X8 Y( T0 r1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update
. R- ?5 }& y: J3 \1616733 ALLEGRO_EDITOR INTERFACES 'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'
, E1 w& i2 e2 ^ f' X1618751 ASDA DRC Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file
. J6 w' x" q3 d: B/ `6 L1618797 ADW FLOW_MGR Flow Manager cannot execute a specific command in 17.2.) K) E- b' d" ]
1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.: L0 p9 Z1 S; t; b) i# j8 {7 O
1620350 ASDA EDIT_OPERATIONS Pin number is lost on updating the version of a connector pin
5 Z2 K/ K% Z- s+ `& H# m& m) ?1621963 ASDA SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected; ?4 p0 s2 ~4 Y$ o( E1 B9 G
1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting an XNet crashes DE-HDL, @3 l& r" w% a$ L9 x0 m7 F
1625209 ASDA IMPORT_PCB File Import from PCB Editor shows board differences
/ B& F6 k7 C6 Z; u
4 B1 e' s1 n) T
& t$ O @' G2 R' jFixed CCRs: SPB 17.2 HF003
* ?5 ]: g" h; i1 r" M! v; X07-28-2016+ T* k7 S N* \6 l9 a: e
=================================================================================================================================== B; Y0 z$ O5 y c' v& o; m6 z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 ]5 ~) v; j3 x' Z/ W. ~===================================================================================================================================
+ W' ~% @) f& i" R+ R1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result Z2 t! S! s; u# m7 b* O
1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ' `" p. H: `& [. t- k) n) x3 L
1472456 CONCEPT_HDL CORE The design connectivity (XCON) file and design data are not in sync! [6 |) {- Q/ J
1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears$ {$ |# h4 m2 ]2 L
1547356 ALLEGRO_EDITOR EDIT_ETCH AiDT gives different results in ISR S034 and S0665 O. a9 T. m6 e- V8 }* A, x
1560102 ADW FLOW_MGR Flow Manager: None of the eval commands working- `1 |7 g( k; Q6 y- F5 B' M
1570032 ALLEGRO_EDITOR GRAPHICS 3D Viewer shows flat LED for a specific design5 {1 W: h6 O3 y/ A: s" k$ r4 o
1574676 ORBITIO ALLEGRO_SIP_IF Updating the OrbitIO database with a modified .sip file gives errors& L0 R1 }# G. k# s6 B
1578876 ADW ADWSERVER Component Browser crashes when trying to show details of a part number1 O' n6 F6 G3 |0 A, m, @5 L
1580744 F2B PACKAGERXL Running Export Physical results in error SPCODD-114
9 r4 M$ Y0 s% K% }7 @+ D3 f1582863 CONCEPT_HDL CORE Generate View creates non-existent ports' N& r' U* Q+ B3 V8 V
1584317 CONCEPT_HDL CORE Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully; d. O* w0 O! I% I9 @( B( I4 _
1587018 ADW FLOW_MGR User is prompted to specify the flow name each time the project is updated( }7 Y6 ~4 {$ e" {% m7 R% ^4 Q
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
. U/ I- }/ V) [) B$ V8 y1587498 CONCEPT_HDL INTERFACE_DESIGN Need the ability to tap individual bus bits
1 U$ G! X8 a5 D$ {1587718 ADW LIBIMPORT Library Import - The Pre-analyze tool does not report errors2 [' x c( U- a. j) Z
1588197 ALLEGRO_EDITOR INTERFACES STEP export fails when External copper is selected on Windows 10
! t; g7 N5 n: _& F' b% w, d, ~1588786 ALLEGRO_EDITOR OTHER strip_design reports 'Design has been corrupted'
. Y) z# a, h; r9 E" s4 V/ G. P1 \. ]1589252 CONCEPT_HDL CORE Search results zoom into the page origin instead of the selected components
: P4 j* p: U2 ?. J" o1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC reported between embedded pin and via which do not share layers& ?/ \4 }4 f" u) C8 U$ j
1589979 ADW FLOW_MGR Design Name change does not reflect in Flow Manager in the same session of a project
; S8 m* ?* Q* l9 Z- X y1590538 CONCEPT_HDL DOC Open Archive: Some observations on the random behavior
0 s/ T5 g; |6 \3 o" x1590639 CONCEPT_HDL OTHER Importing a design in DE-HDL results in a crash
) A3 B3 d7 T4 h Y$ {1590651 CONCEPT_HDL INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager
, e3 Q* o8 U$ @& v' Q8 ~6 h1590720 ALLEGRO_EDITOR INTERFACES Exported Text Size Parameter file does not load names into the text table9 I: w6 S0 x5 m0 [5 m( [
1591070 PSPICE PROBE PSpice crashes when using the Trace - Measurements - Evaluate command3 y/ H$ J& J f4 x( Z! ^
1591223 CONCEPT_HDL CORE Variant information for lower-level schematic not displayed
# D, s1 g. q' y3 T: c: V; P' C1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived
" I! T8 C- w+ k1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when you create a new pad1 X1 J5 N' e$ L3 m/ w5 Q7 L j
1596615 ADW DBEDITOR Unable to search parts: Component Browser did not launch; Database Editor did not return search results
" P& k! j+ T7 w/ W1 ^( V- w+ C& }1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
: q1 X8 p2 R, q: d1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor3 j4 ]4 o. V/ G! y. h, b
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI% j7 H7 S- {1 X& w2 K5 p
1598629 F2B PACKAGERXL Export Physical crashes after flagging error SPCOPK-14588 O2 w" f' }( q3 ~ ^
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork with Mirror option does not import pins or shapes
; P. ^3 P# H5 j2 _& z. c1599744 ADW FLOW_MGR Flow Manager: Commands associated with some of the buttons not working
9 n( Q; o, p6 B& u2 ]1 f1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
5 G) @" _2 y( S0 ~7 a2 V2 H8 Q1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
/ g* X0 O7 e+ V; d% c1600618 ALLEGRO_EDITOR DRC_CONSTR Casing of property names is affecting results when working with Physical Constraint Set3 ~! |& y0 N& `# K& `" h* r3 I) I0 c6 E
1600914 ALLEGRO_EDITOR INTERFACES Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option
) f' y+ W8 T8 \, g B0 i1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad
/ S% m% F# t8 q1 j; w+ V1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
/ H) U) o# v/ k0 L0 T2 d K1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.4 O( T. F$ C9 K5 {: j* L" B
1602514 PCB_LIBRARIAN METADATA References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project
/ v0 S8 J/ {7 F4 S! {1602823 SIP_LAYOUT WIREBOND SiP crashes when using the Add Wire command/ W, l* H/ [1 S k2 e# P
1602955 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC not reported for attached database
9 |8 e+ C2 z; ?6 M- [1604223 CONCEPT_HDL CORE Tool stops responding after error SPCOCD-553: Connectivity Server Error) T6 s0 P$ R; Y
1604746 ALLEGRO_EDITOR OTHER In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools/ J9 [0 O6 ?% m5 F/ U9 o' ]/ J
1605322 ALLEGRO_EDITOR TECHFILE Generating tech file in 17.2 takes much longer as compared to 16.6
- x; S3 @4 f1 D4 s! B' W J' r' N& P2 U3 R" H' w+ m
* y% `0 p9 t4 @) |4 N9 A/ DFixed CCRs: SPB 17.2 HF002
; C" m- \* n6 F( }$ q% o- K4 E0 V06-31-2016
7 Z/ l$ H( g; h b===================================================================================================================================
$ C3 f: R, |1 r7 R( g0 \CCRID PRODUCT PRODUCTLEVEL2 TITLE; ?0 q( l. u9 k; a( w \ ]
===================================================================================================================================" E/ c' _; g1 ^
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets* G0 h* w- r! ^
1469146 ADW LRM Packaging error reported after updating the design using LRM/ m+ V2 @( g1 O$ |/ g* h
1481802 ORBITIO ALLEGRO_SIP_IF Import of an OrbitIO file to an existing SiP file offsets the results incorrectly
0 a$ x8 u O: t7 [" Y4 ^' p1518957 APD SHAPE Shape void result incorrect& w) K/ s2 e' d( l1 j# Q
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
5 Q5 O0 w! r: X/ o1524947 SIG_INTEGRITY SIGNOISE Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.
3 i4 [* [- `8 v( _( B# }* t1 f/ O1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.: |0 M) B) u, z* ]
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in the attached design.
, A$ H( H0 x% _1544675 ALLEGRO_EDITOR OTHER Export Libraries corrupts symbols if paths do not include the current directory (.)5 V* f. W( i( l% k& ~
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Show warning message if differential pairs are created for nets with voltage properties- H* K' z: L5 Y. R
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
}2 n7 U" I8 X. K1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library8 v* l$ E0 }/ d5 f: G& A; s
1555009 CONCEPT_HDL INTERFACE_DESIGN Unable to rename a NetGroup.
j2 u% C! N) v1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets7 D: z- D7 w8 d, c1 m8 B# o$ p
1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation
9 W5 X) ~/ D* ~ [5 T( H7 \; E% d1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
2 G1 d- b( R- d* P( u1 b7 v1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
- ]% N! i1 w! Y9 @4 H' V$ R1561501 ORBITIO OTHER OrbitIO stops responding when refreshing a design in SiP Layout* a' ~+ Z$ `* c4 r
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
3 b( ^2 K+ ]; p% v1 v1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
0 C4 G. K$ Y1 ~% I' y' s2 ?4 F; b1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas/ M, U2 A* b' V; l5 y1 u* i9 _
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions N, u9 ^3 ^. D6 l' o4 x& T
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete4 n1 H/ p& m7 X1 f: ?# }
1566942 ASDA MISCELLANEOUS Several extra files in the /tmp/ folder on Linux
1 \9 u: `' |4 O' L5 b ^7 l$ ^1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.! Y3 H' @! a# B5 m$ F, ]3 R& t
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct4 Z9 V4 S7 P7 M( k. X" V
1569056 CONCEPT_HDL CORE Opening the same drawing in multiple cascading windows view displays non-existent artifacts
& w( F9 \0 ]+ W0 X2 P( ^! p1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'8 _- a/ q- O2 E) ^
1569147 CONCEPT_HDL CORE The signal name auto-complete drop-down list is not displayed correctly2 Z( X i" A u/ ~# j7 u5 i3 }
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2
( z% X- r' Y# e1569924 CONCEPT_HDL CHECKPLUS Checking in a large BGA into ADW results in an error related to negative signals* W* N4 H7 n1 b# B
1570398 SIP_LAYOUT DATABASE Diestack layers cannot be deleted if there are unplaced symbols in the design7 s; Z# r3 s. [# X; A2 y
1570419 CONSTRAINT_MGR CONCEPT_HDL Need to add a customized worksheet custom property weblink in Constraint Manager
, K; ^7 v8 ?. t' |9 ~& r1 g3 ~1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short. S" [8 }( E! j4 g4 {' W
1570678 F2B DESIGNVARI Variant Editor: Error when adding an RSTATE property) U- j, a8 F0 h9 P* j* d$ B4 x$ ?
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
" E$ o8 j1 x8 D: m% a7 O1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display' v; Q7 o- b: l! g# D# O
1573127 CONCEPT_HDL COPY_PROJECT The CopyProject functionality creates an incorrect 'view_pcb' directive value3 p+ S0 ]# f9 F8 u' _& v8 B ?, {
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
# \) X4 K+ ?1 Z% g& b1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2
7 u# e# A/ \% i/ v! i1 n K9 E1573755 ALLEGRO_EDITOR CROSS_SECTION Changing a layer's type is also changing its material in Cross Section Editor. j, p8 k5 J$ W+ R
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the project CPM.arch file
5 x1 @) T0 @; [& n0 n2 Z1574381 CONCEPT_HDL OTHER Packager crashes on repackaging a design with RefDes related advanced settings
- I% n& U& H* [9 Q5 t V# U1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'6 ^" I7 q% y8 ]; L% a! d9 S& |
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure! j3 F/ t$ D Z$ M" o
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
- K4 A! s4 t/ u8 v' H0 b6 Y4 q) O1580891 SCM REPORTS Dsreportgen crashes in different scenarios J4 R$ ?' J1 X. ]$ Y. M# B7 B: G
1581254 SIP_LAYOUT CROSS_SECTION Cross Section Editor crashes when adding a layer
4 `8 Q2 A' J( j' Y# L( L4 q5 `1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error: m: W* T6 v. P' L& h
1588823 ADW FLOW_MGR Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool: D* D2 |8 T' F }- {( |
1590064 ADW LRM Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.24 {$ K" s: H Y3 W4 k) p8 ^
. \7 Y* B- ^& R, \& e
: s$ R. P% X! q) ^7 qFixed CCRs: SPB 17.2 HF001
3 X# A. D1 P" Q' ^& X05-06-2016: V) N% [% ~0 @, `3 T
===================================================================================================================================
2 A- j) c; ?/ u$ q' K" @CCRID PRODUCT PRODUCTLEVEL2 TITLE, o9 {4 R" R5 B
===================================================================================================================================( t; W. s8 \ }/ _/ M6 D! L( V
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
9 x+ N0 T# J3 B1 |! ], @1 }) y1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
S" h2 X" R% B/ |* A1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
6 v6 {6 V0 U! R5 \6 _/ X1 f1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
! m# y, ~" j+ G, T$ O4 E' `1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol9 c3 m4 B2 i$ o& i- Z# v
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser1 u3 ]4 D4 M; W/ p+ h, F3 l$ C
1506672 ALLEGRO_EDITOR INTERACTIV In the attached board file, when using Replicate Place, some shapes are missing from some layers
6 Z, [# |# G: ^! l( d9 v0 S1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
6 V- A; o$ a# J2 H2 ?+ i1523532 F2B PACKAGERXL Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute
) X; {0 u7 w) G, l9 @. E1525783 CONCEPT_HDL CORE '\BASE' scope does not work for SYNONYMed global signals
$ Z! l; C5 D' ^, O, v1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes
+ O% x- \; ~# A1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
! B2 Y5 E$ [9 D X& x8 m( ~1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed' M6 M3 t& R1 l
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.+ ^/ y9 H4 ~+ }3 l, s l" _
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
; n2 R/ u$ }$ V3 g. o: K1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols: T8 B+ |- J2 t, b- x7 n
1543410 ADW LRM LRM shows confusing part status; reports that update is needed but clicking update does not work
" E4 \6 k7 L9 o1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
) _' f; r* B' F Q6 ^6 U1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
* p7 [3 a5 x& f" {, _1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
/ K9 u" H3 r$ ]6 e1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork J( d, d% R+ d
1546877 CONCEPT_HDL CORE Align Left on wires fails with incorrect error message
, v( v5 d) G, X- y1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
4 B0 m' Q% @, @6 [3 D# g1547584 SIP_LAYOUT OTHER SiP - Design Variant: Delete embedded layer if not selected
1 Z7 ~* G* O! P! `1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol0 Q& y9 Y! C2 f: i1 A$ v$ A
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
8 C# l7 M3 j6 H7 `$ A1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report- b& L6 p$ ?) M1 h6 b
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines7 |- v" G {- e% C& b T
1549662 ALLEGRO_EDITOR OTHER Import Parameters Path fails if parampath does not have the current directory (.) set
' J% f7 [& t9 C. s% }1549836 CONCEPT_HDL CORE Tools - Customize - Keys - Reset does not reset keyboard shortcuts% K- p' t8 F9 `) d( W
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems& O* w6 R1 t6 r: y% J9 N
1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to Hole DRC between via and pin not shown
: K+ ?- D! M w q; M' X( ^8 a$ u1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl(pixel2UserUnits) crashes PCB Editor# z: M1 E6 O& s' o6 ]% C
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to NetGroups
* H- ^ R- X# f# p1555092 SIP_LAYOUT DEGASSING Degas offset is not working with hexagons
; \) w7 c( @, K& E7 T) K) K9 {1556261 ALLEGRO_EDITOR DATABASE DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'1 Z D. @. p6 v' L% M+ b7 T
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted0 J2 T6 ~" Y% T/ u2 h+ F
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die0 v1 w: {3 D- C! R6 A
1560197 CONCEPT_HDL CORE BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM
, e) Q/ g# d- Z7 y' \1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
0 p' e6 C* G" {& D5 A1562537 ALLEGRO_EDITOR MENTOR Using mbs2brd in 16.6 gives a fatal error
1 z; F! u5 \( j/ X& t! {+ Y: Q F# \1564203 ALLEGRO_EDITOR ARTWORK Cannot generate negative artwork) K) R0 w( P* Z% V7 A# f! E' f i
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发表于 2019-11-5 13:54
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