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DATE: 05-28-2016 HOTFIX VERSION: 071- P( @$ j* C/ \! g+ Y% G4 d. t: H
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7 T; H' f% H ]8 } w" r1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets4 x* _! A9 c% S, q& ^& J" U1 d
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package" T, q4 J6 u7 T; }8 U
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
$ }1 _# r9 X# E" d0 j* t: p* z% Q1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
+ U! L$ h/ W( H" Z2 ^1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.7 b+ w0 d5 U' G6 m9 G
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.' P: Y' R. x5 Q* l" U
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.). J# b2 B( o2 o* m/ v7 a
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set1 [! r5 m+ l' l5 G, H
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'% y& k) R8 R- P7 J8 ^
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
9 D. h# s9 y8 q/ P- \, g9 Q1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
8 d9 }3 m4 a7 B9 V' A% o- t8 d1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
/ w N; ?" D% G1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
; K; O1 z, q$ O$ h* u& Q0 I0 U2 p1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open* q, O5 e5 L3 t% L" g% X
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
8 H4 n8 m$ c' }9 h9 [. b: |1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC5 U2 F( E+ ~; P! W& S! Y/ Q* [
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
4 }4 G% S4 y% G% e! n1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
, t4 [6 m; h) X3 R1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
& p' u W- n1 n- \! w* I( X% w( `1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete5 L+ `8 v6 N- `& c
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
, m+ e8 C% @( \4 d' L: y7 M1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
0 ^( j y5 C+ C3 ]1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
, E9 N5 n: l* K" D! A$ i1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
+ ?: B! W6 p( x2 }# m6 a+ [1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed+ Z. R; [$ ^9 [) K/ Z w, Y1 [
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
' q2 ]8 z* ~0 h0 M5 Z) T1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
/ F) H) U3 V5 e- [1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
% z6 k! s( W0 i; ^3 Z' g( _1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
, c, u, ?( P- L! }9 `3 U8 Z1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
; l1 y; o4 Z# W/ P1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
) P5 V# r& m) t) |) |' ]# m1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
0 ?& K0 o1 m" y# Z- [2 a1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
4 @; c: b! X$ V- f" r: d1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
+ k5 E, i0 ]% Z0 |# ]( q6 Y1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
9 Z2 @7 O$ s4 ~3 y- p I1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
. K( Y8 R# m6 `
+ E# I# I5 E$ J7 d1 RDATE: 04-22-2016 HOTFIX VERSION: 069
4 @0 U# D" N: X& g===================================================================================================================================
8 O3 p, ^" f7 |CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 {/ G1 Z) y) ^$ o" A5 H===================================================================================================================================) A* Y* T3 F1 X/ M+ I
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
/ ?( P; G# l( y+ w& Z% |& N1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
! s7 N7 o$ }8 L0 h6 |+ W1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail1 ]5 C3 U+ m4 q# S* t* d3 a
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol* p9 y8 P: v- V+ ?" d: m4 [5 b( I6 q( y. _
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing2 A4 X+ O& T. {7 g% V6 L
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute8 J) M' H+ {! Z! _
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals+ A$ y$ |: Y4 Q
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
3 o% g* n0 h! x+ | S1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed4 U* p1 f" g* r: E; b p$ T
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
4 g( \: m4 L$ R Y" C4 _2 V0 @1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work4 S4 @ \* k6 b2 X$ s2 d/ ]0 W
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
+ P4 `0 J& o6 u- q& g2 \$ y1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
8 j" J h4 g% A8 U1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point6 ^; o' M( W& L) ]) K: ~
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines9 K& q+ `* H# ^: l" P- c
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems7 P/ a5 \/ s5 n
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
5 W5 {: y% r4 b8 x1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
6 u1 p: `# b! [* d" I1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
7 c4 C( S) m! y% \' {" [0 M1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes5 c3 c7 t7 q# u; W
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted, k, ^1 ^: K/ v2 M4 F* @) Y
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die, G# o; x* x) }- b* ^( v% |5 Q! r: M
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
; ` v. R4 v4 G# |/ L% n$ j1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error3 p& H3 ~; k5 t' Q" [- I1 a1 Y! l
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film./ @# l% O2 X- |8 ]" h4 D
, k! c+ I6 z- P3 p) }. fDATE: 03-23-2016 HOTFIX VERSION: 0687 ^; M j7 |) Y6 s; m' T
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 U8 F# p6 Y) \* Q===================================================================================================================================
- e4 e+ @. d# Z: S% e* p) t1 b4 S; C1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
7 G( }+ O, [6 I: {8 @0 W1 g1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file5 S/ f( B: h0 r4 X
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license! `4 J, I X( ^0 Q4 k: g
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
6 E. d, Q& A4 x7 {; ^6 T1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system. c% d0 C# s, ?0 Y
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
2 `: x) L, |0 U' w3 X) E" G1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol8 Z }3 Y; H- s, Q8 a; j: m
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file- K. l" ^5 T$ Q" Y; V3 I
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report& e; f/ z8 |/ O
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'0 x. ], _$ d; P+ }' f* L, Q t
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .6 q: @3 G0 y/ H9 c3 C3 F8 L- [
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
9 T+ p& I. q2 m1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols2 g0 ?/ r5 k. i2 B- ?1 ~
5 n4 A9 j# V. [$ I. {- ?' iDATE: 03-11-2016 HOTFIX VERSION: 067
2 w, G: q, U7 r" t===================================================================================================================================( x4 C$ D; I) l# c
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: R3 m/ H6 \$ E8 \9 r v, l===================================================================================================================================5 A7 @. Z1 H3 L1 p
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
/ d' m$ |/ Z9 E. v) U$ ~4 E- R* Y1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
8 g( V& g9 m/ z& [- C1 S3 z X1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error7 e! z' N% Y( b: G) ~" P% E
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
- J0 G$ L5 S% V2 n3 Y1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property7 \$ [+ g# w2 ], i0 ]+ Q3 o! p5 Y/ ^
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
1 ?1 G- a' m( K( Z6 D" {1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
* C9 V& L1 R) k. h4 i1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes' v c: F/ z: _& k( B
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
6 q: o; R1 d& j8 u2 j: x1 q1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
! S4 j/ k; v, ? I9 E& t& v1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
# L: P" f" Z" S1 Y# y1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
' s% y7 P0 D4 { e0 c1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer9 X% i8 n A- z1 Q z+ Y- k
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net6 v" K8 C. z2 H8 r1 ]: y
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
D: F4 [' o- ?' q1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.! a( X- Y9 T: g1 N. \8 ~" n4 f
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error( t9 @, }) g" ]! C9 D4 ]
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.$ Z* t% z7 l6 r8 i* K& u
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
3 t$ B4 }& b7 W- H$ v; d; X- O2 \1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines! A6 `, U5 y1 U9 A
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols* M3 W/ j2 ]& S2 n6 g) C
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board6 y2 B0 R' y1 i/ R1 E$ U8 f
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
$ x; C2 \9 |- j: V' X, R7 Q1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash Z" f, ?+ B; Y& Q
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
! k. O/ t5 T1 T3 \' ]& w9 v1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
. C* Y) s5 I; D8 j7 _1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with9 g4 @/ A3 s! L4 g4 ^
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design; y/ c4 G2 r2 x! {# M# L
. k: [# r8 y# {1 R* |2 f* F9 ZDATE: 02-26-2016 HOTFIX VERSION: 0669 ^5 {2 o1 B5 `( T
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===================================================================================================================================
8 L' |7 ^1 ^$ N3 ]2 W+ `1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
& m4 g% D) P5 ~4 i# @1 Q1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
* f! r1 S/ }# H( A: j' v1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions% ?" O; b9 }3 _ [# h( E
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
: g( ~; Q2 C: D& g- b2 T1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
H/ E6 W3 ]2 n' {1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue Q; I: n* S) r$ k; w5 \, f
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer/ _ h' M3 ~+ g! |$ o2 f, a; F
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
* U7 K9 `% y% O4 ~2 l8 `- v1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run# h. C T) V# z% W3 M' s( }( ?
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
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0 m m5 a$ C- J! _DATE: 02-12-2016 HOTFIX VERSION: 065
2 ]* o7 ^3 e3 U! C% U0 e===================================================================================================================================
' q: ^+ T& _" T+ V; d% OCCRID PRODUCT PRODUCTLEVEL2 TITLE% r1 I2 [3 s- Y+ s: }
===================================================================================================================================0 A6 \+ Y7 b/ q* s* R
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
6 V: q' Z! U W: M4 F2 d! [( \1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
: e: @; S0 [& Y: ]1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit5 v! ?! b1 a0 D2 s1 S2 W; v8 ^
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.( |4 _9 R. e p7 H0 Q6 r
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
# f6 p, d- L( M, m) Z/ R1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
8 t1 g; Y. G- a5 C8 g3 S' f3 g1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger+ l9 I% u. s K1 }: g. V
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
5 N0 l. i- p# H* L1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
+ t& k* o* x/ Z/ H$ K1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.7 F3 `* E4 G2 V5 E9 E/ H8 h
. K- `5 Q! U. s4 m. o
DATE: 01-29-2016 HOTFIX VERSION: 064
+ M; U" |5 r/ E% m===================================================================================================================================0 [) W, V+ ^& ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE, b1 I, u* H7 J- @6 l; j
===================================================================================================================================
8 F6 q) [* x5 @! [8 o1 n' |3 O- j1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain l5 y* |! u7 Z* k6 Y6 S8 J, n6 X. n7 j
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF) w* S& s2 u; X% D* g4 N; ~- u
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.) Q S6 H2 f. T- G9 T
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected. U* i2 G# t H4 O
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer." h3 v7 ]! K' V; Z- a0 y, d+ V, H
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default% t! L6 W- ^# m& a! c: w1 p
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas; n' g) g. ]6 c; T: g. p% l5 Q
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net( Y% L# V/ F( m" U5 Y5 i
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
8 Q' ^9 h+ {5 {6 @ V% u1 S; A4 r1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
: `7 r, {/ L% u7 o" l4 [1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor4 a! \! R' z6 b
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)
% y& B) k0 k/ Z6 I8 N1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design' F% ?$ [: r8 {: j+ Q/ _/ k
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
6 z5 S# P8 U1 R' m1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
) b; q' n: j% v. S- |1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
5 v: s1 R f. M6 \1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct: O) F2 M( P! {" R6 X
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
$ k- X0 Y% o m/ l" K3 G1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
; w7 y, ^ D* w: C+ c
5 _+ z$ M0 f& r# i/ e7 qDATE: 01-15-2016 HOTFIX VERSION: 0630 d- ]+ Y/ Z: I2 u1 ]) \* i6 T
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CCRID PRODUCT PRODUCTLEVEL2 TITLE" R( {3 Z' a& m' L
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
7 j" ^6 u! [. L0 `1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
4 \# _3 c# }* D+ X( R1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
/ D0 Q, {/ [/ Z* D% n1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant* `; b+ }4 B1 `* I. F h3 @
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
; {/ n0 a- U& L' \1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6! t O3 B, u) Q
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
; X6 j3 f0 W' Z. n0 p J1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command., E" m0 ?' E4 z" X- [! P7 c$ \
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.1 H' J1 g3 r$ Q! k
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out k% v5 d/ t1 D! q$ q0 [8 ~9 i" ^* v
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
~/ { l9 h* g, f/ I T: u1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
. f+ C% |! p7 Q, @- T3 R( b1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly( l5 h3 T" H, M) [
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
5 N, z' h" q5 b4 |, b7 Q8 [7 B) M1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
- q% R8 \ C" x3 }; Y9 [0 ^1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'4 t" Q- |; N% @! C+ D/ ~
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes7 d Y# g) ~- @9 p9 ?0 G
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols5 v( C+ i; [" S- k7 ~3 @& j
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
, W P# U5 Y9 n1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
6 o! Z2 ~# a( P1 P7 [
) t% y6 b: p' z! MDATE: 12-11-2015 HOTFIX VERSION: 062
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# |3 b7 C+ T$ _+ R6 b- NCCRID PRODUCT PRODUCTLEVEL2 TITLE
# D6 \: O$ q2 E, q9 }===================================================================================================================================+ r1 Q. K2 A) ?/ ~7 k0 T2 V& [
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
& B1 }4 L/ Z& j( S% a% r1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
; e5 S$ R M# m4 j. n1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
! K# r; f9 B$ z( a0 j5 {. W5 B, d1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
% U1 O/ |2 h4 o& G1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
; h9 W" {' S/ K' k1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked# G2 O. l3 A- I8 @5 j* J5 p
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
" }2 [ l n; `/ v0 y1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
+ d0 T$ Z' T: f1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
" L) a* i& P5 O% w! n1490311 SCM OTHER Block Packaging reports duplication when it should not! a% N8 G( d* ?! u5 M' w
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
8 V- \ }9 g) ~% k0 ^0 p1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message4 p. @& [- n- _' q: z- O
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)/ L6 _# ], Z+ h9 u! R" j8 ^& j1 ^" Z
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
7 O: f/ d& T3 O" O! `5 S1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout* y) f$ l. X7 K5 b1 C2 ^1 d
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
m- l! I2 m: _9 ?; I% N1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types: v9 t: _- J2 m- k% k
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
3 m" K# }, r! Y* }8 K1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly3 w$ Z, S, h0 |' C
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
3 r# W+ h+ m3 u1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
$ f( _: o1 E$ g1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default' q/ R2 W$ z1 F+ b; N
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
! E" I- Z8 w% M0 D' f1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
- f3 @0 N. w5 s1 A/ s: X/ W1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out+ [6 q, U6 h% C0 a% E4 b
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF' d" o/ H: f$ V$ W* N
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form c) W& n5 ~0 s- h8 J+ g2 C6 @) n
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL3 M% r9 j2 j. P, ^
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings* k* w6 p/ T9 A, h$ {% }
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location; b- h- Q7 a. y" D+ C- H8 Z
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
9 W- ? t( s8 L! Z! p( Q, I' c* v1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
s7 T9 T( t8 s- i% O/ l9 H1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
: s" X4 t5 j" r6 Y2 ]) ^* b1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
2 \& C# a* J9 t5 O& i9 M8 e1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving: ]. Z% Q, K ?+ u
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None* I& e. K% @) G3 p/ P% ~
6 i' c1 j7 n+ @% B5 `% ^8 `DATE: 11-20-2015 HOTFIX VERSION: 061 l7 X) x0 b6 }$ J; t- c' K+ \) M5 M
===================================================================================================================================, [- p! T0 P, Y2 J- t2 k
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; L, M# |; U- t) O5 j% F* r===================================================================================================================================
* C. k/ Q6 u8 h& X8 l7 R5 I% H1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
c, U$ M' p L3 }, @+ \' V" i% u# r1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
$ I1 o( `, \5 S8 z1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only4 n4 g7 y: h9 e# X/ _
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
5 R5 H5 |+ G: p/ ?4 H% l1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins$ _+ Q' @# U. F6 _* U8 H$ k
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set- {+ l \6 ]/ o, f
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
8 D. I. `7 q ^0 V; W1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools% h. q3 V4 F. Y$ O; i4 H4 s
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
, i$ c5 f- x0 `% g- D3 @1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
9 E+ F7 n- l0 C, r1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL; S9 o: z- |* U# q' M6 Q, R
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
) ?2 J- m @* R1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable- t+ T1 K6 ]5 N7 @* L9 d
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets: F- C$ e/ n% W) u# A6 l1 ?& b8 }
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
- w3 U" D4 w0 _2 N7 _1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
# q6 U2 E) r; V/ Y; M5 D1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only0 d3 J' D0 z1 ], L/ I+ s
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
# a. h, D4 ^/ O, }7 Z! n& V1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.& B' l) y, M6 H5 c$ c8 S* Q
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
7 y% m7 q* x1 k& f1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
r f& a! `. p1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported7 a' j4 K. v k$ F9 G0 @5 }
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior7 O4 j5 t* F1 ]5 Z( D# t
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board% f: S$ x7 i( n1 X' a& H
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
* S, y ~7 \) n' \" Y. V* F1490299 SCM OTHER ASA does not update revision properly
3 F4 T9 p4 g- [4 a |3 X" p1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer( ]7 ^% i; ?% r
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints, w: Q; N% y, m. R$ R+ d( Z
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working7 _4 r3 s7 y) N4 L# s: V4 N
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong; F/ o, b0 C6 z
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash6 L9 P; O7 g" x* e0 |: G( Z0 ?: w
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL2 ~1 t v8 |% E3 v" x) V
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581+ q+ y0 ~( X2 I
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size7 Q- H* \2 x7 s" W o q& s' P
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
5 z7 [2 K) C* k. a; [1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file% O7 q3 U# B+ Q2 E- X: S2 M
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05