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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the9 O" `, a0 P6 W2 T- m; Y6 I
speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.
8 u* s: c9 y( CTo avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally/ s& [. G. c& z5 M Z% c% E
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.4 w$ k0 t6 j9 S7 d5 O; Z( c9 y
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in
) h$ g; S. I5 M* k" B# Y, xthe cache. |
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