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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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{:soso_e102:} 6 A! f) o# l0 ^* J" q" f
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DATE: 05-24-2013 HOTFIX VERSION: 010 v3 U# `1 V; y6 Z: m
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7 D ], B6 A6 X: U3 T. v' WCCRID PRODUCT PRODUCTLEVEL2 TITLE
' {% b7 `1 d2 y2 ?===================================================================================================================================
" F. y' ~/ q, z( U: {/ R3 F4 O0 i1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer( Y+ v5 f5 C7 ^/ r' [& C
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
+ B2 f1 l3 Z; v0 |, k1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
, o4 ~+ R) y; o! {3 X6 h, O1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor0 Q' {$ F1 t* p
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6' y& f- t8 t. x0 n7 U! O
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
5 P S( {( k6 y+ a4 D1131775 ADW LRM LRM error with local libs & TDA
5 u4 A8 _ _. e. H9 f7 I* I* S2 W4 h1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
6 s" S5 i, I/ X1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo9 ^2 i0 e0 t9 {# C
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.! \$ |! }4 D0 b5 L s* I% o$ ~3 N
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
$ p/ F; X' |: k! D7 Y7 v4 J1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
4 T8 I- } k# l/ b! [" r1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
& N8 W1 a/ ]/ {* `0 O+ l( C1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
% C/ s6 U1 O$ Z- Y* r1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
: l) J- E D/ w' W( N% \3 h3 ^1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.4 N0 W u' Q+ L
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
! j& n% A/ {, X% F9 [. j- V1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash$ q3 R8 g) ?7 Q8 ]( p2 N& t0 [
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
7 ~. N0 @0 c1 I$ B' i: u; f1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering% x9 u. U* j6 R2 p" A* [2 x7 T. h
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
