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Hyperlnyx中仿真，U1芯片为XCZU11EG-2FFVC1760E，4 w" P0 J y y' e
使用IBIS模型为zynquplus.ibs7 T! D( ] Z4 H' h/ w& v: n1 t- b" N
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[IBIS ver] 5.1
( q/ H/ J4 c3 U" G! x! C[File name] zynquplus.ibs0 I( D6 T# b, @! o5 s& G9 \& S8 S
[File Rev] 1.12
& c, ], q1 L" j7 X" ]8 N[Date] 22-MARCH-20187 j H# ^/ p% x( i$ n
[Source] Derived from spice models, rev1.0, using
; }3 F3 q5 g' Z hspice 2014.09-SP1-2
' D# v; |6 X: i7 X[Notes] Xilinx IBIS file for Zynq UltraScale Plus I/O standards.
# D3 ]7 c, V8 {" o, P All models are preliminary., f; r" u/ @; P0 ?6 U
The version of IBISCHK used is ibischk5 V6.0.1.
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7 l' f* E# Z: _+ f5 C[Disclaimer] The data in this file is derived from SPICE simulations using$ K% S8 P3 |- b+ V; D2 k8 }# A& r
modeling information extracted from the target process. While
z4 K/ q9 t$ v+ r9 ~ a great deal of care has been taken to provide information
* ] J3 k* `+ [ that is accurate, this model is considered preliminary as it
- a+ q7 O# @% K has not been verified by actual silicon measurement. Treat the
2 b' q: w+ g6 V data in this model as preliminary until actual silicon
$ q# R9 V) \+ R( U1 T verification is peRFormed.
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[Copyright] Copyright 2016, Xilinx Inc., All rights reserved. x5 I7 S- ~9 b0 ^8 O( l& y
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仿真的时候报错如图，请问各位朋友这个该怎么解决啊？
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发表于 2018-10-18 12:42
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