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2020-1-14 15:59 |
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发表于 2007-12-18 21:50
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The biggest problem with asynchronous resets is that they are asynchronous, both at the: z! Q9 {1 T o+ W4 z( i- }1 P" G
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the1 M& y6 f$ N( l5 ~8 n" J4 M5 `
issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
) N: y9 r: N1 z( poutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
! Z6 B6 U( M% ~7 AAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
7 ]- v$ J- B# S3 e4 k' P! K2 Idue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
$ j* p# } s- C g" V6 b& P9 kreset glitches. If this is a real problem in a system, then one might think that using synchronous
: j, t4 I; O/ [9 m( rresets is the solution. A different but similar problem exists for synchronous resets if these
" r; i1 b3 Z4 ^- Ospurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
; g3 ]: w" S5 b ?8 r$ }true of any data input that violates setup requirements). |
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发表于 2007-12-18 21:19
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