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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294$ ~! k. x! B: o* S
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DATE: 05-24-2013 HOTFIX VERSION: 0105 l0 B3 b* L9 {# Y' Y q" U
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7 \ s# {6 d% I, a! }1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer5 y' |: f6 n _" l
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border: b. x6 @; ~% y0 o# P
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files! W$ Y' I; l& |! A; l& o0 k
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor1 @4 R9 l! h( u9 n0 \: @% J+ y
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.61 h0 g; P$ U. x( n' T ~, i: @5 U
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
& ]2 {% M5 E/ v% R/ w2 \1131775 ADW LRM LRM error with local libs & TDA, o" q9 P1 P0 k' C# R0 k
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4' H8 E0 K! F$ T) x% j
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
! g5 N `+ {. ^+ F2 P8 N1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
( q4 J g6 Y! {+ M$ i3 p& P1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
$ q' e: `: ^! f, |+ Z7 e$ v# K2 T6 `1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
R8 h, G- G! n3 h6 h9 z1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
1 i/ g1 `6 Y3 m5 _1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor* ^) N7 r4 f) O
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
; U' a2 H7 v8 ~3 i1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.( ?, O* b+ K. `" F8 i
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.. l7 p2 U/ W8 V+ A1 I
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash/ h' T0 R( w+ W4 @9 R0 N5 `- s3 W4 d
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
7 h" j2 r/ T/ `6 u3 N1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
7 }' Y h* E4 ]6 {4 k4 @1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
