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I2C START / STOP Detector Verilog Code
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: @- z$ _4 |6 R" m! E \module i2c_start_stop_detector (
1 G- U9 M3 u. @7 o9 d input wire clk, // 系統時鐘
: ]4 T( `' k5 Q& V% c input wire rst_n, // 非同步 Reset
6 s I: Q- O4 U- V. R! L { input wire sda, // I2C 資料線
2 q: n7 q6 p6 y1 H input wire scl, // I2C 時鐘線
* a4 t& T: ~7 P a2 p( r output reg start_detected, // Start 條件偵測到0 C3 W$ J S f. p
output reg stop_detected // Stop 條件偵測到
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// 前兩個時鐘週期的 SDA 與 SCL 值3 e2 Y* n: x% R- e# e$ C: k
reg sda_d1, sda_d2;$ [1 A4 K* M0 S
reg scl_d1;
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/ F. ?- f5 S: R6 |/ ?0 b wire sda_rising = (sda_d2 == 1'b0) && (sda_d1 == 1'b1);
2 |5 F$ r0 a' A% S- t0 ?! W wire sda_falling = (sda_d2 == 1'b1) && (sda_d1 == 1'b0);
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// Sample SDA and SCL
0 {, J+ D# a, Z5 S; O always @(posedge clk or negedge rst_n) begin
! C u! i" F, p. m4 \0 ] if (!rst_n) begin
8 ?1 H1 x8 l. N# e$ B sda_d1 <= 1'b1;
) e. a$ s' u2 w+ Q3 E- g1 c sda_d2 <= 1'b1;4 G6 t1 I/ b) v3 `
scl_d1 <= 1'b1;# O9 d' i, U) j7 \- t; p8 g4 G) p
end else begin; t. V6 t5 @1 B8 a# r
sda_d2 <= sda_d1;, s+ G d$ e7 H) @* [+ u
sda_d1 <= sda;% w& W! f3 p8 a
scl_d1 <= scl;4 _9 D5 @* U5 D% X
end
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6 w! {# P2 q' X4 I& B; A0 Y // 偵測 Start / Stop 條件% i/ M1 s: F$ }+ w1 p8 ?" [! T. ?4 D/ }
always @(posedge clk or negedge rst_n) begin
9 G3 j1 q5 r. a" N if (!rst_n) begin! {$ n- C! B/ y
start_detected <= 1'b0;. a' U7 Q- l) P3 | R8 L! C
stop_detected <= 1'b0;* W4 N. P T$ t; |
end else begin
$ _2 C2 P+ X2 t6 D // I2C START: SDA falling while SCL is high
" ^/ k* ?7 B8 E# {! {- \" G% r7 `5 M start_detected <= sda_falling && (scl_d1 == 1'b1);
5 ?* d! @4 r& V5 {' B6 K // I2C STOP: SDA rising while SCL is high
% y1 l% w0 x* V N" o* _ stop_detected <= sda_rising && (scl_d1 == 1'b1); h* m/ l/ f, Q* r
end! k6 v. D% c6 B9 m# N4 K/ D
end
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% c* Z. ~ j/ Mendmodule
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发表于 2025-7-3 16:34
发表于 2025-7-4 18:21
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