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16.6 的 hotfix 出現囉

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    奋斗
    2024-1-17 15:52
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    [LV.7]常住居民III

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    1#
    发表于 2012-12-17 12:49 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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    {:soso_e100:}
    : c0 z1 I" P( a+ k$ M& d16.6 的 hotfix 出現囉 ~~ 14 Dec 2012 SPB16.60.001, Version: SPB:Hotfix:16.60.001~wint   

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    参与人数 1贡献 -10 收起 理由
    pzt648485640 -10 很给力!

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    2#
    发表于 2012-12-17 14:46 | 只看该作者
    是不是16.6BUG多得受不了了?{:soso_e120:}

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    3#
    发表于 2012-12-17 14:48 | 只看该作者
    还在用16.5

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    4#
    发表于 2012-12-17 16:50 | 只看该作者
    期待这个hotfix

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    5#
    发表于 2012-12-17 17:52 | 只看该作者
    更新了神马

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    6#
    发表于 2012-12-17 18:18 | 只看该作者
    求链接

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    7#
    发表于 2012-12-17 20:05 | 只看该作者
    ASI也可以下载了,Allegro Sigrity SI

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    8#
    发表于 2012-12-17 21:13 | 只看该作者
    本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑
    4 o5 i. |* V3 e9 F- ^9 C- Y5 Z  {/ N) d4 C7 N) l2 m9 E+ ^
    别的地方找到的更新说明,其实干嘛老是跟着公司更新软件啊,我就觉得16.3挺好的,功能就很好了  P( K8 k/ ~6 {) R: e$ n
    DATE: 12-18-2012   HOTFIX VERSION: 001
    # M8 B: m, i5 b( @* T+ v===================================================================================================================================2 b5 o) J# J* }5 d# c) E
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE# O( J; R( _9 P1 `/ p  _, F9 [
    ===================================================================================================================================0 ~! R. p  v5 w
    501079  ALLEGRO_EDITOR MODULES          Enhancement for Module swap function similar to component swap
    ; q5 C/ W! f% Z745682  CONCEPT_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
    ; n' C; o/ j3 I% Z+ k825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
    1 y8 i' L+ C9 v8 }871886  CONCEPT_HDL    CORE             Browse button in Signal Integrity window of DE-HDL option causes program crash
    2 X( P! t# f# t891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
    - b$ }& ^  o+ |. o7 `4 a898029  CAPTURE        PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore2 W+ K; a# e) r9 @$ K" ]3 z' X& {
    923210  CONCEPT_HDL    CORE             Search with multiple properties does not show all properties0 ^' L: S3 @' N0 k: [
    938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
    ! y" k( q9 {/ Z' a2 J: P! ]/ ]4 i947451  ALLEGRO_EDITOR INTERACTIV       Allow the tool to select multiple shapes when assigning a net to more than one shape.) G. K  L7 ^( F* s8 ^
    968646  ALLEGRO_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
    # Q1 @1 s% Q' F' l2 U  Y976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor, M, w1 h/ v5 k1 e9 T
    981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
    8 V* d# o) X- t) ]# a& {/ s982273  SCM            OTHER            Package radio button is grayed out, s6 O6 ?% ]! w$ A% k/ i
    988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
    ! A6 z# G9 Z2 E# O* K989471  ALLEGRO_EDITOR INTERACTIV       Functionality to zoom to the selected object in Pre Select Mode
    + ]/ v4 y+ O# D" y9 a993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).0 N: t- ~* S; d7 ?# o
    996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
    : v, m* o$ j" Y# |9 f" `997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
    8 F9 |" o( l( p/ o1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model8 f& D, r& I) J
    1010124 PSPICE         SIMULATOR        Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
    . z8 `7 O" |  ]3 K) Z8 {1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
    2 ~5 c4 ]* ~/ S" ]6 C1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
    % o% G5 E8 p1 n# ?, i1 Y1016859 SCM            REPORTS          dsreportgen exits with %errorlevel%
    3 y8 }8 Q( b4 P  \$ e1 s1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin* }' q7 j' n! y& s
    1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs6 l1 S  f( u6 K% a# {* l- g
    1020798 SIP_LAYOUT     SHAPE            Shape not voiding on layer 2 causing shorts
    2 @2 s/ ]8 }, ]1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
    5 o# j! h% A; y3 N1 G1023774 APD            WIREBOND         After "xml wire profile data" is imported it isn't reflected to actual wire.
    6 k8 V6 Y0 V" z! f1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button7 u$ c0 T7 d+ \
    1024239 ALLEGRO_EDITOR INTERFACES       DXF pin location is moved when I execute DXF out
    / o+ f+ z5 F5 y% T  m. |2 O7 O1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist; S* v3 R2 L4 X
    1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed! K. l) u8 A( }0 w. I/ r
    1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
    5 ]- {* C0 j' V- N1 B- N1035896 SIP_LAYOUT     ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
    % N5 E$ Z) ]# Y. m4 K  h) u) h1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
    ( A* T; m1 L, x9 l4 c5 O" l1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)1 F+ ]. u4 G! F  \
    1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
    4 G+ Y1 e' X$ Y2 Y1 c& U1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.8 q  Q  G* o+ F3 W6 u. U
    1038371 ALLEGRO_EDITOR INTERFACES       Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."4 w, v, L9 v! H8 _# }6 _7 N, H  {" l
    1038577 ALLEGRO_EDITOR DATABASE         Modifying Void crashes Allegro
    2 ]" E9 b* X1 o7 u" C8 n1039112 ALLEGRO_EDITOR ARTWORK          Antietch and Boundary layers deleted when Match Display selected7 \( C# ?: B" |6 A/ _) T9 e2 _
    1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing- M3 Q+ o0 Z  o8 C
    1040653 ALLEGRO_EDITOR DATABASE         Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
    / r' M! P* Y# K* ~4 y1041368 APD            DEGASSING        The Degas_No_Void properties assigned to Cline does not work.
    ) D6 ~8 t1 ^/ o) K4 f7 w1041864 ALLEGRO_EDITOR MANUFACT         Allegro crashes when opening the Backdrill setup menu2 t; _$ F* N2 L6 X. G1 @
    1042199 SIG_INTEGRITY  SIMULATION       Waveform list was not refreshed by switching tab.
    + i1 I0 O, J, W: d4 y7 v1042348 SIP_LAYOUT     STREAM_IF        GDSII export includes the full refernce path, breaks CATS flow  P# g+ j7 M( G% L
    1043861 SIG_INTEGRITY  REPORTS          Derating values are NA in bus simulation report when derating table is not in working directory3 h: D7 t4 g8 W5 F5 \2 c  B
    1043903 GRE            GLOBAL           This design crashes during planning phases in GRE.
    : ~( A$ D& M$ y, l! T1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached. x; |; o% h- y: h% [
    1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
    - s- r+ N7 d) k8 l8 ^9 Q1 t, H1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur./ _. F! D0 }3 E
    1044577 GRE            CORE             Plan > Topological either crashes or hangs GRE6 k( e5 ^$ @9 h2 ~
    1044687 TDA            CORE             tda does not get launched if java is not installed. {& p+ s. f# ~; u# E6 Z
    1044754 SIG_INTEGRITY  SIMULATION       Incorrect waveforms when simulating with stacked die7 E5 W: }) l1 u/ J' _2 p2 B
    1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.3 A+ L9 @. `/ `, k0 M
    1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?! f; q" _! M6 v, C, R$ Z
    1045863 CONCEPT_HDL    INFRA            Customer had the crash several times when they run script with SPB16.51.
    0 l0 \, B2 q5 K1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
    , K: E. a& `; ~9 w" h1 ]1047590 ALLEGRO_EDITOR SCHEM_FTB        Buses created in Allegro-CM are deleted by netrev in traditional flow
    6 l' [" k, k' K% X1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.; y( u& u6 V$ S$ v& n
    1048403 ALLEGRO_EDITOR SKILL            Allegro crashes opening more than 16 files with skill$ A' I1 {% `: L- K% M: o
    1049262 ALLEGRO_EDITOR OTHER            APD and extracta crash owing to Wirebond.
    ) C( T5 V/ ^1 M  l1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
    . E  w0 `' F9 w1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
    3 R  k: [6 c; T9 O( e6 R0 C. g1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
    ( R2 b- N# e' _: c0 j1049956 ALLEGRO_EDITOR DATABASE         BUG:dbdoctor deletes fillets as design is migrated from old version0 j1 E) k$ z0 n6 v! K
    1050408 APD            DXF_IF           Symbol has 45 degrees rotation  in mcm but DXF doesn縯.8 H; \( _6 L7 j8 @6 w; i
    1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.$ }) {! p% e, q+ s- s& G4 y) S% w
    1050918 ALLEGRO_EDITOR MANUFACT         Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
    4 ]) r! s1 R, O' ]1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes; l$ s4 ?$ u8 [$ b, s5 }
    1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
    ( K" w& W: \! y* S% t# Z" L, x1052045 ALLEGRO_EDITOR OTHER            Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.35 x" }# P$ i) h' z! C' v  B% y0 R
    1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
    ' u7 M& P6 K- U7 I1052600 ALLEGRO_EDITOR SHAPE            Adding a specific cline causing shape errors
    4 T) i# q8 j; k* \2 t1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.- D# W2 s* ~+ _8 i# Z. t: e
    1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
    ) t8 L9 t( u! W$ O- Z6 |1054269 ALLEGRO_EDITOR MANUFACT         Backdrill Setup and Analysis crashes on attached design. G* G! G. p: }) c2 M6 Q. t6 o0 R4 Y
    1054351 ALLEGRO_EDITOR SHAPE            Shape voiding fails for board having diffpairs with arcs7 |6 ]7 _( l/ N8 h6 [! Y/ n
    1054456 ALLEGRO_EDITOR MENTOR           mbs2lib incorrectly translates refdes label+ h* U  }; C, W3 ~! f" M2 v' Y
    1055273 ALLEGRO_EDITOR INTERFACES       DXF exported from Allegro has an offset in pad location for Y- direction.
    . c" f- B/ ?1 x- v& `4 Z2 N. H1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
      d% k7 A* {9 q' E% M9 D& R! F- y4 u$ C1055481 APD            SHAPE            keepout does not clear shape unless it's picked up and dropped down
      ?  ^7 \2 I) A1 t1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
    8 {& `: Y: L1 A. K  g/ O7 I1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
    % E3 l# J2 F% Y1056579 CAPTURE        OTHER            Ability to define custom variables for titleblocks that update for specific variant views/ A7 D9 {" n0 i0 W9 }" e0 u1 ]$ R
    1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
    . O% e( D4 r6 ~8 d1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.8 J9 t- O6 N5 x- x( w' m
    1058002 SIG_INTEGRITY  SIMULATION       Incorrect Xtalk sim netlist was created.8 p2 c. u! R8 Q: u
    1058364 ALLEGRO_EDITOR SKILL            axlTransformObject() is moving refdes text when only symbol pin is selected for move& C2 A3 L: v6 A1 m2 X
    1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
    ( R' q- X- y6 S# U- H1059037 CIS            PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
    " P: P/ h( `. R4 D& L5 e& G1059389 ALLEGRO_EDITOR MANUFACT         about back drill analisys report
    ! N/ G+ x+ ?& e1 |3 p2 s1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.0 c5 `# S; v5 h, o1 i" y
    1060428 ADW            DESIGN_INIT      ADW Flow Manager Copy Project fails to complete7 G& [5 ^1 _/ I# ]5 M* g
    1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
    : o8 w* I7 O! ~' [, V8 |, ?1060977 F2B            DESIGNSYNC       back annotate in 16.5 does not bring in already placed nets as global nets
    / n8 r& _  a) x7 R1061223 CONCEPT_HDL    CHECKPLUS        What determines a passthru pin?! o! X! x5 |+ \' v2 L# f/ M  V
    1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.) z. q1 w  t5 `& w( q& Z
    1061572 ALLEGRO_EDITOR INTERACTIV       Shortcut keys wont work after "Edit Text" command is finished.
    ) R; G9 h! c% M6 p  V8 Y3 I1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00: P; Q! [! M6 _1 J" z% F
    1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation6 h3 q2 u5 G  E3 ?9 |. A
    1062982 ALLEGRO_EDITOR MODULES          Module containg partitions has been imported to the main design and cant be refreshed.: S8 O, B9 l6 y4 H
    1063284 PCB_LIBRARIAN  OTHER            PDV Save As is broken
    ; t2 A: s# _( I7 P1 o2 Q1063658 ALLEGRO_EDITOR SCHEM_FTB        Allegro Import Logic does not remove library defined diffpairs
    : }, P. c: F. w0 ?3 }$ ]5 E8 n1063778 CONCEPT_HDL    CHECKPLUS        The hasSynonyms CheckPlus predicate is not returning true for all global signals.
    ! G. u  F5 v4 P! |6 f# J1063924 CONCEPT_HDL    CONSTRAINT_MGR   Highlight the net between DE-HDL 16.5 and Constraint Manager.# E6 Q  s/ s6 O. e
    1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
    ! |$ w( ], \9 ^! y1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
    * |. v6 B/ t, J) Z! @0 e/ a4 W1065618 CONSTRAINT_MGR ANALYSIS         DRCs on board but Constraint Manager shows the columns as green.
    ' z# }) F+ l9 `1065641 PCB_LIBRARIAN  CORE             PDV symbol editor is crashing when deleting a group using delete or CTRL+X6 U8 z' t( ?/ e& ^" I+ ^' h: [
    1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
    6 o, @& Z- `3 Q7 x7 `/ a) l1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report1 a9 ]' X! Z& g- e5 g& @
    1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
    ; V1 t4 I! v& J8 @& D2 i1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic# M0 \% {1 S, `& Z9 O
    1067339 CONSTRAINT_MGR ANALYSIS         Relative Propagation Delay analysis in the Partition file seems very inconsitent.
    6 j# I. `; ?' I6 _2 X0 i1067984 SIP_LAYOUT     OTHER            layer compare batch fails with write protected file
    5 F) }0 K$ G9 f9 [/ Z6 d6 G5 O' M1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command8 y* w8 E3 \4 {4 f7 F1 w
    1068547 ALLEGRO_EDITOR EDIT_ETCH        Outward Fanout is not fanning out this 4 sided part as intended, p: A, e, ]2 y/ ~+ [* Y2 K7 u( r# S
    1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067" J/ o8 X! H5 m1 ^
    1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
    ; o0 f9 X) o' K5 {1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify& N- K/ r/ G. g7 O0 V( R+ Y$ ]
    1069915 ALLEGRO_EDITOR EDIT_ETCH        Allegro hangs with when doing spread between voids
    . C$ |' z6 H0 O' J" Q4 N1070007 ALLEGRO_EDITOR PLOTTING         Export IPF omits drill figure characters for backdrill holes
    1 _- M. f( W! X4 n1071722 SIP_RF         DIEEXPORT        Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
    4 j" z8 ?- L4 P2 k( s6 o1072067 APD            EXTRACT          When expoting using Extracta oblong pads with anyangle are abnormal& o/ @, q# `- u
    1072791 ALLEGRO_EDITOR DATABASE         Database check cannot fix error and keep report the same issues cause artwork cannot export.1 f' W0 V) O, m/ {2 @
    1072806 CIS            EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
      B2 L6 H  t7 J1072843 ALLEGRO_EDITOR PLACEMENT        The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5! f, A7 ]8 L7 o: ~  ~! x
    1072904 SIP_FLOW       SIP_LAYOUT       Probe pins not being mirrored in Die Editor correctly in Chip Down mode.+ c, _* F: {4 \6 B8 U. \
    1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
    * A  N' x1 I9 y6 F6 a3 L, X6 c( Q1073445 ALLEGRO_EDITOR GRAPHICS         'infinite cursor graphics fail -ghost copies as you move cursor4 [- S! h8 X1 _! K- j
    1073464 SCM            SCHGEN           Schgen never completes.
    % E, f9 a3 M; ~/ f9 h, f, k9 [1073587 SIP_LAYOUT     OTHER            axlSpreadsheetSetWorksheet command clears the cells in memory
    & u$ u4 y) B1 k) L! c; y  X. @1073745 CONCEPT_HDL    CORE             Import design fails
      K: G3 m" U( X3 D' A1073852 ALLEGRO_EDITOR INTERACTIV       While doing a Copy Via use the last 'Copy Origin'
    0 v: q) r. P3 f8 B( |7 \7 J" q1074279 ADW            DSN_MIGRATION    Design Migration fails purge if there are cells with BODY_TYPE
    . t# b; u9 _/ g' U' N: }1074791 CONCEPT_HDL    HDLDIRECT        User gets port exists in schematic but not on symbol message even though the port does not exist* ~  D0 u; V! o! }5 B
    1075135 ALLEGRO_EDITOR DRAFTING         Ability to edit dimension text block in Instance Parameter( F7 K7 T) ~: L7 f' D
    1075151 ALLEGRO_EDITOR SHAPE            Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
    7 p" |: L: @/ z9 S1 r1075256 ALLEGRO_EDITOR OTHER            Import > IPF in 16.5 is dropping data.
    6 L8 D" w6 t% r0 g' \  h  C1075853 ALLEGRO_EDITOR REPORTS          please add "PART_NAME" at Extract UI( p% |0 @4 C7 `  l3 ~! g$ w* B
    1075934 ALLEGRO_EDITOR DRAFTING         Able to Changing Dimension Text Block  A  T4 P  w; S( N( g/ H# w5 o
    1075955 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer! z. Y# _( Q0 v7 p7 F
    1075964 ALLEGRO_EDITOR SHAPE            Shape voiding is not consistent in conjunction with odd angle and arc traces! S! |# h; V8 `9 B4 P
    1076086 SIP_LAYOUT     IMPORT_DATA      missing wirebond after import SPD2
    ( ?" l+ q" m1 g1 U! d5 j# u1076202 ALLEGRO_EDITOR EDIT_ETCH        Allegro add connect causing crash after Hotfix* A) |& A2 x7 |* D+ ^7 c, K
    1076205 CAPTURE        PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
    $ }  b; E" {* Q/ ]0 ]6 E2 O; u1076536 ALLEGRO_EDITOR DRC_CONSTR       Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
    : y) |2 Y8 q2 m$ [  d4 A1076538 CONCEPT_HDL    CORE             Property visibility changes in attribute form not updated in schematic canvas./ r  C" ]& Z2 d2 D! Y* e" S
    1076655 APD            DXF_IF           Dxf does not get offset value if die symbol padstack has offset value
    : Y; h3 \: i4 X9 g: K1076846 ALLEGRO_EDITOR EDIT_ETCH        Grid snapping broken after slide in 16.6* P- ^2 a$ ]- e" w
    1076891 ALLEGRO_EDITOR INTERACTIV       Symbol rotation not displayed correctly when defined as a funckey
    7 p! Y* o* T0 b- W, K1076909 ALLEGRO_EDITOR DRC_CONSTR       Allegro crashes while placing modules from database6 B; A! W5 b9 \' G3 \; S
    1077084 CAPTURE        NETGROUPS        Crash on selecting bus when Enable Global ITC is unset
    ( u& ^2 s; p, j. [$ ?. _) r1077169 APD            SHAPE            Shape > Check is producing bogus results.
    6 R$ J" i& ~4 h$ _! O) k+ L1077572 ALLEGRO_EDITOR DATABASE         Mechanical symbol created with 16.6 cannot be placed on board.
    $ P) @3 X% a' Q/ L  l) O5 t1077879 ALLEGRO_EDITOR SKILL            Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim( R, X& J# S# D- z$ f0 S( h) V
    1078380 SCM            OTHER            Custom template works in Windows but not Linux
    " N/ J* m' @$ R" c  V& p% W1078497 ALLEGRO_EDITOR INTERFACES       Import DXF does not seem to work correctly.) A0 `- k2 N' X+ F! O  J
    1078682 ALLEGRO_EDITOR DRC_CONSTR       Unaccetable slowness with Slide
    8 r: i0 t/ q( I$ }5 d9 G$ g1079082 ALLEGRO_EDITOR PLACEMENT        Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping9 s; M2 r( q: u  o9 ]
    1079533 ALLEGRO_EDITOR PLACEMENT        Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"% _5 }) P4 v( m7 J- Z6 v  Q
    1079937 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
    ) {- V$ Y! i' B1 @6 y; ^, y( t1082582 ALLEGRO_EDITOR GRAPHICS         Allegro hangs on a given testcase using the MMB zoom control0 p' [! |$ j/ i( b# y
    1082981 ALLEGRO_EDITOR SKILL            Allegro crash while change the new symbol type as mechanical.
    * U3 V9 e5 U/ t1083230 SIP_LAYOUT     SHAPE            Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
    & N  Y* Y3 s/ X( K

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    9#
    发表于 2012-12-17 21:16 | 只看该作者
    看到了几个16.6的“特点“原来是BUG

    点评

    ^_^ ^_^  发表于 2012-12-20 09:28

    评分

    参与人数 1贡献 +10 收起 理由
    wanghanq + 10

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    10#
    发表于 2012-12-17 21:21 | 只看该作者
    rx_78gp02a 发表于 2012-12-17 21:16 1 Z( ^% K! Z. w8 A: z! I
    看到了几个16.6的“特点“原来是BUG

      B5 I6 X* M& b) Y* J3 O' u是的
  • TA的每日心情
    奋斗
    2023-2-7 15:02
  • 签到天数: 206 天

    [LV.7]常住居民III

    11#
    发表于 2012-12-17 21:24 | 只看该作者
    有下载地址了吗?0 n$ d7 G8 {8 s: ?

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    12#
    发表于 2012-12-17 23:48 | 只看该作者
    Look & Thanks

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    13#
    发表于 2012-12-18 05:32 | 只看该作者
    本帖最后由 mengshang 于 2012-12-18 05:36 编辑
    2 P! |0 F3 p, b! t. s( i' C+ ]/ J) g& s5 b- T
    的确,Latest Release: 16.6-S001
    1 `3 g' Z8 B3 m, JYour Version: 16.5-S034
    / @5 ^' l9 j, p3 T期待着下载呢

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    14#
    发表于 2012-12-19 22:59 | 只看该作者
    本帖最后由 micdot 于 2012-12-20 10:57 编辑
    : t. N- D, {. {8 C
    3 n/ A+ t7 z. @6 T% J3 L现在提供下载地址:http://www.orcad.nl/patches/Hotfix_SPB16.60.001_wint_1of1.exe6 [  }* y9 R" L! J) H
    目前,我已经下载完毕,安装后确认可以正常使用!

    评分

    参与人数 3贡献 +30 收起 理由
    jacklee_47pn + 10 支持!
    rx_78gp02a + 10 很给力!
    wanghanq + 10 这个网站提供可信度高

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    15#
    发表于 2012-12-19 23:13 | 只看该作者
    第一个HOTFIX就有400多M,以后的会越来越大,这个怎么玩啊?
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