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本帖最后由 烧饼夹肉 于 2020-11-24 14:01 编辑
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毛老师《信号、电源完整性仿真设计与高速产品应用实例》
9 O% h, M" K% O* v% `3 l) ?第九章 SPEED2000 DDR仿真 ,按照书籍教程操作,开始仿真后报错,如下图:
' g9 n! a% }. t. r 求大佬解答![]()
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& Z) w; }6 Q0 U6 x2 x* l( ^2 sSPEED GENERATOR # H. d6 {/ i3 R" @. @9 n. }3 T2 m g5 Y2 p
Warning: Cannot find the intermediate file% T* I, o$ m6 }# `& x
c esktop\ TEST_BOAR_Ddemo_DDR\Sim3_L2\net\SpModel.sp, a6 @: g/ Y! [6 t% T9 {
One possible reason is the net selection is changed after you set the simulation options.
: Y) y! o; `" h1 l% ]# k; V/ \( o 1. Do not change the net selection after setting the simulation options.
- _7 o5 ]' }) `! |. S 2. If you do change the net selection, go through the workflow and save the simulation options again.+ \/ }) ^# n2 N+ U
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