本站微信 收藏本站 设为首页
 找回密码
 注册
关于网站域名变更的通知
EDA365电子论坛网»电子社区 › 研发技术版块 › 信号完整性SI/PI仿真 › PCB Designer’s si guide
返回列表 发新帖
查看: 1732|回复: 3
打印 上一主题 下一主题

PCB Designer’s si guide

[复制链接]
snowwolfe

该用户从未签到
跳转到指定楼层
1#
发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

EDA365欢迎您登录！

您需要 登录 才可以下载或查看，没有帐号？注册

x
PCB Designer's SI GUIDETable of Content # m& N" @& o$ b2 o8 b6 Z+ j
Basics of SI___________________________________________________________________5 . I; }4 |9 Z- x3 b/ y5 X
1.1 When Speed is important? _____________________________________________5
0 }9 G, m* ^# C8 k1.1.1 Acceptable Voltage and timing values ________________________________5 ) x' F+ }8 ~" D
1.2 Signal Integrity ______________________________________________________5
8 T8 _, q% g4 r* v" }  g1.2.1 Waveform Voltage Accuracy _______________________________________5 $ L; J" T* l3 J2 i* G1 i( B$ M& g  n% `+ M
1.2.2 Timing_________________________________________________________5 6 \. B  ?3 O3 y7 `* M# Y9 R+ d* e
1.3 Speed of currently used logic families ____________________________________5 6 I6 e. |7 h  \0 l) F5 H
1.3.1 Transition Electrical Length (TEL) __________________________________6 * i! F2 e/ O' O$ i3 n
1.3.2 Critical length ___________________________________________________6
% |. K/ Z( A5 \0 r. ]. U; H4 [1.3.3 What is Transmission Line? ________________________________________6
6 o  g  s) i: y# B1.3.4 What is moving in a Transmission line?_______________________________6
; o% J* e4 ~0 u9 `2 ]" h* z9 i1.3.5 Power Plane Definition____________________________________________6
$ k. Y# U8 }0 l, d1.3.6 The concept of Ground ____________________________________________7 1 X# @' P  R, W3 p2 H  p* m
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 ; c' c2 R+ G" ~, p
1.5 RLC Transmission Line Model _________________________________________8 * C! S1 o* c& L9 f; ?$ c
1.5.1 What is Impedance? ______________________________________________8
9 U5 B0 p# s1 Y9 F1.5.2 A Practical impedance equation for microstrip _________________________8
# g- U( Z/ z& c4 q! |$ |3 n1.5.3 What is relative dielectric constant Er? _______________________________9
) C  Y8 x# g) f; k6 g8 s; _) v" Q
. P* Y0 }# |1 R6 z9 q- [4 ~/ U6 O1 ~! O8 J
5 B. ?) Z0 Q5 X
2 Interconnections for High Speed Digital Circuits _______________________________10
5 f9 g# n2 d7 |, _
2.1.1 Summary______________________________________________________10
7 I3 }: r# y! C" V$ |2.2 Examples of dynamic inteRFacing problems _______________________________10 - J# I& a& [2 i0 a
2.3 IC Technology and Signal Integrity _____________________________________12
: a  x8 ?/ r5 f2.4 Speed and distance __________________________________________________14 , ]0 W% p6 d  G* I; M
2.5 Digital signals: Static interfacing _______________________________________15 * {% K/ d* I, b; ^+ [5 b8 ?
2.6 Digital signals: Dynamic interfacing ____________________________________16
  ]% Y# n$ `! S) |" j' Z4 W0 z2.7 Review questions ___________________________________________________18
' r& A* ]% C5 M. C* z, o' t  V1 d5 {/ f4 {1 O$ \. |
( O; C7 d  c8 z8 r) D) {1 |
+ ^/ }, v% h  l& k7 k2 n
3 Interconnection Models____________________________________________________20
" f! ~' V5 B! m
3.1 Summary__________________________________________________________20 - |7 @0 L1 Z: G7 k6 G
3.2 Reference model for interconnection analysis _____________________________20
+ W" w& y& L0 @& J; D+ V8 V3.3 Receiver model_____________________________________________________21
  U. \& ~+ W0 f' H1 R3 \3.4 RC interconnection model ____________________________________________23 % E9 s, R; _' I, O4 g! N! s3 _1 M, k
3.5 Parameters of the interconnection ______________________________________25 / F+ K. M! V5 N/ W6 O* j+ F
3.6 Refined models _____________________________________________________26 0 {. a' b* E) j/ D* d' a6 X
3.7 Review question ____________________________________________________28 1 B$ w; [" b& F
. }4 ^- r" J, s6 }* b8 B) _4 n
0 U& a8 X8 s9 @6 _4 @0 d3 j% v- ^& ~

: W/ l! l& S( R* l. U7 Y
4 Transmission Line Models _________________________________________________31
9 z- G5 V" ^$ F2 s! `' t
4.1 Summary__________________________________________________________31 5 g7 C) d7 j- d5 W3 o
4.2 Transmission line models _____________________________________________31 / {' r# \; u: s3 s; H
4.3 Loss-less transmission lines ___________________________________________32
& B" {8 w0 p; z/ X( F8 b9 F4.4 Critical Length _____________________________________________________34 ( }. {/ ?+ e, H# h) {
4.5 Reference transmission line model______________________________________35
, W* j8 Y: G9 w( N, k6 A* c, b4 F4.6 Line driving _______________________________________________________36 4 g, @! Y% q6 N$ \
4.7 Propagation and reflected waves _______________________________________37 1 w: G; R. B2 j1 Y8 f. H2 [# s  \1 E
4.8 A sample system____________________________________________________39 " z7 M6 _9 S: o6 L
4.9 Review questions ___________________________________________________42
0 A9 o" @* @# D+ ^6 u: r4 g" r
PCB Designer’s SI Guide Page 2 Venkata

# t) U3 _$ }- z1 E9 u8 V( O/ \3 D2 u& i; g1 {
3 c8 T  H2 B1 `) m/ j

7 ?  k# A! M; m9 i; {7 o
5 Analysis techniques _______________________________________________________45

2 R. I4 j# V3 F; C: d9 U5.1 Summary__________________________________________________________45
8 k/ Q4 j2 _9 I! ]5.2 Transmission time and skew___________________________________________45
6 e( U5 j' q7 E! Q5.3 Effects of termination resistance _______________________________________46 6 o+ ^0 b- d" `! Q: d
5.4 Lattice diagram _____________________________________________________48
1 ?7 G8 T% R3 b3 P) h/ t* r5.5 Examples of Real Lines ______________________________________________49
' U+ u2 K4 y, {5.6 Simulation code ____________________________________________________51 9 Q6 I' t$ H( [3 Q5 Z% _
5.7 Examples of results__________________________________________________54
# a3 ]  G( D* s3 Z5.8 Review questions ___________________________________________________55
- \5 A; j8 h8 n4 z2 J7 E
6 c$ A5 d0 v) W" M) d6 a: e$ {
. [2 f5 w$ W# O: x
* s8 g2 T, |9 W% S& h" |
6 Design guide for interconnection ____________________________________________57
2 {. c: h. b0 R- Y& b& ~- B
6.1 Summary__________________________________________________________57
; g  x8 a0 Z5 f) L  T6.2 Incident wave switching ______________________________________________57
& U( u5 X% ~8 a: |: B6.3 Effects of capacitive loading __________________________________________58
1 W) q0 x0 ]" M( u0 ]& @$ H6.4 Termination circuits _________________________________________________59 & \9 b" j* J+ s6 h/ W" B
6.4.1 Passive termination______________________________________________60 3 c, o4 i1 P; [9 {1 O7 `- }
6.4.2 Low power termination___________________________________________61
/ K* p) O7 F' }, `1 }6.4.3 Active low power termination circuit. _______________________________61
8 t: q7 K# f" T) J6.5 Driving point-to-point lines ___________________________________________62
, }! E) j3 \" O, H* N* W" K6.6 Driving bused lines __________________________________________________64 2 |+ e6 S" H8 B" @3 o6 k) [2 x
6.7 Design guidelines ___________________________________________________67
, [; z" ~% X) T0 v6.8 Review questions ___________________________________________________67

PCB Designer’s si guide.part1.rar

1.95 MB, 下载次数: 119, 下载积分: 威望 -5

PCB Designer’s si guide.part2.rar

605.88 KB, 下载次数: 107, 下载积分: 威望 -5

下载资料威望不够？点击查看获取威望的N种方法>>
回复

举报

EDA365微信号及QQ群号！
snowwolfe

该用户从未签到
2#
 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70
: M' V) l" S1 f) o. R7.1 Crosstalk __________________________________________________________70
- U' Z7 L: Q$ ^' s, N7.1.1 Summary______________________________________________________70 . k5 u- {+ _1 t. c! l4 J* X! m4 V
7.2 Examples of signal integrity problems ___________________________________70
7 y: R5 J  Z0 f3 g! h( c# x5 i  T1 @7.3 Simplified Model for Crosstalk Analysis _________________________________71
9 N( s& @! U6 n7.4 Forward and backward crosstalk _______________________________________74
1 N! X/ k6 V" ]% S" B7.5 Examples__________________________________________________________76 ' t! p! }# m! R. h; p8 w! R8 M) |
7.6 Near-end and Far-end crosstalk ________________________________________80
( T! Z9 b( V) L$ H4 q: s2 M7.7 Review questions ___________________________________________________81 2 q  l, t4 R0 n* B( @

1 \, f! q# V. \8 Z# @0 k; f: w3 \. [$ z( w9 C
9 n" q+ ~: [: W5 a: T3 P2 c0 r
8 Design Guide to Handle Crosstalk ___________________________________________85

3 ]# g( r; K- P4 \4 a* n  ~8.1 Summary__________________________________________________________85 ; Y0 b( B6 b; ]: Z. b9 U9 @- A: w6 J
8.2 Effects of Crosstalk __________________________________________________85 8 X+ r; i4 B! |/ p1 D6 q
8.3 Passive countermeasures _____________________________________________86 5 b1 K: Y' c, I+ l, Q$ {
8.4 Active Control of Crosstalk ___________________________________________92 0 k, c, y4 ~  X% b& |- e
8.5 Review questions ___________________________________________________94
, }! R- Z& p2 `6 N( i
9 Ground Bounce and Switching Noise_________________________________________97
: S# H0 `9 `7 j4 u6 k, u$ Y1 y& ]2 Z
9.1 Summary__________________________________________________________97
( R) W' x! F7 |& E9.2 The totem pole Current Spike__________________________________________97 & m8 P! k! S& y6 _' ^  p! j) a
9.3 Current flow in the output capacitance __________________________________100
6 a" `: r, N3 |8 q3 y  }/ b$ [9.4 Total Ground Bounce _______________________________________________100
) l( R, }5 K+ q' s% [9.5 Review questions __________________________________________________105 5 F3 L$ _0 f& W" C
10 Design Guide for Ground & Power Distribution _____________________________107
5 Z8 ~  k! L  A3 @$ a7 d5 k; f
10.1 Summary_________________________________________________________107 9 f% m# ^* y" E5 m; j/ w
PCB Designer’s SI Guide Page 3 Venkata

2 S: M* V7 g6 E3 N10.2 Decoupling Capacitors ______________________________________________107
4 ]0 v5 P" S# l/ e  C% U& H9 l8 M( T10.3 Placement of bypass Capacitors _______________________________________113
' D. [7 r4 I* K( v. Y10.4 Ground and power distribution________________________________________114 + o2 {1 f9 [6 m) a# ~: p
10.5 Clock distribution __________________________________________________115 + l) F+ A4 m$ i3 \% X
10.6 Review Questions __________________________________________________118
9 ]+ q. s- [8 E) i$ L3 J8 e& p, l11 Laboratory Experience _________________________________________________120   v# ]9 Z0 Z% }" H" V
11.1 Summary_________________________________________________________120
' t" J- G0 M8 f2 b8 U3 k11.2 Aim of the experience_______________________________________________120
- L1 z( m  K3 ~3 @7 v5 r9 u11.3 Generator Parameters _______________________________________________122
, ~4 `# F( \; e4 Q1 r% E: z8 _8 M5 V11.4 Cable Parameters __________________________________________________123
4 j& Y7 n; c3 l8 v: f; H+ h: `11.5 Mismatch at driver and at termination __________________________________124
, \4 v& @+ b* C" W* U$ n% I11.6 Capacitive Load ___________________________________________________125 1 z% b/ W8 h- B. A6 p
11.7 7. Time-domain reflectometer ________________________________________127
1 I, `, {4 j+ N- `" Y  M4 ~11.8 Driving the line with logic devices _____________________________________128 ( O9 x/ L; }3 G, c8 S
12 SI Analysis Strategy____________________________________________________133 " i5 q6 K7 l8 F  D
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133 - j% V7 d. v+ b" v+ i( M7 R
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133 & T5 M! F2 p* a" n/ G9 P- e
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
2 c" U& r  \, k+ b' N. Z12.3 SOLUTION SPACE ANALYSIS _____________________________________135
# Z) P( ^3 Y# v7 k12.3.1
* q# D! x2 r% B' e5 B6 gSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135 $ }) Y" O2 s  W1 d2 ^
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135   `) F1 ^5 c; k/ C. r
12.3.3
+ A# F0 M8 E" C! p2 m0 H1 h+ mSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
6 A( u$ V, ?1 ~' V2 \. p9 \  x12.3.46 k' X4 C0 g$ ~4 X9 Z/ V6 d+ D
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
8 \# p5 H- {+ z4 H- f- C, X" s12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 ! {. k( K. K0 \6 `  S4 {
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 - T; D3 N+ h* ?. q! h8 e+ ?! z% g9 d
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
% L6 z6 q" f" W12.3.8
) p! |  [. ?4 q- k2 l9 C* i; ]7 vSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
! z# V0 G4 h( ~6 ?6 Y. V12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
% E4 o3 K# N9 r( k- O  R12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
1 A# K& {6 C2 ?12.4 CONCLUSION____________________________________________________139
: B- E/ L* P, C" _  p13 Glossary _____________________________________________________________141
0 B2 f6 f+ ^5 V3 ]
PCB Designer’s SI Guide Page 4Venkata

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

sshunhua1981

该用户从未签到
3#
发表于 2008-5-26 16:33 | 只看该作者
了解了解

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

andy.wei

该用户从未签到
4#
发表于 2011-7-8 11:30 | 只看该作者
贊一個

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

返回列表 发新帖
高级模式
B Color Image Link Quote Code Smilies
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

推荐内容上一条 /1 下一条

EDA365公众号

关于我们|手机版|EDA365电子论坛网 ( 粤ICP备18020198号-1 )

GMT+8, 2025-11-22 17:12 , Processed in 0.171875 second(s), 27 queries , Gzip On.

深圳市墨知创新科技有限公司

地址:深圳市南山区科技生态园2栋A座805 电话:19926409050

快速回复 返回顶部 返回列表