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改进如下：
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HOTFIX VERSION: 015
: D0 }( |2 @2 E0 s! o: j$ p& ^. G========================================================================================================
7 B C6 B3 |1 _2 P2 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
, ~2 S3 V6 Y! x _' G* k, }: Y========================================================================================================3 X9 b# ~& \6 w1 u( U1 r! u( Q% F
264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip( \, b2 V, {5 [2 j0 Q9 p0 R9 @. o3 f
609206 APD OTHER parallel command fails to run on mcm files" n) }. r$ Y% }+ t4 [
646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time
. }& H2 v! ~/ U7 P; J E# M- ^650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames& G& L. S# {& l
665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal
3 _1 m" |7 j6 i9 X8 \" m7 K666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import
* L! G! V8 W& y+ k7 J669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n
2 ^2 f' y" V$ W/ ~' h669769 PSPICE DEHDL Edit Model on page border causes crash
& i- P. T9 i$ q& I) \/ U8 {/ J671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.9 e/ H7 B! r& Y! N5 z& T4 h* W. s
672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl7 ]9 |8 |! a, a+ |5 v7 U
672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke+ s; G6 F7 F. |
672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa
6 @+ `; L1 g6 d676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets/ L6 @% s5 k" i: A# C; \# u
677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets
) Q$ w0 Q1 k C0 ~& g/ G2 [677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.* C$ N! z6 K6 N: G: `
678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license; R9 s4 U% B9 S+ p% v
678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM S" n& b0 z1 i4 l9 D: w
678794 SCM PACKAGER Unable to package subdesign
% H; ]- S& l5 ^678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2
0 s4 q1 U3 n% {" w; p+ M678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced+ Y1 n3 n i% O! n* I/ c( ~1 Q
679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns3 x( N% v @* t+ b
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i
+ i* T( r, G8 P679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo
' x! @% a% l1 b0 U, n679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.. @. R% n8 w# P( R! P
679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st+ o. ?: D6 A; h# F4 c, q
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri
$ E2 Z! o( `# B% H/ Y681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase
& o! H* x+ `- P$ f1 L! V- [681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if5 p! O# t! y3 l6 l$ {4 `
682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte5 w$ D7 R4 V) @0 B% G7 |
683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
# ]& @/ |) ~, ?3 v& Q& R683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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支持！
反对！
没有人告诉啊，