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偶也跟一贴！! k5 ~/ n) t% S Y$ ^1 U* _/ R, y
以下内容来自《high speed digital system design》。
# K! z2 i" o k# J$ E; o) w- p' r% ]0 |, P! ` O4 U
A via is a small hole drilled through a PCB that is used to make connections between various) W" ]8 H+ k7 E1 P
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and" w2 I4 W3 J+ z! P: V1 \
the antipad. The barrel is a conductive material that fills the hole to allow an electrical
2 T- M3 N; W+ s9 yconnection between layers, the pad is used to connect the barrel to the component or trace,/ \' {$ M& z. w* g
and the antipad is a clearance hole between the pad and the metal on a layer to which no2 A9 f# f: {( W/ X
connection is required. The most common type of via is called a through-hole via because it
1 w& S- c! D7 Q; His made by drilling a hole through the board, filling it with solder, and making connections on
* `0 ]7 V+ r2 Pappropriate layers via the pad. Other, less common types of vias, used primarily in multichip+ L% J2 e w6 K4 |1 i; W
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
+ K6 _0 T8 Y+ Oa typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
; [4 p1 O7 R A: A' D. z/ B1 e1 utraces on layers 1 and 2 make contact with the barrel and that there is no connection on2 P/ }- c h! l) u: I
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias* H3 c: H. j2 r( N1 v' }+ ?; y
are by far the most common used in industry, they are the focus of this discussion.
8 Y2 e& S$ R6 l$ |) L$ `
' o. w2 E5 c2 n0 K6 q) wNotice that the via model is simply a pi network. The capacitors represent the via pad* W; k) d; ?' v$ U5 U: ^
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via# D% m0 _. t0 O! T
structures are so small, they can be modeled as lumped elements. This assumption, of
+ O. `" S& M9 N4 ?$ m% Dcourse, will break down when the delay of the via is larger than one-tenth of the edge rate.7 `' _( R2 T0 D& v5 o
The main effect that via capacitance has on a signal is that it will slow down the signal edge
8 b c6 v2 l8 g! x5 ?9 Orate, especially after several transitions. The amount that the signal edge rate will be slowed
3 i- `3 F# i, a" g2 G) o$ Scan be estimated by examining the degradation of a signal transmitted through a capacitive
$ M) S" p) N0 K0 g% k9 Oload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
0 a9 }5 _. f7 B$ A$ k: m$ Jvias are placed in close proximity to one another, it will lower the effective characteristic
1 `5 s9 {% H, d, n* t* gimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
. s9 y3 H( E0 f6 k' x3 A6 x% ?3 o[Johnson and Graham, 1993]
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+ L( K$ G0 ?5 A5 G2 T[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!