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Fixed CCRs: SPB 17.2 HF054
7 L, X6 a% |, B: R. }04-26-2019
, v# g% l1 w" B8 v8 k========================================================================================================================================================. E3 |. |! J* A/ I
CCRID Product ProductLevel2 Title2 P e' |0 }' v( J) v9 l0 w: y
========================================================================================================================================================0 `! _" |+ c) m# t9 o6 a1 V' X
2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
0 m4 x4 l3 R$ a2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
) H, B" B1 c* ]0 w1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser9 R: b2 w, Y& v# J, ~) @* d
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
3 s \) ]# ^9 g6 J" b2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
1 E* d5 H n. r. r: t( i8 L2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design/ E6 _7 h) H- E2 ~; ?
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
4 S8 g; t( q8 K% b0 o+ \2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas6 }# q7 t! I4 R1 G: n C
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
3 ~$ C* C' g1 R# ?: D' c! A4 b2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
$ o1 Z0 ^0 ~8 a. e+ N$ A9 }2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off) z0 s j* o& f7 m( n$ E/ G
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
0 _( u6 D& X0 }; R# }2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
, ~* K. q" w% S4 L! U4 z2 x2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
/ I5 k( M8 O. Y( [2 l1 ~2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin1 B# q+ r. `+ _3 K, ^" E
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element" o. V" ~- p7 p( ^
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
+ l' g; d% W3 r: g2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
|5 s- M. A) s6 g2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code0 x. Y/ E. ` u2 f( Z' }* \
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
, b4 {6 c; M, n/ E2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
0 n$ P% o" q2 J2 `! l2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets) w: R% C2 G+ S' Q4 |3 V0 h7 m' P
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.' ]9 d: L3 w4 b) s3 f9 Y
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
: R3 c! X7 r8 W! a" p) _: ?2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself': h& G; Q G2 n. x' V
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
9 G. h( ? K n2 m1 \9 O2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'% Q3 r) X2 m. }0 Y
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill# Y2 |; s D6 X$ |* E- l
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
# w$ R: K: w+ A% N5 H2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor9 f& @$ Z! ]8 V, H, Y$ C
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
Y7 `4 N# `3 T1 m2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
3 g" X. \" |5 h* F" m2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
6 O* T( \7 c j1 h2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components! ~# ]; E; O7 P9 @& ?
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
' V+ i0 @, B7 I/ w" {! J! [# o2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
& q' S+ N: S0 ?7 H" f1 G0 [ S2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
5 \% M5 Z; h7 J8 ]& N2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update. B' D3 O3 n0 N5 g6 l. p
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'$ ^) Q9 X6 u1 F% w
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
; B4 T# q2 y7 @8 N5 U2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
4 z3 p% s4 w/ f" S% q2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
4 E) U) I! f* h5 J5 {9 f s; Y2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
8 A3 D" _2 s7 L7 K! l; K1 m3 ]2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
- `/ w8 ^; }( H# r x0 o2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash* x0 n2 ?+ t# ]" t, ^
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.- D) Y' ~0 o7 s2 x3 I
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)& x9 s W0 n) v# e8 B
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)3 Q. ^3 j6 x C, r0 c
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048! n( l' n; L+ H5 o
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
: m1 ^7 M* i7 r+ ]& b; l5 o2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas1 ~5 D: `! _4 y( L
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice3 q* }7 y; s0 I) O3 y
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html, \) k& D- N' a; w
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
+ Y1 U" w% N0 j' _) {1 N! B2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6* Y2 r: }2 S4 U: B" f0 T" k
2050674 APD PARTITION Cannot remove C-Point from a partitioned design) O+ b, V( f4 I7 p9 K( c8 K1 E% g
2068814 APD WIREBOND Bond wires cross on auto-separate
" { x( b3 |# k8 p2 E; }1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open4 K0 d/ A j ~' F
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
! M/ E$ ~% A% M/ k2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL' O3 d7 J0 ~6 ^, p9 }6 J: t% o1 r4 b
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window. O4 ~- U. ~8 P" l0 g) P' y
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved* E" |' w; c& {) ?' v
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
5 q5 x$ s8 J9 [2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager2 y5 i A1 W, \, g2 L: G
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps8 w" i0 ]4 b# Y
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM8 M' W, L7 G0 t8 U+ {8 g7 q
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties' Y& m7 O' z' M. J7 S% {
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
& Z4 l8 m; V& @3 b- R L2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses9 B6 ~1 X! L8 i
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
3 [1 f4 S1 [2 S5 G% H( N2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
* Q5 W& G, o! H2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma7 v, A, X' _1 l" q
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.# |$ U5 C+ d L u" s- P, R
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character7 T1 Q/ H! z! ^- ?+ t4 I; P$ b
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped. |, R) [, a$ C- z/ Q5 j% X
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties- T$ i0 w1 Y8 x. a
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated* u I/ F+ D9 l% ]3 f; |
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated4 i$ q1 N5 X I2 T1 b: R
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated2 @8 g* ~9 Q+ o+ r
2038021 PSPICE FRONTENDPLUGI Bias display is not updated. t6 b0 j. X0 ~+ G! ~
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
+ @) O% V% k0 B7 `2 ^/ {2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
5 K& G7 [( k* x$ B. m( Q2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks1 K( A) n' H) O; m; i. ~' {% L
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.1 E5 x6 ~9 N# K( m
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
7 f+ B9 _8 D0 m: `' t. T2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
: k; `# h8 A! c, |% z2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
1 N3 c2 j5 e$ P* B+ D b( R2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 0522 i6 _3 I8 `3 ]5 x. |& Z
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode8 U- b4 y( B% O6 L5 h
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error- M1 u$ N6 c+ F: z0 ^ v {
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
( r5 W" \$ s$ K! q2 z. R1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
5 o8 ` U8 D9 h% B- |1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session+ ~1 P7 R! E1 [
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
0 p4 I) S) S+ ~8 K' _2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written- ~- j. L+ z8 X2 }6 P* U
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping3 T! p+ k* x/ A; G* k0 r
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
5 b% d: s. }) j9 ], M* G6 U1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
9 p' X q3 l* M: D. {1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
2 _" Q6 s- B6 f; M3 ~: G1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
' T+ g5 o* ]. @% Z1 x1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
) l- {2 e$ ~# E; r9 y4 h2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.& {/ h! ?8 j& V; |
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
4 f4 {- u- @- E# m& n7 c% }1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
7 C( ]- j T9 F/ ]/ ]3 j. s1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number/ \. Z W- v9 `" I! V. B
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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发表于 2019-5-3 15:45
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