错误如下 ! M4 G y* u2 x' X8 lERRORack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which; U* _. M: f9 Q& c
require the combination of the following symbols into a single SLICE2 K0 `6 d+ \2 ]5 b+ m% ]
component:$ I9 r. g( F; V: z2 C
FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal = . w$ w- J$ P1 Y* E Chain[37].uChain/wOutA0<0>) 9 g2 u9 w3 m5 x; T+ B" ?0 b FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal =+ K; x8 g6 j5 g% W3 M0 O/ K
Chain[37].uChain/wOutA1<0>)- y! L: h4 u5 C4 D
The set/reset signal Reset_IBUF_1 of register4 c5 S2 G0 Q3 o6 ?8 P
Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the 7 `/ w) ] i4 h3 _ SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design/ F* a4 ? b6 [
constraints accordingly.4 l# C! |& r* z3 x) [- z
请大侠帮忙
[复制链接]
/1 
发表于 2012-6-8 17:35
ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which; U* _. M: f9 Q& c
收藏
淘帖
支持！
反对！