POWERSI仿真的时候报错 XX is outside of the plane XX

w8832095 · 发表于 2020-2-27 16:02

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POWER SI仿真的时候报错，大佬帮忙看看，哪里出了问题

"Via1302::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1313::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1316::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".

"Via1317::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1320::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1321::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1347::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1348::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1354::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1355::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1421::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1479::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1481::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".

道法自然 · 发表于 2020-2-27 18:12

帮你顶一下

w8832095 · 发表于 2020-2-28 11:02

不同层，貌似孔的大小不一致，导致短路啊，这个孔径怎么去设置呢

xieda2005 · 发表于 2020-3-5 14:08

不是告诉你那个过孔了嘛，用里面的查找功能，查找孔，比如报错里面的，Via1302，看看啥问题，

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[Cadence Sigrity] POWERSI仿真的时候报错 XX is outside of the plane XX

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