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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES# `2 \6 l$ U# x4 S! m4 X
SECTION 1
6 D g. V$ d0 H- b: t/ W7 w- yINTRODUCTION+ |! C+ S7 b0 W- i1 V
SECTION 2
0 {- ]3 U9 L* o) L9 C& B; z$ E6 d) ISAMPLED DATA SYSTEMS1 B& d; ~, [9 H* r3 k4 Y% u
Discrete Time Sampling of Analog Signals3 W0 q; {$ p7 r3 A
ADC and DAC Static Transfer Functions and DC Errors" H+ |) n" v# P0 _ _% ^! Q) s# v
AC Errors in Data Converters# t/ n: v+ L4 T: D
DAC Dynamic PeRFormance4 ^1 h& }; g1 V
SECTION 39 ~6 n! a: e3 `
ADCs FOR DSP APPLICATIONS5 t1 _; C) Q! Z# g' d7 N( b
Successive Approximation ADCs
) Z7 X8 ~! v3 S. d$ G Sigma-Delta ADCs
) ^( a0 T3 {* K* L/ t4 e Flash Converters7 x& U& p* ^8 L5 u1 Y. O
Subranging (Pipelined) ADCs
; w5 {) Q* G7 k: y) p3 w9 c: q4 Q" l: ~. d+ m Bit-Per-Stage (Serial, or Ripple) ADCs
3 u* G1 r3 ?' c r$ [* hSECTION 4
" o1 E$ ]( n) o7 v% xDACs FOR DSP APPLICATIONS
: o0 l5 r3 P6 z) ?, o! c DAC Structures
; A6 Y: f8 P: b) X Low Distortion DAC Architectures/ O3 U/ P; G9 k% r
DAC Logic
! w' F5 G6 Y% A0 P( q: v, ] Sigma-Delta DACs
" r5 W( g5 |9 E3 V Direct Digital Synthesis (DDS)
6 h% n+ H4 M% B' bSECTION 5- c1 z" C( u: j2 y/ v: ~
FAST FOURIER TRANSFORMS4 u! L6 R& G. C- n0 ^5 g4 B
The Discrete Fourier Transform1 e b4 U* X( ?$ e' q9 L; E0 R& u
The Fast Fourier Transform+ z+ b5 C9 ?" W, U) `* `5 f
FFT Hardware Implementation and Benchmarks
/ x' e6 N4 e9 j9 R! D4 Q DSP Requirements for Real Time FFT Applications x: g' }: `5 J$ T; g7 m
Spectral Leakage and Windowing
Z$ v3 \) O5 e5 BSECTION 6
8 l1 L4 _& I8 eDIGITAL FILTERS X+ @! f: y- `
Finite Impulse Response (FIR) Filters
) e2 C9 k" Z' X0 ] Infinite Impulse Response (IIR) Filters# Y' U) ~& v8 p% R( ]
Multirate Filters
9 [ R6 B* q9 k8 n8 F* K% i+ i Adaptive Filters7 l# r, L7 T9 ~- Z
SECTION 7
: J8 A8 x. ]7 u: i' ^DSP HARDWARE
- @' s" l, V7 ?9 X Microcontrollers, Microprocessors, and Digital Signal0 b2 w' X" _, B: M" r& |
Processors (DSPs)
9 Y6 q- k/ T6 G& n DSP Requirements
( k) J- a' x" @8 }$ x ^8 A& e ADSP-21xx 16-Bit Fixed-Point DSP Core
4 A3 R, E1 e% P% F8 w) ?3 G0 L Fixed-Point Versus Floating Point( T- e, d. k6 G% G
ADI SHARC® Floating Point DSPs
y4 C2 x$ n; J' ]; n ADSP-2116x Single-Instruction, Multiple Data (SIMD)
. I% N+ U4 w7 i/ i( q: j0 p0 pCore Architecture
- F8 U; c- b" c$ {- ^ TigerSHARC™: The ADSP-TS001 Static Superscalar
% V1 p/ g0 W+ m: O, D8 pDSP/ I( {$ Y% n8 x! k7 {
DSP Benchmarks7 p9 V( d5 \7 q7 W( J; W9 T
DSP Evaluation and Development Tools3 w6 r" ?* o; `+ ]# b, Z0 ?
SECTION 8
; W* Q' a5 a$ n2 |INTERFACING TO DSPs
5 ]: V. b: B8 j Parallel Interfacing to DSP Processors: Reading Data" B/ d" M" W* d& Y: I* m, B
From Memory-Mapped Peripheral ADCs
' N4 T4 U* C K" W( X8 u Parallel Interfacing to DSP Processors: Writing Data to
4 I' p+ E) R8 z$ [' o0 [; AMemory-Mapped DACs
. n1 H4 X& u: [4 c Serial Interfacing to DSP Processors
# o& C' p+ H7 d, ?1 Y6 C! @1 e" v Interfacing I/O Ports, Analog Front Ends, and Codecs to
& X. x2 @ R0 n1 ^! w/ G5 @: JDSPs
& W$ v: R5 i- T1 _& Z$ X( {3 e DSP System Interface$ F f# O8 S; U. }( b: M$ F# x* u
SECTION 9
# r j- Q7 E: M. b7 M4 y: ~DSP APPLICATIONS
6 u! R/ h2 @( h- c V' j2 \ High Performance Modems for Plain Old Telephone8 Q3 T# k3 I3 F4 X5 Q5 Q7 g/ d
Service (POTS)
9 s1 ~$ s. _8 `1 U Remote Access Server (RAS) Modems
( S7 h5 J$ S5 W ADSL (Assymetric Digital Subscriber Line) O. B: _& Y2 G O P
Digital Cellular Telephones
; d. d" O2 ?' U7 Z+ M GSM Handset Using SoftFone™ Baseband Processor( M8 Z( J3 q* J' ?$ P# h0 S2 _
and Othello™ Radio
/ s8 l; [- S0 j5 N5 d- v' z/ l Analog Cellular Basestations% L' T$ m: m7 N! z8 M: L
Digital Cellular Basestations
. c, i- a; p+ k5 _- N+ [# k q Motor Control0 t% I5 `. C( J/ D1 v
Codecs and DSPs in Voiceband and Audio Applications) o7 {+ P- _; I, _3 n2 P5 |9 _
A Sigma-Delta ADC with Programmable Digital Filter% ~8 l1 G$ C/ \' s4 Q% T
SECTION 103 z* @" C( j/ A' p& s! B8 E
HARDWARE DESIGN TECHNIQUES# t O0 N/ K- u! \8 L6 b8 Y( ?% ~( j
Low Voltage Interfaces2 T' J3 R- P5 W2 |" h
Grounding in Mixed Signal Systems
7 l7 @. i0 ~, s6 s+ g Digital Isolation Techniques
' O# K! z! V- K* u. O Power Supply Noise Reduction and Filtering
5 \, }6 X( @$ q Dealing with High Speed Logic
0 B- y4 s4 H; R9 |; T: X; |' RINDEX文字 |
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发表于 2016-12-1 15:13
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