|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
DATE: 05-28-2016 HOTFIX VERSION: 071
g1 ~ H9 f- P. h' K' |2 L===================================================================================================================================
) L. b1 ~% {, `$ Y) i% D) HCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 ?. {/ V7 [' Q; W- {* N===================================================================================================================================
4 B' g4 n8 [6 ^: S1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets
: H& `5 l0 A: W, @) U1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package* Z4 ?, Z8 r# e9 X: o
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser2 b+ s' j% b! g, y7 r# | v; E. p
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
; X( H# a3 I# [$ t3 B1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
) v0 g* r0 y* ~* E8 U1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
6 w; B# G& U2 T: W) W1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
; g+ r+ z# P- _; X, ?. G5 I% ^1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set6 I, W3 ?* }: Z) O" f
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
4 \- z( H/ J5 @- s: b1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
1 K |0 M+ b7 u+ C/ e1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
! R s ^1 {/ y5 i# g y: s/ ]1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
( o9 n* w, ^% G/ @- r3 d; b9 w9 Q2 J1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets$ @$ G$ i1 j+ x( N8 ~
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open. w, n$ w8 \0 v/ N1 P0 I
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
. \! y4 Q C; _1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC% G/ G7 y- ~" [: o0 c+ l, Z0 R4 d
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
( K0 ^7 x! Z8 s, _. u0 K# Z1 x% a1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas, t$ k F2 S9 \" \/ `
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
: \8 N5 S/ S2 I! F8 I( A1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
6 A, \$ c1 ~9 H7 \1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
' Q, V. b8 S) f6 \; o) d8 ?1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct( j. J7 F# ]. r4 s) U
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
0 |* F) H! D8 y/ b1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'9 D: l) K4 g; o* T% _" b% ?, ?
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed9 @* b. T) c% y, G* A; X
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
, f' m" m! R$ b: t; v1 L! f: |' J( g1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager0 q$ L1 Q- A4 i
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short5 e4 i0 Y2 w, H! z" |" d) @
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property! g+ R0 K& g4 h
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only" W7 a: W; g P/ c
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
1 W/ m# p5 U2 G, [: N1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
7 r! |) z# B# O1 A1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
$ s+ _& u1 j( ]0 e1 p1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings" e' C( _7 U+ ]4 x/ C
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'2 t8 U* X9 N& g' C4 y; T O! u
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
* @# @- Y0 C; Q% U6 s/ ]. z' f6 n) F6 T
DATE: 04-22-2016 HOTFIX VERSION: 069; f$ C) A) n1 U& B
===================================================================================================================================$ {" v0 o: b: R' }7 O9 {
CCRID PRODUCT PRODUCTLEVEL2 TITLE& A+ g/ n8 D! j
===================================================================================================================================: n- c8 J$ _- j4 j* C5 g; }6 d# p
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
0 u* N- E0 O1 L9 e% f# b) c1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
" ?+ g( Y2 @6 t/ m) o1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
1 n& M. J/ W$ W1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol% v5 S/ V. w; H0 q, r7 h
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
7 n+ g* c$ ?( E# Q1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
; n: x' g; c& ^+ [7 [% u, T1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals' @7 G# N: g+ X" F7 b H
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
) p! w0 u1 V9 @1 z8 @2 j% ?* z1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed6 ]2 M8 P' [- u c' r" G
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
4 z+ }! V1 v# C7 c' D% K1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
Z2 Q3 V0 u+ C$ K/ y! m7 W1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
" ?- z1 c: @2 P" K* J1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
3 ]6 ]5 \; H, u7 [& Y( P! I1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
/ x% l. T- N, D) Q. X1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
- g% c3 B3 K7 b: O1 ^4 C- V% z1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems: T4 F( K( A9 R
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro5 ~" \) C' |. _! \! e. t9 O8 m1 J6 a
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
; T: T8 _( U+ m, Y1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons" a1 `1 h' V8 t9 _7 @7 h% J( O
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
# g! \0 L7 B! j" W8 h1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted- w2 K1 l5 ~, g
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
1 f& @4 g2 e" Y; P' Q' Z9 K5 z' x4 K1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
: P3 |; W- h7 ?# P$ A1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error
- d& g+ Z6 P/ H% t1 |9 ~1 l. G1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.. d9 F5 s0 j; m# R9 G
+ A/ q _) Y/ M% w0 ]; WDATE: 03-23-2016 HOTFIX VERSION: 068
* m$ m0 k5 ~: M0 o===================================================================================================================================0 g! u' b3 _. q' m2 d/ M) M: w3 ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 x2 a# o2 B5 x4 r/ b2 u# E===================================================================================================================================) E' b* L: T5 i( G
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager0 P' B1 e( H. V) \- F( q
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file2 W: W, M9 ~9 w* O
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license* _0 z! K% @6 t: m* y* O6 E3 i3 s- c
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short' e4 y' M) _; f% @' g7 r& E
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
G1 z* E2 E( w8 ^/ R1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
& `6 l" ^ J* ~5 V) D! D' B' w* x1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
H4 F( s. X/ |, j7 @, L1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file( D' ^8 i8 b$ i; n( I* p+ P
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
! }9 m4 S; h9 `/ H/ E1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
2 M. c0 e1 k* ~. v# Q& U7 c' N1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .* b5 W4 x6 ^+ P. z2 x% u
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts0 r$ g- |" p4 a: }9 F1 ` }: p9 ^
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
7 o, w0 T7 F: V X' M3 U5 F5 X
8 R: i( a# B9 v+ z5 R5 p2 ^% kDATE: 03-11-2016 HOTFIX VERSION: 067
( t e9 c7 S) X. z6 b1 T0 S===================================================================================================================================( K; k$ a5 s8 a2 y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& r2 |) c% ~( b7 ~) j===================================================================================================================================
( a$ J: h# @* i& x1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group* \) z, p P+ }
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines8 z% ]7 {! `) d! m4 ~4 Z8 S, O' J8 D
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error4 s' K, h6 g6 r4 t5 Z$ Q. T
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
8 w V& J& n- x2 g1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property% ^% g g7 x. n6 O$ C- ]
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net j2 H# L# }' [
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
! V: M' F' ^$ F8 k1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes0 A/ A4 |5 b A8 S+ S2 j! A; r
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing; u$ R& u/ x% W) [9 E
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager/ ^$ b: M/ f9 s6 G# @
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
" @" X$ G' h |$ A# {) A+ W1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties" | X" A- p! a- z! k
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
7 W6 R; X+ U* L# c! Z! q+ R# e) {1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
5 ~ z$ z4 K3 i8 k; B3 n. S. G1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform% j m/ k8 d& j. C' [& H0 V& E
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.8 M' P, o4 j" R! u
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error0 L/ U3 F! p1 [
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled./ m! L& k! W0 T) K. |
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib6 d$ m7 p, V5 z3 M
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines5 q8 l+ e$ E* r
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols: p$ G M; P+ k/ M2 e! t+ m
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
3 `& O o3 x) X: G# s1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
2 w3 d2 e+ n' p) ~, L8 L+ R1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash! {9 ]" O( `2 |) d4 y. h. r2 x- G& b
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
9 _5 [5 ^5 K, _! a1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
! W0 U1 g. \& u, m: d/ |9 [. F) A1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
1 w, t; Z' [* d% U8 I5 K) f$ Z1 G1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
; R& Y7 ?' t4 W+ D* d
) w1 g0 Z4 m9 S' F9 A: qDATE: 02-26-2016 HOTFIX VERSION: 066
p" g0 {& l) Y9 Q; }7 B9 Q+ D' e===================================================================================================================================
# _, N9 H) M0 R4 E+ _7 M' v- Q& iCCRID PRODUCT PRODUCTLEVEL2 TITLE
- g3 }5 h. _/ |. F. }" @$ c===================================================================================================================================
% f7 a+ A. P8 h: T1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
6 p' |+ J# @1 R1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes1 ?1 R; e ?% M$ ~& m% B! C A8 X$ r
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
7 v# y6 r5 x; i4 t+ G. `1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
; e4 f' l) k( I. Y/ I2 }8 p& j! f1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr1 E$ ? x# S4 W, {& }# f6 w
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue. [! d% m' G+ U3 h8 t4 f+ f
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
8 `/ {' ^$ N4 w) G1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
' F: ~+ p8 E, I8 `1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run8 W5 x# ` ^3 q- I! T( ^0 z* b
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed- H% Y4 C0 @5 y) ]) g. ]7 d- o
3 \" @" V" R6 A! s5 Y4 f1 z. F
DATE: 02-12-2016 HOTFIX VERSION: 065
2 E1 M: e+ F- o8 Q* @+ p' C$ I===================================================================================================================================
* } d9 Z$ s, u" W1 C$ L% H* F3 UCCRID PRODUCT PRODUCTLEVEL2 TITLE
& b% U; p0 e/ \! K8 h===================================================================================================================================8 y& M$ \9 D! ^0 J
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
) J! |) V, G* U# M1 m' a1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
, _" {4 W9 Y6 a. {# i/ m6 F1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
/ `/ s6 F1 j4 z$ _" \1 s1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents., N9 w7 i0 C P0 C0 J, B1 n# w
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
( w. u( d6 x. e: v$ j1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine8 [* e/ v; a4 _: `2 a" P5 n9 u8 h
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger/ r. v+ s7 K9 [! ]1 ^9 e+ O
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
& W! N; L' Y0 c6 L k6 J1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
5 {4 L [1 U+ e- E x. t1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license. S* q8 v/ w4 o2 D* Y( V
; N1 n. x$ ~) I9 }
DATE: 01-29-2016 HOTFIX VERSION: 0640 z# { }3 s' d: \! j$ Z3 k7 c
===================================================================================================================================
4 L" N0 y, r3 ]+ CCCRID PRODUCT PRODUCTLEVEL2 TITLE+ b4 j& ]8 F6 R* c3 r( A# k
===================================================================================================================================
5 C% t% t! K$ l1 q+ J' q. l/ F1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
" i1 y) e" q' {& l1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF- P2 Q6 H7 x" j; L
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
; [$ R) c% R! f: ^ Z$ l7 P1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected' ]/ I0 S! M8 V; W1 P2 S" e
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.; ~1 P, O: t+ c) f! l
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default- D# ?2 Q: X5 _/ R: A) H
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
5 X, D: `# L0 H' {1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
6 y$ f- w6 H; c8 \9 S, b4 ]1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
9 [: \7 g9 Z5 m1 x1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic; N+ A; O9 g- u, k
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor1 M4 ?, v' g& t- \$ H m; D
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)9 R2 f# B/ l, p6 z
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
! m6 C4 f2 u; ~6 u1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash& n$ l% r4 F: u/ x. Q# r6 o/ D
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
% D- j" ?6 P/ [& O8 u- m1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor4 l& L3 G0 l$ }/ Y; P3 m
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
2 @1 `5 K5 ~/ |( W- L$ g4 }1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 632 `4 ?2 m$ [1 J' p2 h/ B7 r* G
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes7 s2 Q; `1 x( v) ?
0 S3 K6 A) b" l
DATE: 01-15-2016 HOTFIX VERSION: 063# n S# |' y9 @% ^
===================================================================================================================================* ~! F. N3 f, q, t1 [) y7 `- Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; r& M) M$ v! X4 x===================================================================================================================================5 }/ T, D+ A' a/ C+ e! P
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
/ T _" s" s# O# H2 Q# j1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs) z( [3 q/ T9 g: v) o& x
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
$ q3 `) {2 T- L; Y: u+ F1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant. J) K2 ~6 ~: c8 h9 h6 E7 H9 ^, n- @
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
+ m5 O" |( h9 H2 H- E8 u, }1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.64 t% M8 p3 ^' ?. B5 Q: M
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
+ q8 D& k$ A5 \4 P1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
9 t4 }+ U& g) h |1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
' Y) k( y9 F3 w5 H# ^* ^1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
& e$ M6 f( P8 _& q$ N$ @* M1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor2 l7 S' L o/ t% E
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property( z2 G& d3 ~2 y( }3 ^% {$ e( k
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
. N1 B- K5 R9 [& x1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
, N/ A6 T4 F" A& L9 P1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol9 k" R2 p. J) g
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'% V! {6 W) A0 ^" Y
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes0 z6 C7 ]2 M2 r3 D$ j4 H$ ?# D
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
( N# A, s( |7 w0 R1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
) |: V8 F; O s9 \- L1520207 CONCEPT_HDL CORE Genview crashes after renaming ports% Y7 g4 a0 s7 }. f
Y- W8 d7 ?8 f' R! j( }5 R5 R: ~
DATE: 12-11-2015 HOTFIX VERSION: 062, J2 Z! h4 A0 g. ], Q% @& [
===================================================================================================================================
! t* b* M* f* T$ |/ K& xCCRID PRODUCT PRODUCTLEVEL2 TITLE# C/ x6 S2 [* t
===================================================================================================================================6 _- d7 x# W" E: b6 {( X# T/ E
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
2 Q) P1 b& I8 m1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
6 F% w3 Z0 A v: f2 _1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option- f! K+ B* x. @
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC/ ]! r" t+ F4 k: y" l( x% @
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view* e3 t/ Y0 q' U0 S' S
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked) o; o) c" E( w+ G& ~7 u! C
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.; H' ]7 z4 N5 V1 U; n4 R& G
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file9 W7 k0 V3 |6 f
1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
0 _) d T' p8 U S* y$ c7 h: j1490311 SCM OTHER Block Packaging reports duplication when it should not
/ t$ f# x( p3 u1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
M. M6 r' w; y" G1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message' x( i; Q/ b3 k/ X
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)" |+ ^$ w9 E( d3 w; `" [
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit4 s, @# E1 [" ^$ n) z
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout) t5 T- d6 @, N: F1 U- }' _4 K
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
- w0 W) o4 G0 p' t) K, `1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
) l7 z O3 S5 T3 w1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
x* _ I) S1 A6 Q. [1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly5 x4 ?/ O% D* q. Q, a
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
" }8 F8 h) F3 A3 M2 S( T1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
$ m& @ C$ G, M, {7 e, M1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
, ^6 Q! D& E9 j* n1 j+ V, q# L1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
! y- \ \5 }' `" x: Y4 I2 g1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
- f5 x( X9 A7 E* _0 d+ W* t1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out b7 ]. {- w. ^) y+ y0 T
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
: a& F1 t& M# q$ u6 W) w" q- i- Z1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form9 j- ~( x5 t3 [% z/ O0 d% J, T7 l
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
/ M* O# W; p: W N1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings" [& k8 o, ] z8 U/ u9 d
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location1 Y) x* F2 l! i
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized) ?; H. C" Y, s9 e" u; p' ]
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
. f# g3 G$ E! p$ R4 v3 B7 {1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
5 q2 _" F% X1 _. _( g" \) m8 b& i5 X1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin. S3 \0 M5 @9 D3 i4 S
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving& o+ b% [: k! Y! g7 [
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
( K' k3 ]: Z0 u, } v$ M- {0 k5 H6 o7 K4 l' c
DATE: 11-20-2015 HOTFIX VERSION: 061
! Q! {; e9 X: w; C1 I===================================================================================================================================
" J6 M- p: T4 n5 ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
. _* V, W8 U: g2 O- i2 G===================================================================================================================================5 L8 D9 ?1 s, U, L
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value3 t. V! f, X/ o+ b( |5 t# u
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
9 L; u. c) q d3 N1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
% f1 ?2 _- S r) m# a1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle" u6 I. w) Q- B7 i( [* v
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
7 p' ] @( b9 c; k: O7 V( \- J1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set9 j% I K3 v x: c9 s4 e
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin& e* S6 k3 w0 g+ J
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
; q$ ~+ z* S8 ~2 v" L M1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
6 W1 A: a/ L, Y! P1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
# B: a" q+ ~" F1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
! S, K1 p* K+ L; z' n1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy: U4 L' T! K6 V2 ^. O5 ?* w- y
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
* r( E( z$ P; d' j1 n9 Z6 e1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
( w' I. C# C1 c& o/ @2 W6 I- ~1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice1 r9 S' b6 Q8 |! u, t
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues1 @9 R& l6 S d. N- Z& D
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only) O0 h0 r) ]6 C# K) z0 H
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project, H# K' P- g: V; w1 Z
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.7 Z6 l* _: \8 l4 @
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
( M9 N! A+ g) `0 r1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems& N h! {$ \1 ?0 ?& b! O' A
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
- h) c) i8 |+ c+ q1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior: D3 {% W1 U# B9 Z) g6 a
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board3 o& x% t7 g K# F& _/ S
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
# c U/ ?; f4 C [/ d! S1 y" V1490299 SCM OTHER ASA does not update revision properly* R8 B% `6 O: v9 W
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
/ k2 W% @! }4 G( B1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
$ V; f1 q8 p; I& K( U2 r# S! y1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
6 j2 A, k3 Y- M1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
5 E: Y7 ^- W. @$ l& a, `3 t; h1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash. ]9 W4 W! H8 _. @ Q# I
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL$ h( a, |5 e6 {/ q# _5 q' J! @
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581( `( J+ P2 h" r" H/ Z- A" Y8 b
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size3 o, k7 i/ W9 \; \
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
7 q, I' ?) w' ^& u1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file( H V( A0 v; n/ ~; W$ {
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
|
/1 
发表于 2016-6-29 12:21
收藏
淘帖
支持！
反对！
楼主
发表于 2016-8-17 13:05