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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the
/ Q4 a" i' g o4 \9 U9 G) lspeed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.+ D y& t- |! ]" ]
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally1 ^5 O2 H w6 g% J+ U' H# G
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.4 V9 v/ p" |, I+ N7 j
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in
) p; m; B% @4 ], K6 u! R0 Wthe cache. |
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