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Hyperlnyx中仿真，U1芯片为XCZU11EG-2FFVC1760E，
5 W% Y% |; e b$ d; t4 A使用IBIS模型为zynquplus.ibs
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6 V* c4 m0 r c; X7 I[IBIS ver] 5.1 E; \, Q+ E. n4 O
[File name] zynquplus.ibs
' @( q* }: }/ r) z[File Rev] 1.12
) U6 R! [- T3 i" L, F' G[Date] 22-MARCH-2018
+ n" I5 X) G7 M+ R% w8 c, m- H) m! ?8 U[Source] Derived from spice models, rev1.0, using. e* v& c5 D/ |2 V' f
hspice 2014.09-SP1-2
$ [( I6 q% R$ } J$ x% ][Notes] Xilinx IBIS file for Zynq UltraScale Plus I/O standards.
% `. @4 ~6 U4 K( z All models are preliminary.# g$ h( d% ^ Y: A. ]+ G
The version of IBISCHK used is ibischk5 V6.0.1.5 Z B' g: P/ S6 e( b( v: @- Y
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0 K' G1 b& b! }; F& i3 w1 z[Disclaimer] The data in this file is derived from SPICE simulations using
5 C: X- [) q; q modeling information extracted from the target process. While( N& s- ?( x- w+ q5 K
a great deal of care has been taken to provide information
5 S9 c! Y* X' U8 T8 u# |3 ^ that is accurate, this model is considered preliminary as it
) j3 d: a& u0 P( m6 J has not been verified by actual silicon measurement. Treat the' R% E" {; j+ ~* q, I* F
data in this model as preliminary until actual silicon6 }! H: h& E. j( V# B6 I! R
verification is peRFormed.
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[Copyright] Copyright 2016, Xilinx Inc., All rights reserved& r7 G0 o- O5 j v6 P# B8 @
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仿真的时候报错如图，请问各位朋友这个该怎么解决啊？
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发表于 2018-10-18 12:42
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淘帖
支持！
反对！