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EDA365电子论坛网»电子社区 › 研发技术版块 › 信号完整性SI/PI仿真 › PCB Designer’s si guide
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PCB Designer’s si guide

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snowwolfe

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content
. z2 D" h; w+ u% rBasics of SI___________________________________________________________________5 / H# v  n& F5 d- |0 K5 `) U
1.1 When Speed is important? _____________________________________________5 5 q+ M3 G' D; ^4 R- H& C4 }
1.1.1 Acceptable Voltage and timing values ________________________________5 ) N8 Y0 I: C6 a. A  `* K
1.2 Signal Integrity ______________________________________________________5
# w+ `" u6 p. n6 Z2 y* K1.2.1 Waveform Voltage Accuracy _______________________________________5 * F5 O- W$ i/ f8 E% i
1.2.2 Timing_________________________________________________________5 , k9 }0 c5 W! C# t$ J
1.3 Speed of currently used logic families ____________________________________5
7 A& w4 @+ k$ _. }" N: u1.3.1 Transition Electrical Length (TEL) __________________________________6 ( N9 T7 x3 k' V$ n
1.3.2 Critical length ___________________________________________________6
* x5 K3 E1 Y) ]- L1.3.3 What is Transmission Line? ________________________________________6
) j3 w3 J! r" M; H5 U+ F1.3.4 What is moving in a Transmission line?_______________________________6
! Q+ K6 ~7 R6 A# H, H( q1.3.5 Power Plane Definition____________________________________________6
9 J& L: Z  D3 S' ]7 O1.3.6 The concept of Ground ____________________________________________7 * }# D/ l! Q+ P& |2 \
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
$ T, g! A% @1 \1.5 RLC Transmission Line Model _________________________________________8
+ L. c2 j  j! h: y; j* P; x1.5.1 What is Impedance? ______________________________________________8 6 y2 _* J6 a1 h& M2 ^
1.5.2 A Practical impedance equation for microstrip _________________________8
0 W" ^3 a, ]8 C3 b, V+ M1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10
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2.1.1 Summary______________________________________________________10 3 a  @& s/ |) B8 A
2.2 Examples of dynamic inteRFacing problems _______________________________10
: u) i* ~' r# U( C3 m( t! [2.3 IC Technology and Signal Integrity _____________________________________12
5 a) d0 ?6 a- F  P$ Z; J6 L" q2.4 Speed and distance __________________________________________________14
. T2 v; o, J- R2.5 Digital signals: Static interfacing _______________________________________15 , P1 e" D4 v& @8 B" j# y/ ?
2.6 Digital signals: Dynamic interfacing ____________________________________16
0 g8 ?2 N# M$ ~( ]8 g2 f2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

8 L/ A; @# x, s! r! h2 S3.1 Summary__________________________________________________________20 ! `" _" M. D" j# L) c$ H
3.2 Reference model for interconnection analysis _____________________________20
, c4 S; d4 B, Q* j3.3 Receiver model_____________________________________________________21
6 g6 o/ Q; _  c2 M6 v" C( F3.4 RC interconnection model ____________________________________________23
. y) W* {- U/ M4 A* V5 d4 D: Y- t3.5 Parameters of the interconnection ______________________________________25
& z4 \: w9 m4 ~3.6 Refined models _____________________________________________________26
3 \# b4 y; ]- R. j6 `5 ]5 E9 k3.7 Review question ____________________________________________________28 + x+ W5 L- n0 V7 k1 r) V
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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31 3 v* m1 a  _2 c. I) c+ R, J' I
4.2 Transmission line models _____________________________________________31
$ \* n5 K/ c, Z0 Z$ y4.3 Loss-less transmission lines ___________________________________________32
4 @0 g" D; i. a# `0 B1 w4.4 Critical Length _____________________________________________________34
2 [6 g. l! u  H& D* Y) ^9 E1 C: p4.5 Reference transmission line model______________________________________35 ) B: i9 [9 ~5 J. Q
4.6 Line driving _______________________________________________________36
" v9 v: l9 n0 _$ P, n* p( B* d4.7 Propagation and reflected waves _______________________________________37 - n. F/ z0 W, v- N# E' S4 D
4.8 A sample system____________________________________________________39
3 q! L3 B& w. ]6 {2 J+ D7 \4.9 Review questions ___________________________________________________42 # U, L. o7 H/ R' i' s0 d( K8 X
PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45
+ L$ S' D* M. x( H; ^5.2 Transmission time and skew___________________________________________45
0 i8 Z: {) {6 P0 `" u: R6 r5.3 Effects of termination resistance _______________________________________46 + i4 W% f8 ~/ j+ ]& |  @1 ^
5.4 Lattice diagram _____________________________________________________48 - D# t" p2 S; {& K' A4 B2 Y
5.5 Examples of Real Lines ______________________________________________49 ! L; w" p6 w! z2 o3 t0 }* ]
5.6 Simulation code ____________________________________________________51 ! b8 ^0 W2 K3 z1 ~
5.7 Examples of results__________________________________________________54 0 K$ t) Z4 t) k# I5 f% d! T
5.8 Review questions ___________________________________________________55 " Y1 u  b% s& z0 y, R  w' a! S& P

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6 Design guide for interconnection ____________________________________________57

( ?2 _) Q  |( o5 }7 V- J6.1 Summary__________________________________________________________57
5 y6 S: H# z0 h4 X& U5 t: E$ Q6.2 Incident wave switching ______________________________________________57 8 x5 j5 J; B) B& C
6.3 Effects of capacitive loading __________________________________________58
; [( ?5 J) n# b* `& q, H6.4 Termination circuits _________________________________________________59
% ~7 O; x' E$ X, z  G4 @6.4.1 Passive termination______________________________________________60 ! j( Y7 B6 l% |6 Q3 z1 |: U0 q% x4 G9 m
6.4.2 Low power termination___________________________________________61 6 B- @$ S3 {4 V# l4 m
6.4.3 Active low power termination circuit. _______________________________61 ) }; ]6 V8 l6 T+ Z* ^
6.5 Driving point-to-point lines ___________________________________________62 $ q& F& Y: _, H& t! B' d9 Y
6.6 Driving bused lines __________________________________________________64
: l! r! v9 L# d, ]! J0 B. V6.7 Design guidelines ___________________________________________________67
% `/ p# s- j- e. o( @6.8 Review questions ___________________________________________________67

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snowwolfe

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 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70
5 z- p" y3 P/ M" c, H) ?+ ~7.1 Crosstalk __________________________________________________________70
; |- Z4 {) F* m4 i$ k7.1.1 Summary______________________________________________________70
- n4 g! z3 R2 a- L7.2 Examples of signal integrity problems ___________________________________70
# w9 I8 E5 G' z; e- U) ^7.3 Simplified Model for Crosstalk Analysis _________________________________71
4 |4 r/ z8 H$ z3 R7.4 Forward and backward crosstalk _______________________________________74
/ [8 N# Q* o! d; a# [- Z7.5 Examples__________________________________________________________76
4 d) G- \7 o" c; M6 ^" K1 V$ k7.6 Near-end and Far-end crosstalk ________________________________________80 ( v; E4 ^# b8 Z, n5 r1 s7 `
7.7 Review questions ___________________________________________________81   X; v, [5 [+ N/ f: u
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8 Design Guide to Handle Crosstalk ___________________________________________85

2 ]) I! e1 W- x8 @5 A7 P# q8.1 Summary__________________________________________________________85
1 f9 y2 l3 \4 @2 d5 t. F+ l8.2 Effects of Crosstalk __________________________________________________85
2 t/ ^, n! U/ }8.3 Passive countermeasures _____________________________________________86 3 }  G( k/ w) p4 ?; [0 L
8.4 Active Control of Crosstalk ___________________________________________92
  `+ C3 r% o# _& D7 q- i9 Q+ M8.5 Review questions ___________________________________________________94 1 t' V& F) z8 n1 p, ~* l! m) m6 [
9 Ground Bounce and Switching Noise_________________________________________97
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9.1 Summary__________________________________________________________97
' h3 \8 Z) s# U$ n# t4 _( C+ `9.2 The totem pole Current Spike__________________________________________97 / B# m* `# d/ Y& J  D
9.3 Current flow in the output capacitance __________________________________100
1 ?$ x5 d6 c' k* o( @) j9.4 Total Ground Bounce _______________________________________________100
3 G' [2 A* D4 |. X( O) q: j9.5 Review questions __________________________________________________105 , B7 @7 I1 @% C6 Z! C
10 Design Guide for Ground & Power Distribution _____________________________107

6 G- c7 j7 n5 `7 Y/ W10.1 Summary_________________________________________________________107 3 W: B  G& l5 D% x
PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107
$ t, W- F' W# u* f10.3 Placement of bypass Capacitors _______________________________________113 , }4 g6 f  X; F8 C  e4 F# {
10.4 Ground and power distribution________________________________________114
' }( C' u9 B' g6 k$ Y, |" N10.5 Clock distribution __________________________________________________115 % k- ?1 l! r6 B5 K
10.6 Review Questions __________________________________________________118 ( n6 W0 x# Y1 L' V: `( D# J
11 Laboratory Experience _________________________________________________120
/ h2 r4 u" X4 `# N  N# u/ w11.1 Summary_________________________________________________________120 $ _9 g7 _1 d# _( s, J$ G% W* x, n  W
11.2 Aim of the experience_______________________________________________120 ! I8 g( z% y- X
11.3 Generator Parameters _______________________________________________122
0 i6 p& u1 I; y$ h+ {2 m1 w' O# B11.4 Cable Parameters __________________________________________________123 6 N0 e/ d$ \: m
11.5 Mismatch at driver and at termination __________________________________124 ! }4 c; @8 j" ]2 w
11.6 Capacitive Load ___________________________________________________125 ; m  @  f  H# `( A+ h$ s
11.7 7. Time-domain reflectometer ________________________________________127 / M, \0 ]  N+ Q) X( D% \
11.8 Driving the line with logic devices _____________________________________128
8 L- \. x$ E* m. t: b4 }3 V12 SI Analysis Strategy____________________________________________________133
) B% s0 H/ [+ j5 O* @9 Q2 g; ^! p12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
/ W! o% A; t5 H; c$ I/ W12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133 # |5 E0 k! G, f) }1 z2 j1 z7 J3 c; K
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
8 \! @- U- p1 S12.3 SOLUTION SPACE ANALYSIS _____________________________________135
6 Q, T7 @/ Q0 R12.3.1
8 W3 W8 L( V  _" Y/ nSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
  A& D5 ?4 f: h! W3 n( u% C1 T12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
8 {" h. w. v% B' X# t12.3.3
- B( C! `( V/ {! r. T5 USTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
$ s& m8 U6 E5 u  \# t  c12.3.4' J9 g! J, b: X$ n4 E( [
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 - u* N7 ]  F% f2 ]$ a9 S4 Y: U) `  _
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
( x6 F$ V# D0 [12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
* j! o6 ~5 d0 ?- A7 d12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 2 _! O. P0 F3 _/ K% [! k
12.3.8
( W" m% G8 P# I$ C+ K. RSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
! \. E5 e. b. h12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
3 r! l( H6 i; B4 |12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
4 \0 K7 a" I! R12.4 CONCLUSION____________________________________________________139 + `  Y  C5 i& _) m$ @" n. h
13 Glossary _____________________________________________________________141 + x" G- e+ Q* T5 z" X5 E, F0 i
PCB Designer’s SI Guide Page 4Venkata

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