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DATE: 05-28-2016 HOTFIX VERSION: 071/ h5 X* `6 Q# Z) K2 R; y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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4 g7 m% Q" k0 e! {7 C/ N1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets% b0 Y; g1 |; r/ c6 S
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
8 {8 F0 x8 f3 W# @. A1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
9 f6 t% W# Y3 ]1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly% Y: T Z2 {. G
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
M2 `6 t0 ?! z: v8 o2 ~# D1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
( d7 f; g3 u1 d: {& v1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
7 d. R+ X6 M k! G: T' A& \1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set! |( j- r0 N8 F9 o U
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
3 m& i. r2 {1 S5 M" v0 A( D1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
4 h* n$ {( r7 Z1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG# q* a+ @/ ~( w# C$ V
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
& `6 n) {- P& u( T8 {/ O! {7 T( Y1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
9 l, L/ i* H. R1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open- Y& S4 @ E! X+ }) C* A. ]7 l
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
' I8 v# Q ]7 t4 V: D8 L- g1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
1 p: k0 Y4 e. X* W1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
( N( q! f" |. m3 u# J, `% a1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
; I' [& g# a4 r( R6 R1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions- T5 a; ~( M W* m
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete1 z- Y5 J, {! S" c* s
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape./ _5 T$ q0 A* [ q7 M, z
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
' M; S: O- ^! o1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
8 a" H1 ~7 d7 p! r$ [# n1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
8 u- K& P8 |6 D! [+ X" G1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
- @0 ?. [6 x$ `" H! y& O# l6 _1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*... @/ b+ O/ B, {0 Q1 t0 F
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager3 B" @) y3 _4 F$ @) D1 L e$ g2 b( C
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
* @0 V9 @: J: r {1 Z1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property0 c- ?8 d7 G6 A0 I! i
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only* C& a1 O. _# ?7 B+ W
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display& _% y* s8 N. d# ^9 d
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)" {; |( K% A) V5 E5 e
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
3 o4 V2 F |9 a0 x1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
0 B+ z# o8 K/ Q, ]1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
0 |# `5 }9 \+ F! K5 d1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
6 n, t) B" p* \. K% z/ u& d( u5 I3 v' D- O
DATE: 04-22-2016 HOTFIX VERSION: 069
2 F$ x# F# h% K! u+ A; }( _. g===================================================================================================================================
" d6 n8 D+ i! w% S P0 xCCRID PRODUCT PRODUCTLEVEL2 TITLE
' Y1 c1 l- v3 h; O& l; q9 q t===================================================================================================================================
8 a. @4 Q% k: m0 Y/ K1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
) |5 Z) i% L, u1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode3 c9 A' S3 c: c' J" _4 s
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
2 A7 y6 c( q' g; P6 K1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol2 H& ]: L) o7 l
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing& u O: V+ ?5 s6 L5 m5 K
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute( v/ u' G8 G4 o- r& N
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
( O9 k: g: ]9 ?1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
J* d- Q: ?) b6 }+ s1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed* D' q n6 P1 Y: ]4 n- r8 V
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder+ F4 E/ w( h4 b+ P3 \
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
4 y/ k7 X2 {' U) D1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork4 V% {2 ^1 B3 s+ h
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message* g" Z: \0 P8 ?- \1 V6 N
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point% h% e z7 x3 m
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
, @$ T7 { c. I* ~# _$ o1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems6 p2 j# G/ W+ W4 K6 q! H2 o
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro/ W2 q: s8 K% K& j
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups/ {5 p9 F( o3 {
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
: l# r5 l1 R' d3 o# z1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes8 i7 f/ W/ }) T9 W' u% H
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted: j! b- a& A S1 i, H
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
. z/ N) T4 D2 ]( @; v% |1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
9 \8 ]& v! y* |2 s4 O ?' t- d1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error$ w+ ~4 \/ R! ?0 a. {1 I
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film., O. M" W- y+ R4 U
4 }5 T' }* E' O- wDATE: 03-23-2016 HOTFIX VERSION: 068* k ?, H2 M5 }* ?! j$ t" O
===================================================================================================================================- J' H) c5 E9 o1 E) ^; v% X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ Z7 A$ J" W1 b: Q$ t4 r===================================================================================================================================0 W( I+ P3 X1 Q6 Q
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager: b7 E+ y- c3 q8 k6 A3 k" }& r
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file B L$ t8 e( ^* }* ^
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
3 n6 w; W+ b q7 a; S# l# \1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
9 P1 F6 {4 F5 _* z5 L1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
* ]: a% v: k/ B9 R; i" J: z4 d1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.+ P1 H2 M1 j, v& {# R
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol6 w* I3 J8 @) ?5 L
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file6 B6 Q: v7 }* _7 @& n8 R4 n
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report) Q( f1 q+ Y( @ K, l: v- R- a3 V
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'3 x) s' Q) a" V. m- n
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .. p3 f; d' o+ @2 }+ X% u
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
( s* ~( r% K1 E: S9 h1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
: B | {0 e7 G" O% l) |" K ^; K* v5 _( M3 m+ H1 i
DATE: 03-11-2016 HOTFIX VERSION: 067
6 P% U) F$ n9 b===================================================================================================================================
2 {+ \) D& _ C0 k. v/ g8 TCCRID PRODUCT PRODUCTLEVEL2 TITLE7 p3 M( y# U: k0 `0 a6 {# l$ o
===================================================================================================================================
0 G2 N; T" z1 D9 A$ W- Q+ s& B1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
. ~" ]3 d: c7 D1 `2 {/ D* d1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
2 s/ A, s& W J: ~1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error' i/ Q) g8 V' s# B* d6 r
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'$ p: z% B' [3 ^( M2 q: r
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
$ v$ {$ P6 e% R7 A1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net2 j. H" O! k% H* K- z
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
) j2 g) i* N- d0 i1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes. V3 M" L) G ~, L
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
7 B+ e; z- g4 H* c) t7 @1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager3 Y( [5 u3 J6 O; v
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters0 `2 g9 Y% r- J4 a j$ P
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties6 ]- i5 b$ E) a: S: M9 M* M
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
( s9 i6 u+ g5 J6 D5 f1 f5 F }1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net* I% t7 u. a. Z7 D
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform0 E, z4 ~, D1 X+ ?- p
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
- i* \' n+ T& s1 ]+ |1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
( X% Q4 f" @ a; u3 x& u1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.; Z, I3 b. J0 o5 b9 c- `/ u/ d
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
. S* K2 w( B+ M* {% D1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines6 H# ~* I G1 e
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
& t0 S7 v Q) s. ^+ Y$ U, t1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board) n; n" q9 |8 G, H0 T
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
) R& Z) I2 J* a7 Z1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
) r4 K+ b! O% k1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked. y8 y1 ]7 [* z0 m6 _
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.1 m& R5 c, |6 `- [, a. b# B
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
9 y' \0 ?# b4 k5 K6 ?1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design( d6 f( E" C2 |- G
! @- x+ }& ]9 F5 U5 GDATE: 02-26-2016 HOTFIX VERSION: 066
2 B2 A) }! \: t% N/ s( O0 o' q===================================================================================================================================
0 }8 y/ @/ S+ }! JCCRID PRODUCT PRODUCTLEVEL2 TITLE
, o0 o9 ]- l' E, i( E9 Q5 V===================================================================================================================================/ ]7 |# q" Z0 j( D. C, ?# J% m5 g
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
) f5 z4 y9 j& g6 B1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
+ d7 o* X1 C; S1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions7 l) X. Y& D. M ~, H
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
1 O4 L H6 C) h1 k1 k1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
7 A8 d: _; l/ X1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
1 o' V7 r% n7 b- m3 A; @- @ N1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
* A' y9 B% V; ]# I( P: o. V1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins5 J( s' _9 `4 `6 i7 ^- [2 ~
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run7 ?7 b7 o; c% e
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
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1 d: r2 l) [+ pDATE: 02-12-2016 HOTFIX VERSION: 065* i. e7 o( z# ~- F& N
===================================================================================================================================
" D' W8 |5 i! r$ h( \) WCCRID PRODUCT PRODUCTLEVEL2 TITLE. G+ ^" z3 H* M* f* b- u
===================================================================================================================================
1 k! A: O% ~- k }' n. F* M1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working1 z5 [. M6 @4 P: i. C8 t% K
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
' Z. T* P) w6 i! K0 s- [( b1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit' f4 X8 S0 e+ A5 w
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.! F9 h* J0 }9 q' X" X* p& y# _
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
3 y3 j, A/ U' b4 s9 l/ _1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
( F; _8 U3 B- Y' F$ o5 p1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
( p, g, \) x z# H1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
' x- [/ |1 ], o1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
9 d& m$ W$ Q5 ?0 b1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.$ r( F% {1 F& P
/ v- J; e5 e, A* {4 }DATE: 01-29-2016 HOTFIX VERSION: 064) }& X" ?6 R' Y* H
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CCRID PRODUCT PRODUCTLEVEL2 TITLE$ v1 \; \7 W$ B0 e ~
===================================================================================================================================
: z8 Z4 N" u8 K+ Y" k3 C1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
, X z* j _5 S! v v3 q1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF1 j' o; c, ?9 h; p3 U
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.: V6 B7 h' x) u+ C! q9 K
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected4 D4 ?. y6 L8 e
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
7 E# r' e2 y9 n" W6 ]. T2 E* }1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default2 ~; H5 `- X" e- d+ b7 W
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
8 A) N7 k" i# V) h4 K% O1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
2 z7 C! Q5 D+ |+ g. e1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
" D* k# C& ]9 C6 l1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic; I7 T$ ~+ m/ C# ^+ F9 P7 o
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor8 z" z; W) t/ T6 l/ |8 d H4 d" ~
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)
1 S+ b3 e; A5 j6 l0 u) @& G# r7 h1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
7 d( j2 ^* n5 M$ C. s1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
) T9 v# ?; Y4 }. U1 r# m) X- {1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes. g& B" G1 T: K, \
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor# v( k$ |& q' I! Y/ J
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
# ^1 _/ P, R" b( E, F. l! Z1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
# G% e0 e' }- W1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes9 W3 ?. {: u' v- O- i: `
$ r% m" g: F9 z. @5 k
DATE: 01-15-2016 HOTFIX VERSION: 063/ L. g/ ^, v' R
===================================================================================================================================
5 `; g8 ?! R! B$ fCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 S" D# g1 I( `1 G1 b7 E1 ^8 K8 u===================================================================================================================================. A3 h/ G l, d$ I/ K9 ]1 P8 M
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
% \% b {7 [; s1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
7 G1 l9 I- c5 E4 u1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
0 r/ G& L. b7 p6 |2 ?1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
, e4 ?5 a$ g0 i4 ?1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork y9 x2 d( ~% Q1 P" d
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
p) T3 M3 S+ n' j4 @1 B1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
' R4 V# W, E2 j* j# W! C+ D1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
8 y+ l7 ]5 V. A/ S1 P, N/ b: |6 y1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
5 ?1 f* O8 \% N1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
$ Y) Q: d$ Q6 q7 C) q" j1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
) T6 S3 ~. ^3 m. W1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property; q6 f* m' T% [# b. q* y
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly8 K' d" [" ~9 Q; m$ z, R0 O, _' ^; |
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
) _+ C; G2 ?: o+ N% R% G( j1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol8 r9 s! E& ]* m5 E
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'4 i3 @' M4 x. j$ o1 q
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
, L4 d( L" ^5 O, B6 Q7 `) K. @1 B1519518 CONCEPT_HDL OTHER Genview does not generate split symbols: f$ U$ j; a7 A( c+ x1 }( e
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
0 G: M# I6 x# m4 j9 I1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
, o5 Y& g. |0 D* [
" Q' u. F3 b9 mDATE: 12-11-2015 HOTFIX VERSION: 062* A7 Q% j$ ^4 z0 f
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 f. v) w$ S, H$ ~5 ~===================================================================================================================================( F0 a7 i3 W- y, V- r
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output, i! W V8 o v& N2 Q. j' B+ R( @
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file4 H, e+ s2 d( R. K; F3 N7 W
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option# R; [- `( n: |9 r$ r5 [1 H
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC1 [$ Z4 J2 h. I4 k9 g" `
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
' J1 c1 D' i; |8 ]* m; `& F1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
* ]% x E4 U; y1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
2 t( i" q% L* A3 ^, w. |1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
) Q+ O0 J T4 P; K; S1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding! }' \" o( s# D
1490311 SCM OTHER Block Packaging reports duplication when it should not8 T8 Q8 \$ K% E/ ?) |( e
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'( E4 ~+ P: U' X: t# U5 Q2 q
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message9 h; W. t8 v( S' ^9 E% k( n
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
# d6 R% m( W1 h8 T5 M9 p1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
5 U" a3 c7 y. V+ z) o$ p1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
7 R4 m# |8 A7 O6 E1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )4 {# S! }4 A3 u8 {' U! v
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
1 @2 _9 F# m; D4 |9 Q* z- g1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
: r8 c j, A+ A& {. T1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly- k% g+ S! R3 i' r7 P( G& B
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this5 k) N- m2 ^0 X1 e& h# O' k6 ]! \
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
/ v1 V+ J# E& }. s) k/ i9 A1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default3 K5 H1 w; E3 x, X" e3 t1 t
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts, _! T: Y3 x. _+ U/ `
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
: o8 ^. {, G; j1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
1 E) q! W8 s3 r1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF8 q8 p9 F9 N( B0 C/ R7 i; s$ ~: U
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
5 ~# @) N8 k$ e9 G9 U& Y8 _1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
6 W, f& n; G* j' i( B3 L6 j" Z0 X1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
( d! C* g8 |' a* H1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location: r( C3 [* G; K
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
3 F; _4 G$ G- f* A1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
& l/ B+ H* k( `9 B8 c1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items' V+ B3 E% Y" I' L
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin1 Q# Q- F6 `( o* q% ?% q7 b
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
* Q# R; z2 U8 h+ k; |" I1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None7 }8 A1 o1 p; C3 r( d( i
9 Y( F% C0 {5 C! B1 FDATE: 11-20-2015 HOTFIX VERSION: 0619 U' ? d) N9 ^2 }
===================================================================================================================================
. [- V0 N' T0 J- ]1 M7 VCCRID PRODUCT PRODUCTLEVEL2 TITLE1 u9 \0 [9 D3 m- g
===================================================================================================================================
/ |; w* m% l3 K: ^4 s# N" }1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
& j4 D' g( [* D6 a6 }& `1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init: g' N% m5 i' h5 W# k
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
7 Y/ n% q7 k( P1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
6 i6 ?) U. A/ j" m( u* @4 s8 o1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
/ {+ J" o9 j: B" V+ w1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
4 v6 m+ s4 Z7 o1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin @" z+ _& ^3 {! Z
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
7 L) L8 E& W& j/ R5 P" g1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
1 y* K g m' @4 c7 m2 K$ |1 D2 G& i1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
( A4 [, b6 X5 W3 t4 F. y1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL( o' U1 L$ p" j! Y7 L3 T
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy: i5 A: i5 z7 y$ p
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
2 L& X& H+ N9 [3 \1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets/ U6 B0 \+ ?+ _2 [' O1 ^
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice8 l2 o! N7 T% Q$ \/ a! ^
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
& |1 z2 Q5 \" @1 O1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
, t$ L1 B) u+ j" P8 G1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
# D$ [6 Y; N% E4 ]8 { i# J1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
. L, f V* o1 n6 P1 N1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility$ B& r$ L% \ k/ R
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
& h( G9 ^# S; d% x/ \! y9 X1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported7 k( ?, h/ B) c; o
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
4 S8 q( r$ S6 \% U/ c1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board! Y' j6 C: }- E3 l4 `
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
7 d: l$ T# Y# ]( B3 L- x1490299 SCM OTHER ASA does not update revision properly
1 _9 L* N! r* |( O5 X6 {" |1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
G4 y- T2 V% D6 j1 W/ w3 P7 e, |1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints4 l/ X( g, R+ G
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
( v! w5 c' o _/ T6 c& K' E1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
( T2 I3 e: [1 y) p+ }; q" q1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
8 Y% E* I( g) \2 R- r1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
9 O; U% v d, ]2 Q) Q1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC25811 x" I# B+ q4 {! O5 d* U9 i
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size8 e* P, }8 g! }2 [$ l) {4 _7 g
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
0 M! x4 }" O; H. }6 a9 i3 s+ ^$ _1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
9 p1 X2 [8 a* @1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05