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DATE: 05-28-2016 HOTFIX VERSION: 0713 X% y: s+ v! f: ]" c$ ?- ? T3 d4 q
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
( L. R1 \8 b* U6 j) I===================================================================================================================================
( z6 F/ @6 I1 l, j6 [2 c1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets& P. G" m0 p k: w; M
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package* Q( m* @8 k9 p
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
: y: P% u3 L- i$ d3 L8 h1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly) i1 \# h; Z8 N( N) C
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.2 G; F& F: O; C9 p; v- x8 O. W
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.3 f/ ]8 d& V* @: u! [
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
! n$ H; f! {2 B" |" r1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
& ~' V$ l# B. E1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'6 ]" a* w, U+ o3 W
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
& ?$ ^& g% x7 `% x( P0 }' j1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG5 l" ?4 E8 b, k, ]; c
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon7 [' T9 V, n1 w2 D/ _' j3 K& Y
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
) j1 _+ a% B+ g$ _1 `1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open7 \, M! g+ J5 b% @
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters0 i4 Y I/ _1 z' ]+ w
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC5 K/ i. x( ^- ]
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins; A- z2 S8 W- y2 F% K; o* S* O
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas# a% N" _: o* C3 R( h# Q" k
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions$ a8 u9 p( z8 X# `& ]! y7 @
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
7 m1 h1 C+ v% o7 d( z1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.6 X( j; f$ A H5 ^
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
1 B. H N4 a7 t1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window% S. O8 ^/ t4 J. H$ M
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
9 P/ B; z$ I8 N1 d8 E. h( {+ |1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed9 |0 X0 H4 C9 ~: P
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*..." M; V5 m9 i& E2 l% T' ^: E; u7 q
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
/ `9 [/ l% Q2 D1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
" l3 G, `- S7 ^! I- J6 J8 Y1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property1 }! p! i) u4 z# h- \
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only. {/ c$ r# @$ G* f
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display% Q! T9 y1 p* T# W0 t
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
W F& l/ X9 S! y4 p3 j6 m. d1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
/ q/ |7 W6 U) t# E, K% B$ c+ M1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
- Q6 n1 w; p' L7 b1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'! s5 D5 y3 R9 B U ~* v+ Y
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files. Y* j1 q9 K/ k7 A$ B
) s$ |4 w8 E; n$ S# j7 q( T' z' |DATE: 04-22-2016 HOTFIX VERSION: 069& I9 {5 p! N% p O; f: u
===================================================================================================================================
3 A( ? s, D8 qCCRID PRODUCT PRODUCTLEVEL2 TITLE
; t8 b+ \; \, S===================================================================================================================================* f7 k" M% }( a; d
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output3 @5 z9 [$ {, h6 a3 [
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode" F* v+ `/ d( W
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
% i! c% l2 w0 W2 V1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
5 ]% J1 D" O7 J5 X0 J0 M2 P1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing' ~! \1 H; ?4 e m4 w* {2 r+ N* [7 Y
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
3 s- _& d: Y$ ?6 I. ~! {; m; i1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals% N, s, @5 a. `* Q7 {
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork1 ]0 E$ h2 ]2 O4 K, R; x9 O4 ~
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
, ^/ U) D7 G3 E7 }% ?5 V7 y' H; @1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
$ ?# Q8 K5 i% h: B0 V9 [1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
* t4 ]! F' f0 s1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
: _' D. B5 m+ D1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message( }+ q8 z) l( G) G
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
' g1 V& g4 N3 V& E& x: _1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines# x( T0 N0 ]- Z. l% g9 `
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems8 y* y4 W3 }) S' K) ?
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro' h" L0 L5 P: `) W" e' U, c
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups( B" B. x1 w2 a/ J
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
9 X" ` R' Q7 b) G7 x1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
( }/ h- S/ @8 ]! G, m1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted( B. V% k/ l3 T' B
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
+ x# Z' U5 {5 B1 h' C1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM( [5 U4 Z. Z! Z: @
1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error
& z: K$ I" {8 w& ^" c1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
6 i* [+ n! I# o2 M1 s" o
0 e5 n! {) I/ _! I. aDATE: 03-23-2016 HOTFIX VERSION: 068
( y* n! S9 X G( Y0 e, {8 d2 A===================================================================================================================================
: b6 a# M8 ~- ]% u) {CCRID PRODUCT PRODUCTLEVEL2 TITLE
_( A4 E% k; p2 \===================================================================================================================================
+ p3 A- |# \; T$ T1 b$ g1 O+ l1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager0 @, x6 X. @2 ~" v7 @# U
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
x; R2 \1 u3 t; l6 M$ X1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license& ?$ R2 z6 `0 K
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
4 b: H9 X3 |2 S2 K: ^1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system% x0 l- `, O' G2 Q0 a
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
0 H) d6 ?' G u8 F5 T4 J: D" I1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
Y% p7 V# a8 ?/ [9 F2 p1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
& n& K% L4 Y/ R/ L) ~1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report/ }) T& m0 X. P7 _
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
# b; s' i9 K0 q0 H1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .% g# O) m! l" `6 G
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts, l* _% Z \2 |: q2 l7 k2 i
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
* ~9 R5 U7 O# s. \3 N; M! X1 {5 }7 z' ]. V1 o2 r3 l2 ]6 | o
DATE: 03-11-2016 HOTFIX VERSION: 067
4 A5 N$ G: |, H5 i: k: i% I- p===================================================================================================================================
! R2 e3 H9 ^, n+ f% qCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 K1 E( J0 S* i8 b===================================================================================================================================" _( I) T, x) ^ R' m* U, w0 m
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group9 R$ R. n0 P0 _0 [" d' Q, ^/ {2 s
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
' m0 ?9 w7 A/ k' d$ V1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error0 K& f+ U: s- h% D
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
& `" |8 y) c, R. h9 z3 p1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
/ F d+ l# F4 y, X, |) w6 { m1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net- W. \+ e/ O4 k6 V- V
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file, D4 g0 m+ m6 A' P1 |* I* j
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
3 \" `4 N3 N" Y5 L" |3 M1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing- o8 ^. u! a8 A4 \) a4 Y
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager# d2 n! B7 g5 Y7 t4 M- n
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters' h' J/ g5 G4 ~" U1 f1 }9 }) s
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
5 ? h* G% ~4 l1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
* n: F s% `; o) ~9 E1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net: B1 S1 a1 s2 P. I4 N4 g) `
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform8 w0 h) a9 x6 Y9 a2 T" i6 |
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.& j1 ?6 }3 I/ J
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error0 c! w l6 ]5 L
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
* l/ {, `0 `2 o# m. x, Y. }3 v1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib7 V" |, r' z, Z) M) ^
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines* U4 Y& P5 e7 E" S
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols! s+ d: H( O$ t' b% ?* ^6 u
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
" u; e8 T1 L, C$ b _- d( Q1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
3 f; X& e( C1 r6 b5 U! V1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash/ K: i! ]7 f4 g4 k3 z9 D+ e8 |
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked$ }( i" _6 U" m- {5 A4 L, ?+ x
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
5 S3 M0 r# U# @, s- ?! k1 }; x: o1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with# B. e5 j9 N2 _ B/ N$ ?/ O
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design2 k1 k3 \: p3 T
0 N# p/ I2 k: f5 A" M+ zDATE: 02-26-2016 HOTFIX VERSION: 0669 h% e7 ~0 v$ b& ~$ T9 [
===================================================================================================================================) s9 u2 B+ O) o: _ u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# u, l& {, j* V$ W; h=================================================================================================================================== D5 i: F( S( T9 T
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
8 R9 n( [ O9 i/ y1 r! t5 F1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
7 L, G+ B2 j. v' J3 U1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions% s4 B% V2 a: ~% e) s
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
2 W) F9 B9 o0 T0 c2 n1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
4 x- Q8 `1 W1 Z1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue) s2 q. [3 U& _
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
0 X0 P6 E7 K" M/ O, x. M' B5 N1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
8 c# d8 Z# w6 x! Y1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
7 S! e0 F% j/ S1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
' I9 N8 b( e& Y7 j7 j K, j
8 y7 \- K. Q, j' K# F( `) @DATE: 02-12-2016 HOTFIX VERSION: 065& w; v) F$ B) m2 S
===================================================================================================================================
# H3 k* U N5 D8 D/ ZCCRID PRODUCT PRODUCTLEVEL2 TITLE5 f Q2 t9 k2 S/ D# O3 N4 O
===================================================================================================================================
! i8 w; `. p5 o) ^' F$ [$ ]$ X1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working/ ~8 k9 [" s1 O& P$ O0 m! m% s. [( n
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
/ z' J. \/ v2 a/ ^1 a' g. @- e8 z2 K1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
+ D5 w4 M! C# H1 L$ z3 R- t- l i1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
- b" l. ~' u! @* k1 r, F1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms( R) _9 Q, q& l" H# a. L4 S$ ?' z1 D! s
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine0 I+ M8 k+ M: d/ |; t
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
5 y3 g6 t% A+ E, x% ?1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
' ]5 E2 `8 u4 H1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup9 V1 j) s/ H* x1 V
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
/ s! N0 w0 j+ _
& o6 v) P+ N5 P( ]; |3 ADATE: 01-29-2016 HOTFIX VERSION: 0648 K% k: X; s+ @* T: F' h
===================================================================================================================================
" v& J( }9 l" v, W" S- hCCRID PRODUCT PRODUCTLEVEL2 TITLE! a# |' R9 o; B2 q! ~
===================================================================================================================================
, S7 a3 t g; r5 ~. @' u; c1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain& q' d& ?' V% n
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
, b' j8 I# p4 F" d- M# i0 j1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
. {1 b, P8 ], b. Q% x' |1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected2 l! u3 B2 }1 l
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
3 `, d6 y0 D6 }6 n+ t1 e1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default6 U! _: t e2 [7 I0 k& O0 @
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
3 N* ]3 h. S7 a1 G1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
: {# ~2 N- u& a* n. L. X" P$ a1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
% t9 a z `5 a k* M- h1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
* L) X% c. T5 y2 N1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor# A+ |+ h- a% {0 F {: A
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file): A& [) r2 {' C1 T: |
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design" H/ v$ y0 h `' g3 o
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
$ K- K3 o# _. X* F4 |# ~% [1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes% O c$ z3 [% ]" v: x
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor2 m$ a; g3 S: e- v( j
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct, L" r3 A6 D7 X1 A
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63! T8 r- f. e+ T" e _! p3 o1 H' X: {1 A
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes6 t z3 f v' _( \+ s7 s1 F$ u
5 W( u. Q, V8 w, r3 U- d3 t
DATE: 01-15-2016 HOTFIX VERSION: 063
! I+ d& ]4 f. [6 t+ a" Z, E===================================================================================================================================' w) f* g3 Q2 ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 u$ l% W' i, i1 r- z
===================================================================================================================================$ Z' r$ \0 O2 d: [ |
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region2 |3 x7 u: Z2 b" ~3 h! s. y7 O3 w* M
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs9 G! |: n. w! y# \% F& b0 J
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
$ ~6 l5 f" L4 D0 G; Y1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant' b; \5 S) w8 Q& P2 q, f
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork' [ ^8 S' ?& d3 d1 Z
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
/ G6 ?0 f& _& N/ d# `1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
6 R# f! `! }* \. Z: ?- }1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.% s, ~2 }3 C6 Y; @4 @
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
0 t: f. G# a2 Q& P1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out; P: X: ~0 i' \& d- m
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor* o& }. L% h5 W3 e! v, g8 O$ P
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property1 Q6 @7 F# a1 b4 E& n$ M( x, G( U
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
" M8 X/ V4 z: L! ^- S4 X1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation8 ^6 N5 |& E6 b+ s, `/ g, t& f
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
* f4 h. S& \& M6 r! V1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'+ b, a% R' _( s* P( y
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
& ~! u2 E9 u: Y& U q0 S) T1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
0 y' K& J8 G9 R- w4 a( U/ _% w1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas4 Q6 I) R9 V+ b- j- R6 y
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports! k( A k1 Y! L5 T1 j. b9 u. n1 N
+ K2 S( p' a! Y3 F5 X
DATE: 12-11-2015 HOTFIX VERSION: 062* J0 K" {, b9 c7 m
===================================================================================================================================$ @; Y0 @) h" x% R& M; s( k
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 p- o4 t0 R B: A( F===================================================================================================================================
% {( c) x9 \& s" | Y2 v1 ?1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
7 S* N2 e0 G7 H1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
, }6 ]7 `0 q8 g" f5 N% D1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option5 Y( B) v- q. }7 c% }; Y' j
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC" g I+ w( @% b+ ?/ ~
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view. p' H: [1 H6 r4 i1 w9 l# N2 L
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
5 \( f4 o+ u& t( Y1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.! O% A' n1 R% Y* Q8 E4 l; i
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
; k( Y( _0 z) p0 ]4 z1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding7 |5 }8 r2 @6 u
1490311 SCM OTHER Block Packaging reports duplication when it should not6 a9 J- D% v3 ~7 A& H
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
/ y3 z) o4 F$ \3 ?1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
" R. B% |( l6 ]+ r) k9 |1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
* O+ z0 w) z& W. g* {8 R1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
: P: x2 E. Q6 }8 ^" C* F7 P1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout. d5 e' S* s7 E: n% Z9 r
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
$ Z; j& ^0 y* N# p0 w. h1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
' F; h; J: C& U' [9 g8 Q1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
' y$ D5 E, M" z6 }6 }. B* m1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly7 N5 Q, d r1 v7 x3 R
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this5 I* y2 P m* ?- B" p, f5 K
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
9 @1 U- M6 l+ M) E1 k1 m- G1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
8 ?- t0 f7 a$ w2 u6 Q1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts& A( U6 L" u8 c3 [3 \5 k$ \
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks/ [9 X0 d, f4 t
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out: }9 ~3 {# ^- H
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF; A/ l( s7 j- ^5 O: M
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
: N& |, K$ b9 w3 v4 s1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
( S7 S* L/ k, U1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings( M3 Q1 b: c/ L9 B1 L ^3 I
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
$ O$ b- e0 D9 E! q2 H6 q: b5 e1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized5 l! |1 i8 q, Y* z* K. \& y
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary4 u' j9 E0 Y" X( a( E
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
! m7 J/ O1 {0 W1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
- R: C! ^& ?5 C. J3 ?0 e V1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
) r4 n/ [& l2 o3 Y9 j( q% \2 Y1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None" M j1 b' C* e, S5 @
* M( x+ r9 g& L2 ]: Y8 k R& r
DATE: 11-20-2015 HOTFIX VERSION: 0618 m$ \3 h8 w9 D! E' h* A
===================================================================================================================================
( Q3 E- U' `4 ~7 B$ XCCRID PRODUCT PRODUCTLEVEL2 TITLE5 Y- a# }+ C9 b, a
===================================================================================================================================
; T: B# ?9 L; H! ?+ i7 A1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value. j8 _' t0 Z5 Y" M* X8 U: F
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init* U5 W7 A( E0 P( F$ w& ^
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
9 f- P- [1 f% Q& h" y( _1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle: K. l. f. ~5 B1 U3 V
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
1 F+ P2 S- v5 t y. {) l \5 L8 x1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
. r+ J5 N, U, I9 Q- I1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
1 h. L. h6 v2 e% B1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools1 Z$ O. H9 ^4 l
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
: c% Q% P( F( D S' s, B9 X1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
1 p& \1 K7 @* V2 E; x1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL$ p1 \' h$ V$ Q
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy7 r0 p' N3 |3 u
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable2 b+ S) o' p7 }+ y W/ \; e
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets m/ y' j, s* T8 e
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
. `3 O, C5 {$ z% @5 O1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
; }" Q; x$ t5 }5 Z8 Y+ y( O6 q, W1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only7 t3 a7 ^8 C- W% D* w& {! @ R( ], c
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project# t1 n9 `6 v7 z% m" @4 T, p
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.8 _! R# \0 k) s: v
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
- o( B+ x, V6 Q7 c. j1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
$ z& }0 }2 f# u7 o E1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported B. n% f0 g& @( A% y, r# b
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
, ^7 I" F8 P$ @3 I* @1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
/ ]3 H* h% n3 ?6 C7 ?- t1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
5 N @- O8 s$ d7 G+ c$ X1490299 SCM OTHER ASA does not update revision properly" h! |, z. L' H5 h
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer+ x( v) g4 {# u }* p( d3 `2 j; m
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints% c- ]! q h8 j0 L" r: ?6 _) K
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working( G* C* \' L8 ^/ D& W& a9 D( B9 t
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
8 Z- ?9 B) j2 x. T( v( P, g1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash0 R( d$ H9 i- t# j: Y _9 A
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
% G+ y1 D6 y, [' J/ L1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
6 _% x/ O/ d$ {& ?7 l3 `. l* R& C1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size% b# M0 q! F% a6 j4 T' p
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
/ N+ Y# u- ]$ M! d+ q1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
$ U7 p0 ]' ]. \' Z( e! D) w/ B6 g1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05