|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
Synthesiable High PeRFormance SDRAM Contoller
8 o3 R5 }6 a7 J2 z
2 S3 a7 T9 i" aSynthesiable High Performance SDRAM Contoller
$ d# c0 g5 V9 B4 ySynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
8 {5 O- L7 `2 l3 l4 W o& p, uVirtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
1 t* q! F, h- R5 C+ M% n ESelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high! i( c1 [! _# }3 r& o$ b
speed Synchronous DRAMs. This application note describes the design and implementation of b. y8 J$ ?2 ^9 }5 P5 ` ~
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
+ _7 z: o4 L6 S5 \controller in the Virtex FPGA family. The design can also be implemented with a Spartan-II7 D( A' t1 ^8 l3 f
device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
% p. c9 F6 n# @ }# mand routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
9 Y* X$ J% ?4 rfaster. |
|
/1 
发表于 2016-6-12 10:59
收藏
淘帖
支持！
反对！
发表于 2016-6-13 15:22