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DATE: 07-25-2014 HOTFIX VERSION: 032- U0 z( M R4 Z
===================================================================================================================================' P8 N* T) J' @1 Z. n0 v- ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ p- n0 \0 a3 t# r! d===================================================================================================================================
[. i! @9 l6 r381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
+ R) v; R/ g: q; {616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.
. m- D( c4 G5 _7 P, `982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window: ~: V3 e0 r0 F: k
982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols) ]( k' I7 u2 n! A" z% b. r+ w/ F! m
1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt
. }+ b' C* M8 E- b8 f- H6 y1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data$ E& r; C1 n# _9 ]; [: y; S& a
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
9 D+ }2 C/ m7 i$ [1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks( b1 Y4 `, x5 E* ^( n' Q" m
1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks
0 s, _2 b/ Q3 P6 g1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file- s! M9 Y! n, m0 [/ l1 v
1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly
+ q8 @- g& ~3 ~, u& Y3 D7 z5 S- D1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.% q6 K H) m+ l" O. }/ k, N4 ?6 I6 q( f
1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area" v0 l5 f& ~5 }2 `; M5 q
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting2 O% Q$ M+ d3 I( I. Y0 e1 B" A9 B
1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
9 \1 G3 @! J4 X$ ]1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
1 T- x" n, D/ Z1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go$ T( a4 d" A( W3 F
1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV" R! Z" @- `- `) d
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
* [4 H% \$ z4 L9 X# g- Q1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.$ f; g1 X- V+ y y% E4 T
1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
' p# r% Z& `! k8 t! a1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run
6 p' T9 ^7 I7 ] f: b1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc' W3 C( [; y3 \; K1 K3 d7 M0 C8 s
1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
% I( Q, j U* k3 J! _- Q, I4 J. B0 }( m1244857 ADW TDA Policy File Variables not working correctly in policy file- O5 C5 B3 r: k3 ~3 H" P" }0 K
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM+ f" E# \& D" W$ g/ E1 K2 F: Y
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke, A3 X, h ~! v0 c5 h o
1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.50 [( \. R& C* l; I
1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design! ?+ x* ^0 O) H2 r. S0 A& j8 N
1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page4 X+ x! [5 q" {* r4 a# A: q3 [
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.8 p4 x N: n1 f4 G
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
/ d. n4 ?& {" l9 `9 x1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences., r% A: Q& t9 f
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths
9 J+ c0 G6 y+ d( c: \( s& X( A, o1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design
, b6 q) H; s1 }- s" A( G1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view( E; j- Z; E Y- r
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
/ c% ^# ~8 ?. E1 P& {1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
2 B& j* }5 y. \1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
4 D3 N1 Z: x A8 D a# E1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
! {; e" x8 ~+ u3 X2 K/ w+ [- Z1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number2 e! J' u" F* l$ a
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message; Z0 h' y) a' O
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text) V' }& M! M: Z6 ^& \ ]
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet
7 T, b$ k* O7 v( C1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf
) `# C% h* R- h1 G1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
. b- w( d/ Y6 ~& i, \1 M/ v1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
3 ^: T; y9 G- c! a6 F1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror0 }; i+ M1 b6 l9 b+ S
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
; n5 e0 B5 O6 Y M+ z1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
9 o* X5 K8 I! O" U4 }1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
9 z* U5 T1 _* Q. M! R1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.
0 K F0 A$ l+ x1 N1 i0 c) v6 T+ }6 D1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design, e) s0 i# A+ ~+ j) k0 [4 ]" |2 `
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property' [- S: B5 J: T8 s; R* i
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.' R+ K5 ]4 T( H1 o/ {; C
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
9 _3 b, Z/ S, ], c O5 ]- S1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file2 P8 ] L6 J7 A1 e/ T2 n
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
% H5 q4 w' r/ R. p/ h4 e1 i1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes./ k$ d% ] o: \! Y$ c. f2 H
1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value7 _" ]0 C" i8 k% [9 C7 [
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
1 @. n% t9 ^' N$ L1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project$ W; X. a( H! x! Z# q
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
* @6 T$ s5 T3 c: i- \. U1267541 PSPICE PROBE pspice.exe does not exit when run from command line
% K) F+ C1 S- L6 H& E: d/ O1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode
; M: ]1 j- Y0 s9 J+ t1268299 PSPICE STABILITY Pspice crash on attached design
+ T: C0 Q- h# \8 V1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension
+ u9 N8 N$ j( N6 c1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.9 w& t9 M, y# x
1271385 CONCEPT_HDL CORE Locked property can still be added
, N; X: m/ ?0 m$ t* ]; O1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.0 [: Q% t' V6 h, s. V
1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu& t" h* u" k2 ?
1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.
! v) H5 t1 I; S/ J6 `7 r, x& |+ ^1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.* u2 b& M% X* l. p. k
1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database' Q4 d8 V0 F. K
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed: H, `# c+ Y, d/ `' f
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command, v3 [8 x0 U, ]0 |8 T a
1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
- W2 {. `5 F& K+ w1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
$ H6 S2 ~! |) d/ [3 \$ f9 p& C1275724 GRE CORE AiDT delete another clines
" o* L, v4 ]& `' L7 {1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check+ k9 n) Y: @' @" z( a' Q2 c. W
1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
3 H6 C! T: Q& a) p$ g+ {1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines
# ]' B( X6 w" L5 w3 N* j6 D1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
* j& B; H/ w3 ?1 h s+ l+ {8 E1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
& H+ d, v' K5 Q6 Q" v1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes
; l7 l" X* R% t' v0 E q5 [" m1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away5 s9 Q* d! ?6 q$ D
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset! T# Y9 ^2 D8 j
1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
+ b8 b5 F* Q8 Z5 N9 Z3 O m+ l( }1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC6 P# m, G( _5 n1 H7 H7 v' O
1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value4 D8 t l8 ~# \- F) \
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.; M# ^* K0 O8 G7 t) h! l" K
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update
7 l! h0 y$ ?$ X* u Y! ~, L1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property
# g, z1 E; R G) J" w* }$ h5 I1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines, U/ a' i/ T: U6 A) H* t) M
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.60 Z8 i9 g5 T# L( W; H& e
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.
, }! l. `) D: N" [1 j9 S1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command+ H4 J* _+ n- ^0 G I
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions( [) h4 O$ s4 b
1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
+ ~$ }% y9 x0 L* n1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
6 | h+ m5 r: g- t7 ^1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
. [; }: t/ {7 H7 ?- a. f1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM0 |$ U7 T& v! _6 d
1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid
8 [. N" ~3 F6 p2 ]. d1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected7 \; K% A# m3 K( _
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.5 g6 _5 `7 I' K* C# t! I, U
1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group, H' h" ^2 G# |4 {: E E! N7 ?
1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'' c6 Y2 b5 {9 d2 A6 t& d: [
1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option., F( l7 I0 k0 G0 L' I* Y% j9 a
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer6 V$ Q9 o' k& R
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
# d8 K: j) [( a( i, m% Q1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error& J/ G) d. o3 S. D
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler' K" F, \' K8 A5 W# V( f8 y3 c' D$ q; A! ]
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
% q. f. h1 U% ~. m9 u& Q4 I1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
6 y0 y* q( R# g/ R/ x) W$ M- o1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result
) D+ @2 p+ ?8 {6 p$ I
, q/ }/ H& V1 w6 Q4 e" _3 R9 j# {DATE: 06-20-2014 HOTFIX VERSION: 031+ s5 R. C0 S2 s2 m" @
===================================================================================================================================
% h: C, n' ~( ECCRID PRODUCT PRODUCTLEVEL2 TITLE
% Q% E) {5 V1 g$ Z) q9 d===================================================================================================================================* i) z* x( s9 Q- n, ?2 u' d
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
1 n7 d# V# y( B2 S1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version3 v7 h: {3 T% E7 a/ [' S
1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash
3 K* Y1 O+ @& ] t) s" _! `" \1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.. Q7 i* [0 M% B. A
1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line
. g' R K: W7 R8 O! }+ s) u$ A1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL$ T$ u+ K% ^5 d' U* u* i2 s
1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.( o/ i2 q9 F5 r: ?. N
1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names. |: f: m5 K- ?% L9 ~+ x& t+ ?
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop
& N6 d. N: E) X6 H7 D1284656 CONCEPT_HDL CREFER Crefer fails on large design/ p. R7 J+ D# g
1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design
6 E) K! _' X, R7 |9 @: x4 l1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad
" o+ w# Q/ H* u4 }! ?/ q
, ~8 Y6 Y/ [2 ZDATE: 06-12-2014 HOTFIX VERSION: 0300 ~; a C7 W5 A1 |& c0 }
===================================================================================================================================& |3 }0 X7 Q! _( u# i
CCRID PRODUCT PRODUCTLEVEL2 TITLE* @% F$ O# r f8 u# n
===================================================================================================================================' a& d, R6 X( \+ f' l, a5 E
982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them
+ p: T( y4 \7 ~* \1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application# Q- z. C. F$ n
1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS
, \+ D; @. R8 E' L5 ]1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes.
7 K( a! w1 t8 B* M1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model; s* Q. o4 x. ^5 e; Z; C$ m
1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View); T1 k7 a) J8 b1 h$ E* ^5 ^4 H
1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash
0 q+ n+ j, \/ h2 \& V1 X1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present
4 Y' D- H( O t4 M' ]& f$ s5 a9 I1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file
& a& Z- V; e( f$ N; Y# {& C. h l; y1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue8 V7 x/ J' D0 d* i' |
1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks
2 ?; B; x; w( D, c' s1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes
* J+ N: g3 D# O1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected# k& K' O: V$ ^" P
1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase5 X* Q& a6 G0 T8 n: l( P
1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly; ?$ C3 J* n1 Y' ?* u0 `. l) y
1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.1 z% ^ ~% h6 o' h
1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser, O* K4 f, i4 v" p" x3 G! ^
1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path% ^3 C0 _/ J! a* C/ @/ T, _
1274661 CONCEPT_HDL CORE I can't copy a property from one component to another
! A% |( x4 s5 @* r, r4 [1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board7 }' H8 _) G4 ?3 m; _( q% M6 M& z
1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect5 k* [2 c( S7 v: W% f& l
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard
2 C( f+ Y3 C1 m; J# \5 v4 ^1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move
! R* R# K V9 B9 g9 x% U$ q( e1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring
+ {( @, z d6 T p1279258 CONSTRAINT_MGR OTHER Import logic stops with error5 b3 H% ~+ n8 E9 r9 f8 x
1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor$ |9 I) n% G* z, O4 U; Y
+ U+ t: n5 K) p6 V0 f$ tDATE: 05-23-2014 HOTFIX VERSION: 0295 L6 Y+ S& c( s8 [! M. p
===================================================================================================================================" J5 L9 j* I/ S$ X: E0 X
CCRID PRODUCT PRODUCTLEVEL2 TITLE- F5 [# a6 e) V* Y
===================================================================================================================================
7 g. m2 f2 X! m% x. i2 N1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs
9 z! w& l5 A7 u2 [1 t6 N1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.9 F& ~, \8 {0 y
1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid3 `4 F! x1 ]* X- J+ A4 p
1267602 SPIF OTHER Route Automatic hangs
: h# A% u( `. ?# `1268022 FSP PROCESS FSP is not respecting the use banks for attached design.5 F3 K" P1 \; i, V/ S' p" U
1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581: _$ a* y8 g& e7 K* V2 N
1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data) U- \8 ^9 L z+ p: P
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes
& l Q _. c! N" [1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations
; y' J8 E# B: v% q/ w1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem
, n) Z7 C/ I U- A+ ?1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle( b, d- y6 E( F
1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design5 v# e: x: T. q3 O" k, R
1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem
r) g4 S' @3 N5 u2 m$ m1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?3 O5 `* ]1 s9 i. H. h- J
1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.7 ?5 f! _: _% i2 i- h# k8 t, l
3 l9 E$ [2 w* b \
DATE: 05-10-2014 HOTFIX VERSION: 028" S# T1 o; v: ~% f
===================================================================================================================================9 z! I6 M+ }( o$ w: j$ K: T
CCRID PRODUCT PRODUCTLEVEL2 TITLE
% ?" H- p5 @# s0 [- p f& Y===================================================================================================================================. x1 V) }: c! O
1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols* E7 P6 t/ m4 {% v2 s0 W$ W
1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.
* O. z" @; q- c1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.5 s- a) `8 Z) H" x
1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?. C/ A7 Y7 r) D0 f! N- j" J
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages
: K! A" }! F3 M; h1 D# d1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option
; T$ I1 ]# N, A& h1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.) C" s3 |) W! a6 p8 T
1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.& \9 `" j" \8 q1 h7 S" @9 s; { X
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui
2 F. K( c, @' q, x1 v1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule9 N* q( ?) y* U
1262560 APD WIREBOND bondwire can't connect to GND ring directly
1 F$ I! D/ V1 U) w1 A0 L7 \$ L1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
% P0 T& e7 A2 c7 S6 v9 H, q( P( d+ d1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
4 A- s+ G( X2 Y/ q+ V0 P1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design
: n! a! {* x( u4 |9 J8 i1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.
" X2 F2 ]' ~. k l$ Z! g! u1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.
0 u/ e5 b! @' B, A1266687 ALLEGRO_EDITOR SKILL The SKILL p/ M m. _ x: S- y% i% d0 j5 w
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
1 B2 p* s* j9 T+ s8 d5 @1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
& i, ?' J) w3 q5 I9 |1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path." `" X9 r* C n0 a- C3 B" b+ _2 B
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.% R, Y1 B- c2 ]! b7 A
1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
, s5 t2 Q D1 s" a' a6 L; E7 Y* A) j$ I
DATE: 04-25-2014 HOTFIX VERSION: 027
9 r' y. O# I/ L===================================================================================================================================8 o8 a0 c3 W9 V
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ W1 d) x. y' Q2 Z
===================================================================================================================================* R: r; ~5 |& p# C; e2 Z) b
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
4 ~* n R: S- o481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in! I5 a E* s% z7 l
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
$ A1 J! d; W& v0 I! O1012783 FSP OTHER Need Undo Command in FSP7 E+ v( t0 n3 B9 _, I$ a
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
% a) O W8 \# S1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved) V8 G. d6 @: ]. |! P' e
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
: R4 ~. M ]* d% W& p! s1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups& D+ d5 c+ |, X( L5 `4 X2 B1 J
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash( N1 n; F& I( ^' D; v% N
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
- l3 {' k2 Y+ s' P% V1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode) K3 J5 S. ]$ W4 q
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present% T, i6 ^6 T/ q/ t0 ` ]
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list. n: F X( h( I b# T& m( M
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
0 a6 G2 s. `3 |7 \1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.( j! E, ?) m7 P% j9 ]
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV. y+ }$ W% K3 B0 X+ a3 P5 u
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
- _' q# G6 p v: A+ s1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
6 x W0 W7 r, T$ p0 A1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
5 R- u$ {2 W' n& I# |+ R$ Y1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
8 _- T3 l- e: M. H S; j# y1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
" r8 i$ R4 N6 e3 B% z! P& B4 w+ f1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed9 ?1 w/ v# S# k4 I2 C3 m& m- F
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
4 a5 l! b# x- Q6 d6 i1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers4 W- }6 X% P9 Y9 M7 T& Y: A
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
# o( T/ h0 d$ a5 X. p1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
8 J5 D; {* q3 ^* U7 X/ ]7 {: T1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values" o& w/ a& S: i% U8 ~1 s
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging/ L' q% T$ u0 t9 J
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
1 E; M- B `+ ~* w3 [1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
9 x m2 n' B) H% X2 _! U% r1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
* y- p5 N) u# ^' Q9 n1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes) U. @6 @, B! _/ T2 m/ Z+ n; j
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux) E8 k5 }/ N* u0 Y4 i
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.7 L+ S" \3 H f
1221182 ADW TDA Team Design with SAMBA
1 S9 a% Y3 N: _* Y5 G) s; ^1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
F- } @- q7 @1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened+ Z% l* \: o+ m( G
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
8 f* I4 k5 q& u" Z) i1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
8 R/ \! ?4 O. @5 N+ F, R9 N3 ?1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms- m) J' o# G/ L( K
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
3 n( B3 I# V" N1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
8 d) Y9 g* R8 O: b2 J1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
# I3 U4 X; Z7 f, D1 u5 l0 t1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path! X$ i; ]: ^* I! m5 K
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin* G2 O% U1 K4 B! O) e5 b3 g
1225494 CAPTURE DRC Different DRC results for Entire design and selection
+ m0 A- A& L- v, I# j1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property2 t# D" V( u4 B; C" G
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet$ \9 @; _" \. l7 o; G
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet' r5 Z. J) _6 \1 L' y
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal
$ n7 g* S4 g& a6 Y1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
z$ X7 T8 _* b$ b: c/ G/ Q. Q1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors6 b' l( a' i6 c' R" N
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,80 b4 a! F7 ?% }) m) k
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
3 R8 }; c; F% t, m3 B& R, {1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
- c# D0 Y& d! q; G1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
s0 r2 ^" n7 m- r, B5 I1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
$ S8 T8 b& k, |8 s% x1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
0 z/ [2 t& _2 v# ]1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
% s% `, @6 f8 p- O. P: B* T& N6 V$ J1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.$ s% Q9 Q' O8 d# K0 s4 M" r# W) s
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).1 O3 @4 p0 T M
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM( t K4 }$ ?9 ?$ R- D* z( Z
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
# x; b; Z& o1 r, \3 }" A) |1230432 CONCEPT_HDL CORE No Description information in BOM
1 v' E/ |' P! k1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
) f l+ z ~6 B9 [ S1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
6 Q% V9 N: [+ c4 D8 a: U$ U, g1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
4 c: ]7 G. p% p9 E1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
5 E9 j, d9 p8 k ^( g( y$ [/ `2 g7 x1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.4 Q. I* s( J& E
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode1 p6 n ?! b+ [
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
0 m- ]1 F. h" L8 @. J S1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
+ |% t8 H! N( x" l1 J5 a; d! P1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
0 y, e" o6 h! n. E( F' ^- D1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy( N/ {3 K0 C$ W- J! m0 G6 J; ~
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved0 S: R* d/ i; F- z5 r
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect) o5 }- }) E" n* p* P" g. I
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
: g' T. {4 i) h6 E" w1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic# Y3 ?, V6 X7 Z; _* V
1236161 CONCEPT_HDL CORE Import Design shows the current project pages1 k4 C- {% q' J! i
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.4 ~/ ~ o' A9 x$ C# R0 ?. u; D3 X
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
) }; S \/ o9 w1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file9 `5 L8 P7 g4 R# I6 Q
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape& x" L+ k: ^, G5 _4 F( S) e
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
5 m) v/ {5 W# L1236781 F2B PACKAGERXL Export Physical produces empty files: V: R& \; F- V( n- L q% W
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
, ?" v4 t; z, z ~: P8 |1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command r; ^3 ~7 D! c7 L" `
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
) j$ s8 c7 d7 e4 n5 ~9 T1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
0 Z4 V, X: d, g4 |/ Y# M# u- [0 R" B1238852 CAPTURE GENERAL signal list not updated for buses; _, Y. N2 L' y& u1 y( _) l& ]' }
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes- T- T) M0 ~ F1 x% s
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
1 _0 u$ }. U! h% r0 g9 X: G1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE" Y. V, _- ^8 P! Z( @! I4 u' Q
1239763 PSPICE PROBE Cannot modify text label if right y axis is active
G4 o6 d$ Z5 z5 l" i5 g, R9 W1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
! S% y2 v/ e$ o5 {1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
3 [3 F& r- I1 k. A7 v# ~# E1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
) W8 p2 w" O! _* m5 ]: Z* c1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
& X O5 x' ]) @4 _1 v5 } M- ^' Y1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
, T+ X5 X) \1 _7 H4 r: }1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
8 c: F9 K9 g. M" ]" }: i1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms) B/ E8 p" T3 V8 O! F8 @( w0 }
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working/ e9 H, [; n7 h0 W; ?0 r
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.3 F4 t1 ?' o& ~! P6 x" f4 X
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
* Y% }8 V9 j* i/ u8 M1 S1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
+ P$ f: X* s2 h5 o8 N1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
9 P1 @ O# {$ Z1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
2 w+ T6 h0 Y1 D( W9 G1 V ?1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results- |, q/ `, v' [/ E
1243609 CONCEPT_HDL CORE autoprop for occurrence properties; S! R. @+ P7 F6 e% c' }
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
0 k; k7 P+ H6 T- u# ^1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed., ^% w9 y' c) _8 ]' w- |' p8 [/ b T
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring( E1 V" k4 g$ c: T( @
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder# R/ F3 O x; X- @; j* d
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is: Q& d! |' k2 h6 ~1 S- P5 T$ j* l, e
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
; [0 d; v* c0 o1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?5 @! ~5 A2 U) a
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
4 y& Z! \' w, B/ g. b4 G1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
7 l1 o+ k. o+ C) n3 \1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown6 @) C# z7 ]' `$ ~* C$ a
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number$ B8 ]) [2 c" w, u2 X& u/ d
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL( j9 v3 z% E J0 s! t: t
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
( U+ e5 F( c, \' b0 E$ B7 `& Z1247462 CONCEPT_HDL CORE Text issue while moving with bounding box2 A9 [2 _' H0 W) K
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
, ]; {4 A; _0 H' F" f9 ^2 }+ G k) D1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
% n5 W2 V9 q, r6 a* }1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
$ m- N$ l) L/ q1 M/ k$ m; r* e! y1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
: }) |( N8 [3 |& E! Z' P' ^1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint3 E+ K8 d& e l' s
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
9 ]. r; @/ A$ }1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
6 S2 B# R2 @; E7 \ \ {3 d1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
# Y+ ^; H( ~# w) A* i. V6 {4 g6 s/ |1253424 SCM SCHGEN Export Schematics Crashes System Architect+ I# D8 K6 p5 f/ z$ v" k! O+ p
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled+ @( \3 C, n3 `: a
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
, p v4 l7 k# ?- c3 {9 A1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router$ h5 t5 L, ` ^/ h% ^
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error* ]# X0 M7 |+ [ t$ f7 o& L
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.% C1 |1 S( H& T \( n
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
7 ]2 P( M' t/ Q1 o1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
/ c9 x/ ^6 A. g1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
3 a( j/ A/ ~0 S. C- M4 o8 G1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided3 o6 D5 e( j8 D8 U3 A1 a$ a
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE1 s2 [3 K1 N; [' W# s5 L( k) n/ r
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
5 K) o/ V' u1 L1 M1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
* V" {# O; [1 m$ w. o1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
) e+ o( g( O4 A2 r" ~2 `0 O. w6 V1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long$ n8 b& v0 ~+ l1 F& @
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash: v1 L9 B# P2 L* T* @
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
+ u0 _+ ^3 P7 u7 i5 I1258029 APD WIREBOND The bondwire lost after import the wire information9 o; T% q: w+ g# A2 k9 a
1258979 APD NC NC Drill: There is difference of number of drills.
* z0 Q' K( I6 c$ @" t. r1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement0 P6 n; ~# h; [4 F# V# F& N N
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
3 p" H) G+ ?5 q( v3 q, z1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"' V- q! p; W6 y5 ? S) B
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
' R/ r1 k' M' T0 B7 P1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
6 X; t* }/ r8 C- m: q; D n g" b1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
0 {" z% a- y c
! z3 v5 X, u0 U o" FDATE: 03-28-2014 HOTFIX VERSION: 026
/ E/ T! N" u' {5 f( p# S===================================================================================================================================
: P( `. s& S+ [! [% J, s6 M9 WCCRID PRODUCT PRODUCTLEVEL2 TITLE
* j. K. D& f0 A5 O4 S===================================================================================================================================
' D/ V4 r0 P* k1 ?; A% r3 {1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files$ s. m& A% j! X7 A7 Q
1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT
5 g3 w4 }2 y! j' _0 d1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor( E, X& T# d7 Q5 B* I. u
1247432 CONSTRAINT_MGR OTHER PCB Editor crash* K8 _. }7 G I1 a
1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?
9 u6 T: U0 W. t0 k5 \1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position) j) w& r# S% ^% O
1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.
4 {5 ? F$ w! I! r `1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor
, P$ d! p- ` O9 F5 J1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE
. n8 W1 ~$ d9 y5 I2 q; F: @' K9 J: u1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file- Q/ Z- Y& Y0 @/ c7 W3 ]
1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.
) h. s* x2 o% O1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted
: ^. m t, F2 }8 ?+ q# U1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property& e- M7 w8 _& O. h- A' ?& c3 |
1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output* R7 A7 w! K9 T N& C
1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol
& l+ \+ f/ W- n: v; U* l
5 {. W+ D- r3 CDATE: 03-13-2014 HOTFIX VERSION: 025& ^8 I0 ?# ], Q* P* M
===================================================================================================================================, `. y9 G; G: k+ ?# M" _( [
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ L7 J2 y+ r& a d( Q0 i S7 Y===================================================================================================================================; b1 e- P( O6 ~2 p* V
1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work
+ a/ W# A. r0 P7 }2 e, ^* X. X5 X1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.
6 h! k& k- C) \) h w1 I1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues
+ v% x3 o7 I! H$ J1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection5 {% i1 ^1 o2 `: H+ M
1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry.
1 D- x, }4 y/ O; B! G4 R1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin
( P; j3 w! ~5 ]. F1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing! b. }* w$ v; t& F0 l; r: V% _2 W
1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design
o0 n8 N! d$ `% U4 R6 S* ?3 c1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore.% F9 @" F" Q8 R4 W
1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name8 v# p+ ]! @) Z( ]1 [% f
1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode
( {" U2 V' _! e- z: T3 A. v1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.
% q$ S" P/ E2 W2 K. @) g: v- I1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save
! ~# L( ]/ L: z* ^# N+ P1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error
3 ~ p/ `: q7 k, j* f& {1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022
5 D+ W! d4 ?8 R- {1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design6 l3 [7 N( `$ `3 O% r$ [
1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash
4 n* e4 w4 ^+ E/ o1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.
! [+ r' F) K% c; a4 R1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.% L1 X) N* {- i
1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field
/ s. y- D- s$ p1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center
/ J: S/ b2 K! |. A% H. f1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color
. Z1 d+ v1 L; `2 E
0 |# D. w- s; X9 t; SDATE: 02-28-2014 HOTFIX VERSION: 024
4 ]% o% E( ~; M* x7 |+ g% F===================================================================================================================================
; P- t. x W. |4 p" u1 K4 V2 OCCRID PRODUCT PRODUCTLEVEL2 TITLE
! r6 Z7 \* @* q) @& Y0 v===================================================================================================================================/ B" u9 }; q0 L( N& i# E$ l
1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d
& {- S% t6 y9 f7 D9 t9 m1234991 ADW TDA Team Design does not remove deleted page files from zip files
1 [/ ?$ w# A+ h7 t( f6 L+ h1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components8 s, X% y+ u+ j2 w7 v2 H" @
1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition
# k7 K* m! E/ U; T1238140 CONCEPT_HDL CORE Design Entry HDL Crashing+ x# e7 \' d4 D; z, }
1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.
8 h5 X) k! e- R. G9 P% A( o1 Y1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value7 U+ n( K) B9 Y/ b
1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.. |& V9 c: A; g h# |7 h7 \
1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
$ q$ D9 X. m, f6 C- h/ _1 X# O) n1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data W, w8 Q; B1 a" a$ y1 H) S! V, C
1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135./ g6 K5 J) a: \. M8 U
1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP
4 z3 C2 A2 G& q1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?% u9 u r& q; s8 f* T
1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented
* i4 L# z8 X# L6 g: n1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22" W; A. D) x g( ]& x* k9 c( W; U8 d
1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166
6 r5 h8 T# Z# K2 O e0 N1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.8 L5 W" c. W8 T6 T2 |) W& V" \
1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23
& X4 f6 m4 u% O+ L0 @' z: o) `1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements
* ~0 T$ x* i1 ?0 |& Q1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip
& Q% ]+ Z/ |4 `% A8 K1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021' ~4 b/ Q2 c* N ]: R8 k
+ n9 p( h' P! n' L/ W1 F5 J1 X# MDATE: 02-14-2014 HOTFIX VERSION: 023
" f7 ?$ T2 N5 W* N+ {/ S2 M5 Z===================================================================================================================================. u; J0 N3 m5 b
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 h# V1 D: ?% J* V: v& m
===================================================================================================================================
7 K, f( l" m& a Y+ H: u5 E" e1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
& ?* g# P4 c9 R2 q- C1202715 SPIF OTHER Objects loose module group attribute after Specctra. L, K: R0 M' }& Z. W3 |
1203443 ADW LRM LRM takes a long time to launch for the first time
8 w" ?4 X* R7 D5 v k& k1207204 CONCEPT_HDL CORE schematic tool crashed during save all* x6 _% M- G2 M$ G
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter4 o# C; O7 Q/ a$ U1 Q7 e
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA a' z( D! p, N8 Y/ u- U9 a* l
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side. N/ E; v. h, z( G7 i7 w7 w
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
8 v4 s9 F8 [' V# i/ \1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.2 s5 T' H f( H( ?! `' l# t
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup5 [ }; F2 N) m7 r" P
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.; Y( z& H1 `- @# f b5 G; w! s
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7! }$ w( d" z8 i F {( l
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's, }- \% Z" z l
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.; d; F" k& c0 x. C* f) c
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
* Y$ \* [1 Z, Z6 ]7 m" B- k1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form) I, ~" h+ i: U$ |1 o! a
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
2 q$ d2 i! X% o1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
* |. E3 l$ L1 c) m1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
5 G7 C0 y# f" d: A& ]; L1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.8 y: [9 w# t0 g0 u, u4 K( a
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
% h$ K r& b# i1 m" L' N* C1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
) I3 U1 r3 q8 K1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File" ~' @2 h* G: m* N
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat
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$ R; o! @7 U6 J$ ?& {DATE: 02-7-2014 HOTFIX VERSION: 022" M/ A$ \0 Z5 J7 L) v3 _1 w! R
===================================================================================================================================
% `! t7 g* O& q/ S6 tCCRID PRODUCT PRODUCTLEVEL2 TITLE. r# L9 I+ P J9 w: C& c* w5 M% p( n
===================================================================================================================================) q7 W- p6 k# l' l' g) I; b
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
# g% V& l& [& T7 e222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design
/ J6 f. O0 S1 x274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
7 @6 q4 N6 b5 s, J% c413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
" o8 |) B M9 Q J8 m609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.# ]/ D- e+ W; E# e
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility P) S% {, H# `+ ^" ?
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card% C) N, a" E2 b5 W: ~' N1 `) a* A
982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor
+ ~3 B3 P! z. P0 O# e1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list)/ B$ t6 B6 M5 ?% |; p4 n" `
1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.
2 s* n8 s! n5 T8 l% Z/ y* B8 B1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design3 R0 Z* e0 H; t }" c( V
1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility
* u9 _; s6 `, r6 o% @1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks
: N; R3 p3 ?* J7 j" ^5 Y/ s3 l" N2 s* H1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
" s4 q$ ]' W0 s' r9 [/ s1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs. k/ w& A. o0 N; u {/ _8 E; Y
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports9 T1 c3 B9 r( t1 t7 C/ j& a
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.
" e5 L- u! x3 ^; P1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge; ?" d+ K, U# ]* }
1147961 PSPICE SIMULATOR Simulation produces no output data; J2 h: o; w9 }
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation- c6 ~, k3 s# r+ x( O+ F
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.62 P; G3 Z: P) U
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode% _% h- H& ?4 a5 _6 X; u
1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
4 `2 T/ I- V/ f1 D3 e5 x7 g( J ~8 A1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly* n x" P2 T0 v6 D2 Q7 o
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors. f, L2 [9 K5 n1 Y& t5 J* _& b
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning7 j3 ~) P" {3 G
1172043 SCM OTHER : in pin name causes SCM to crash
9 k, G9 I, t! z$ t' r1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet
, l9 w& t, Y. I1172743 ADW TDA Allowed character set for the check-in comments is too limited
: ]7 O, u4 M! a$ Q1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
5 J, J- W( [, C' z# D/ j1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process
6 M! w* s! O: N: s2 r: ]4 \9 G1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible
3 s3 s) X3 R" {) x" r% P! X: {3 m1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM7 R3 s! O0 K X$ M. t* K7 m
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD" _. _2 o+ ]2 q+ @7 k
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue
2 a4 H0 F8 d6 k+ \1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells
4 z/ |. l1 S% S6 A, e/ j# C1 {* B1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.2 ]( w0 a+ N, ^. N
1180164 F2B BOM BOM csv data format converts to excel formats+ b w$ b1 S$ K( f
1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section
$ f# e( s9 i) m f1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet2 B" l7 u2 _( C3 q
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex
/ d. j( B( F+ D6 v r( J1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.
9 A# P! C; k7 ^0 [) E2 T1181739 GRE CORE Running Plan > Spatial crashes GRE8 K: S8 S0 G0 G$ a
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors- a; u7 Z$ U1 M" L* Y4 k
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet+ }4 \: P+ O5 Y6 @! P
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
3 a- r% A, W3 V6 i+ _1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.
! S8 g l' C6 E0 g* l! x3 A1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement7 ~0 t4 h7 o3 ?& }, ^
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
, j6 A! B# ]+ j6 E6 ]( l# }1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing) t* b5 M4 z7 I7 i8 |" H, L
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC/ k1 m. g+ s. T0 r; V
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 20130 }) n! D% |' Z1 T
1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward# v8 ]! g1 T: r' h" `* c) \
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"9 J* i* v% P5 I' y8 s
1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.
/ e! e( Q# J$ C+ a1187723 FSP PROCESS Synthesis can fail depending on component placement6 y: \% r: C. @; W1 W5 {; Q
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP
) P% O/ W8 ~5 |$ S4 L1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic
! g8 @* J; f" V, d7 p1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin. }" d; Y7 O5 p
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers* c+ I" B$ r: j
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file
% ]6 b0 L; S: v! }- I" x1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia
4 \% n- b& m6 \1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.. J4 f g4 c. s0 b
1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
1 }, ?& T2 V7 S8 ?0 b4 j1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info
8 K5 P9 C( T" K6 O' s3 P4 s7 t1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard
" D. a p0 I. R* q) L1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache
8 [: S- J- I6 r* B% C; ^1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports
* Z+ b1 n( j8 r1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers
' z' P, Y# v2 h% l, `1 j1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet9 g, X' c- t& |1 X1 b$ X% m0 _) m
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview* {# R" m/ h1 [4 s0 N$ C
1197543 ADW TDA TDO does not correctly show deleted pages8 } z* q u& |6 |
1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled
9 _# j) G# c9 ~' E% G! ~; F1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.9 ~8 p0 \. d; J8 y; p7 L
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM
. _4 U6 j1 c1 X, T4 J T% Q1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.3 n) I+ x4 I f {4 ~. ^' I
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.
* w+ l. T% _6 g$ \# Q/ ~2 A1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick% Y: H7 h- }& g8 T3 h6 g
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file$ ]' \- b/ j1 Z1 y5 z
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup+ y. B) K( W1 s% q6 L7 n' L
1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object4 I8 F$ Y) a# I7 \& [( T8 D
1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout
f0 h1 q% h/ }8 V1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option
3 w8 C% Y, ^8 P1 L( ` T1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.
3 O" {# J# t9 |* M' [3 e$ T8 x1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.0 i8 g5 ~" P$ ]/ F. M2 ]
1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file
9 u% T% T1 d) i5 _( s) \* w7 N1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax1 g7 f/ n) u9 u3 L+ h
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled* G( t; t2 m, o) f
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data9 M7 I. P8 N4 K4 O
1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�3 N' R3 a/ E+ u3 O) A
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View
v2 ~% T s8 B1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus) F8 X" ?+ \& y+ B. u
1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly
3 J& a/ ]* }( w9 g& S! d1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working
$ u" X3 q8 }9 m3 h1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color
/ H& _- P6 a5 ?9 F0 N1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant; w7 N* C4 D% d4 p$ q- s( Y L8 k
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
( @2 J1 ^' C i5 a1209769 CONCEPT_HDL CORE Top DCF gate information missing0 d; H. q3 q3 g
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
6 u6 ?1 Z6 ^/ z1 Z/ ~' Y$ q1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
, E u: o K t/ T) l% C1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite
5 u: y, q/ r6 h/ B1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
8 d p/ V7 c1 M' { o( A3 J1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file6 d& s: s9 G0 f6 z) _* ]3 U
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
, L/ s1 U X! `6 l8 `9 V% \1211620 ADW COMPONENT_BROWSE Component Browser Performance* z; M# y9 A! e
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.* J- k4 P- R7 l8 K7 u: E
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
" [( R% x! {7 [' u6 w1 b, X1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.3 ]" J* A# |: T7 }
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition
q& O/ I+ X5 _. A; O1 _1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing
6 D; C& q4 o. w- t% V& Y# F1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option8 @% H5 @& F/ a
1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic
* t/ _- f- o9 n. Z3 L- Y1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills: `0 o. S! I5 f5 d+ N! }
1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
- G4 H9 m# `% r' [; x! M" U( N1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net9 ` e* a J; M% X/ [' b, |
1216328 CAPTURE STABILITY Capture crash
/ s6 _: | {3 S" y# G8 A6 m% V1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
! o- [( b; G2 ?! u0 Z( W1217450 F2B BOM ERROR 233: Output file path does not exist# o" T1 u# {$ p. d+ \6 u4 F
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB374 p/ }6 ?/ D; @7 {
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473% N8 N8 C4 _" H% S/ y4 Z2 w
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window; B0 @ U0 F4 n
1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface7 X- b2 h% x) Q. w' M; q+ o
1219053 PSPICE PROBE PSpice crash with the attached Design# n6 ^# X2 F: S' g9 U! E5 s
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable) L0 f/ X$ r3 f& I3 p$ g
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board
$ ^0 C* a8 b+ S, z0 {1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()& R& u" p" q3 C6 |" g
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found
: c5 ]! F: G8 q2 l! ?/ z1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design; R P) _# P% V+ [$ w, a8 z
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair
2 |- L$ A y8 k' ]; H1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip
; W* Q2 u8 w4 m0 ~& X7 b: x1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.1 H& L3 L* e$ J; |3 ?
1221416 ALLEGRO_EDITOR DATABASE strip design for function type6 n5 n2 h' k+ L K
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component5 v) G( t p! e% M5 R
1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.
) u3 O8 @# l0 ^3 s. f1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.# y1 R _ h6 @/ p' e) B, k$ n
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup
4 d( Z+ t- x( P7 F3 z* M2 v1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
. Y2 u" \# T) a- M7 H" O2 j) l% e1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
3 B5 s' _2 x( a7 Z. I1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol7 a. @+ L- L Y4 U7 F" u
1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1* s2 }7 j. A& k: n0 q) ~4 u
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
# y- K1 I( ^+ a% x% @1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?2 T& t. S' ?, `% _! |: u
1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again
* F5 i ]. A2 ~) y2 l4 o1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
4 R4 B* N& R' ]( ^8 X1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
: l8 v w. x, N. M( |8 N1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL' L! f" X' w7 ~2 d
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer H. P0 _/ t; M$ m1 L: a' ^7 p
3 M9 f/ `6 h% V
DATE: 12-20-2013 HOTFIX VERSION: 021
U7 t* j2 k n! S3 t===================================================================================================================================
# b% T; H, H/ U/ R9 ]* TCCRID PRODUCT PRODUCTLEVEL2 TITLE
9 x. V( S/ Q" q5 b* u===================================================================================================================================
6 o. A$ X$ G) J) ~/ ?1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.: b" ?( f$ g- S( K }& R$ i
1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6) J6 h% M; \& Q8 q- w8 G% R
1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file4 Z( ~7 l q# _% f
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.( W! ]2 h/ C, r" T8 ~. a: X
1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape
6 k, @) d! Z' F& R1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols; I$ Q' E; M) d6 P" B5 o# N
1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM/ I8 n! }+ y* ]! W) T/ B
6 P1 O! i. q; ?- |, u+ |
DATE: 12-4-2013 HOTFIX VERSION: 0206 {9 S! W. o* r5 U$ m7 C
===================================================================================================================================
2 H9 N- p" Y- w, C iCCRID PRODUCT PRODUCTLEVEL2 TITLE" L! I# S- i2 T. _4 y
===================================================================================================================================
6 T W$ `5 s6 S& E. t8 d: V1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.34 c6 O) {8 `* b, E- K
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1.
( Q |9 n$ M1 j1 V, r+ i) `1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016
! ~7 X6 H3 l) ?, ]; B& y( z- L; f1 k1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s0166 h+ N m' |- h6 z/ H
1199700 PSPICE NETLISTER Netlist fails on addition of netgroup* D$ ]: E% i8 V
1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line
2 D; \4 Z2 p; I; O5 h1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM
4 G) M6 S, Y- b& r1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.
8 y7 E% o0 y+ {% [8 r5 C1203143 GRE CORE GRE crashes on running Plan > Spatial8 E$ Z. @) c- T* h% f/ I: c
1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017
T. e6 R+ X' [( y3 R1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning4 Y% C+ a3 |, T* l2 }: }
1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color
, a& m! h! p5 u5 l- \" L) w! ], U1 R1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found6 w1 X5 c2 `% p5 k* ^) w
1208276 APD STREAM_IF Stream in fails to import what Allegro exported
3 Z2 q v% g8 g1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?
/ m6 b% Z, y! O5 ^% }( g. ^; w, _1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.
! W9 M6 Y9 l" a1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table$ p K- Z# W! }; ~
1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting* V0 ^7 h" C! W
1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro& ?; K5 B4 s% x: S8 `0 A2 N
1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design.8 X9 X% J) ~ k1 W, E) _1 `1 B
1209902 PCB_LIBRARIAN CORE PDV crashes reading part
+ I2 K& i# r' Q. f/ B. d1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message/ F/ ?* ?0 y6 X* l) _
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.
& \& \, ?0 d8 T. w+ s' y1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers. z9 ^9 ]% r. E$ J9 @
1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.5 ?& j2 j7 b2 T8 y- C" l ?* `+ v
1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.' J- r) r. G2 m
1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048
2 D2 c5 X! \& n0 L0 n' Z1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting
" B h1 [8 m- F, A' u0 C6 W F _8 u1 [ r1 j
DATE: 11-15-2013 HOTFIX VERSION: 019+ h/ q+ e# ?; W3 [& k
===================================================================================================================================0 n% N* R* U, @6 J' Z3 U+ z7 l
CCRID PRODUCT PRODUCTLEVEL2 TITLE* ]& U- }, j0 _. i
===================================================================================================================================
. a; ]0 w3 L; X) z2 h$ Y! @1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
) d6 F- M4 _ f4 M" c1 u; [: d& [6 e1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly
2 S) ~& P) q% S$ V) I1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device./ s1 p6 o3 F/ I
1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings/ r$ h3 V2 t M0 `; G
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.
! T; q; {# q- z1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected4 \, e) Y7 e% W+ X, J6 F5 r
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product
7 j" {( R7 j6 A/ t0 C. M4 [' S1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
1 t u( V z1 q4 H% Z4 [1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
. C$ ^/ I+ e" ~1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.1 U! N3 O& Z4 z: v# w
1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping% P& V. F2 o1 P- g% T# q
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.) {& n6 e* o0 R! _ j* z% w
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro, E0 y, Y$ p! z0 T4 Y9 I. a7 R
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode( L; N' b" T# d# Y
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.
3 B7 n( C/ M4 [3 T9 i1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.* N& t$ l; {: C9 \6 j* R
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs3 w2 |* l# J4 ~4 u" j
1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017 j ^& E W+ F# d: @% K" C
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor
3 \0 X' R( f6 D6 g+ L3 l1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout
( G+ g$ H! _( e! ^7 S4 d( l1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor2 G" j1 J1 ]6 u
1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct5 g% q) r! f" i0 Z0 P
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
- W5 N) H* o$ U, y% [% j; b% a" W1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error- b+ e/ b& o8 P6 k5 ?0 }
1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails; {0 f# z# A( J4 n# l% h
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
" l8 }1 [# n" E) N1 { ~1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.
2 t/ A' \0 M* R* Q/ V8 @5 k1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
0 r9 k8 ], c6 {1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor
% T& b8 c+ r# O$ |9 E1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.. `" |' {: T* T/ l7 W a# ]* G' C, y
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro! z+ n# L' y% R3 z, g& }0 S, V
$ v$ ]3 B0 r3 |! h) O
DATE: 10-25-2013 HOTFIX VERSION: 018
; t! \" F' D) Z4 N, I8 q0 A===================================================================================================================================
7 c' X% l- c; C2 u% k8 f# }CCRID PRODUCT PRODUCTLEVEL2 TITLE! {% ~; {/ p+ K5 _: a8 H
===================================================================================================================================0 V$ X1 F/ G( U4 j7 T+ T" }" `
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL: u6 E- p$ ~( a" w
1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl/ b% l$ B5 w0 Q, {+ O) h
1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.
* y7 ^4 E2 P; M4 y* p/ {1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.
2 \5 A2 V0 ?. Y G4 e, p$ n2 G1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.+ X- A3 B8 U& \! z2 `
1189100 SCM OTHER Replace part in SCM using ADW as library fails
& U+ E# h9 T& l! X7 F( Z& D1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.; s+ X9 |/ N3 o: N$ ^. x; P: H$ p
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks0 E4 Q% K% C9 \4 T! l
1194597 FSP OTHER Pin definition problem$ h4 C* F I: W
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
% d0 X# `; N4 K" r' j$ D, |1195309 GRE CORE GRE crashing during Plan Spatial.5 r2 G' C) T8 A8 q3 H7 y, W. I
1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank- u, Q \7 T4 E; x2 A
1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of17 }( ~6 Q7 K* j+ e+ l+ w( l
1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped) S* N: j* p% J# l
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
( |( G2 O' W; j* j4 l1199323 GRE IFP_INTERACTIVE Crash when importing logic o1 `; A0 w' C9 C* {' {) v5 ]
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
2 R! i) ? b9 V. V y4 f1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer% h3 I; z1 M- V3 o7 X. m& Z) }, V$ B9 K
N4 l! u7 T- z
DATE: 10-10-2013 HOTFIX VERSION: 017
; C8 ~$ b. U' m8 Z! E5 d- A0 B===================================================================================================================================
2 T7 _: O8 h3 s- E9 ]. `/ xCCRID PRODUCT PRODUCTLEVEL2 TITLE- `, X4 h% g6 H& @/ H' c g; p
===================================================================================================================================
: y! _' N$ `& i/ i735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type+ Q O. w) }* l# g/ P; @8 @+ r
1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
/ w+ N8 F9 l# G) Q/ _' B1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing( ?, B6 Z- K% r+ n1 p; g1 C* d
1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.0 e [- J1 `' @- r+ X. s9 ?* v
1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.
7 c( x, l, b! L! s$ L2 S1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
t1 ]' L" _5 r1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
Z8 K( }, D% Z- W1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill., e: ^& U# Y9 ^6 Q! [$ h
1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic
8 {' n/ V# F, S9 m! ?, s q* Y8 I" ?+ n1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log3 L3 b; w3 |# M& Z6 O
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15
; F# a3 R k2 U% J' }- T3 ^ g1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status2 [7 e0 y0 K, N+ v
1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.
8 l h/ b! G" z1 q, I3 r6 U1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board) \' P$ z. X8 L$ A6 j- ?; N
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
- D. p; h7 y, w* Z: ]1187196 CONCEPT_HDL CORE TOC not populating (page 1)
( j5 m& {# C# E+ I1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
1 }( n, w c t1 k% y0 K1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.2 n& \0 ]; }! q5 O! P
1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
+ @! A4 v. k) a- K; }$ f b% e1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
# J) v: x- p* }" F! S% p- b; w1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
. T! J6 l; J; T6 {3 M) H1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully7 q; B# O2 K: b5 z3 I# @
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
- ?2 f+ x3 U7 J# Q0 B7 b. F1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
% E7 _9 J6 o& Y. k7 w1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files. d0 p0 C% I8 T. G; c. e, Q
1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
! X8 {1 _ j9 i D' E2 H9 C* p1191514 SCM PACKAGER Packaging error PKG-100+ j9 Q# p* ~% h" w" V3 B5 F) h
1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly2 O5 L# s& P% R; b9 X
1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
( K9 R* O2 L; s4 v7 {/ T# h2 k1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
+ V% C6 w& L7 N& K9 z# y7 _1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
' u& }/ O7 `7 U5 y0 y3 X1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL) h$ Q) H% N0 j4 N1 A
1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
. X# ? [* H. b9 m7 Q" }- t1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved
" k8 W9 U2 m" |& w" i8 F+ i
4 q5 i/ h& {% F5 D% F) T% UDATE: 09-27-2013 HOTFIX VERSION: 016 X7 K* H9 P! j& \+ ]
===================================================================================================================================
9 z |+ m& T/ C0 m- T0 s% ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 }( z+ \0 p' `& ?. f9 q===================================================================================================================================1 B5 {# H3 N5 }2 F5 g0 N
548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist* ^4 \# S; L* D6 ^1 q3 _
1076579 CAPTURE GENERAL Display value only if value exists
) N5 u- X8 m: |/ s0 R+ y% K1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
( _) X/ y& Q# _1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
5 M; K8 T. e9 Z$ J* N1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
* P" e, X' Q* ?5 t1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.* t/ E3 J9 R$ r! M+ p+ k5 a
1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
& {* e h4 r% b" B& x6 I1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms/ t& ?6 a7 d# Z' r* g+ I
1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
, C2 s1 D. C$ K7 \ u& v/ H& H, C4 U1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
) K3 U! f4 w5 Y' F# a/ l- N+ M1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.0 L s' B3 M+ x$ u* ~; g3 H
1123364 FSP GUI Clicking on column header should sort the column.8 B9 a- N$ Y$ `/ E2 A1 e$ h
1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column) ]1 n9 Y, w3 x" W
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.7 c' j& S0 G1 P* x6 y
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
5 p7 \. W& j; {6 V( I1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
9 r- G( F3 n, G1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set! T0 p, b. ^0 l" ~! K) r- D+ G6 r! P
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
5 a4 o ^9 p1 ^- E! F1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.
% h9 ^5 U) C$ E8 ]% {1 x1142894 FSP GUI Ability to RMB on a header and select `Hide Column�+ F' h' i, \8 ?
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
1 s# \/ d4 k7 x6 U1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP
; ?! Z& a* Z4 c8 z1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract6 B4 B# {6 g9 q8 _! r7 k, k
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate( Y! s9 Z" \0 s6 t2 A8 q4 \
1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator2 i# g( ?7 |% F! R' Q
1145286 CONCEPT_HDL CORE Directive required for switching off the console, z% o9 c4 b/ j% k0 b2 s+ J
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
+ ]5 J" P9 _, @1 D: ~1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
+ D$ K7 r6 u* L. U1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.- f1 K0 {* e5 ^0 C
1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.! J' c. U5 K* b. g
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
$ [# V. M+ f' \: _' k1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
1 E c* V: L5 t+ G9 U! _. B6 e+ l5 L1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
+ f) r- p) j% c0 c$ x8 ]1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.* R, P( F: |" ]6 `
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
; z/ g# _4 R9 D; |1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.% [- L$ o" J& W8 c
1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
$ b# ?6 O# x0 |, O" g2 Q: |1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?2 \- }' _8 M2 |% g2 F' `
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
* u& E/ x7 X& d7 ~1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.( }3 U2 @8 u/ ~ {+ _! o) P+ z
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
' b& ] N3 d! O, ~, t- A1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out7 t5 I, I9 a/ Q* J2 t! E1 n0 T- M
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
, |0 C% H, O1 V# A7 Y* e8 S1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.6 l' n( }) q! i, w' b) w4 F2 Q
1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
5 Y5 k7 b4 d4 u+ D( f# I, Z1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
* ` S' L% ]+ ?* j, ?4 U! L' b1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template" @5 ]7 W' i# l u: _
1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
) v. \9 S! P' u1 r' t; p6 [6 f1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation3 H6 D1 K' b+ Y
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines: c" R6 A9 L; N+ }# a
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
% ^! J3 O( d: [7 ]9 [1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro N/ { D9 ^) g+ @7 \
1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape/ ~! W& v9 k9 V) H1 O: p
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
' k" S9 U4 }! I; _. h1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
! d9 G5 s- O% k* v! L! Q1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6- `0 f& R' E) _4 C7 a Q3 I' o1 Z
1162629 FSP PROCESS "Load Process Option" under Run does not work properly! k: S9 ~1 v- h- s' Y: W
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE, U. Z. ~5 l/ u2 r
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
3 p+ j, s( W, I7 T+ L3 N/ m1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab. u5 L9 R+ H0 g+ ^3 V/ p
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace/ C2 n& Y: G* [6 u$ B0 ?7 k4 _
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin4 a4 @) O; X4 i' U V
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?5 L- P- [) R; ?/ m* l5 S8 G8 ]( k
1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
. E9 g! e/ a! Z8 G4 M1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol) Q) F) P3 x4 }2 Y9 k% f
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.& W3 Q/ q7 e1 q5 a: }3 U' K
1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.8 ]) E {0 G2 X" c5 x' O! \* i
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
8 v% O& f( l' \- J# C# q9 Z1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
2 S6 i+ E" R* o* n1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)4 O, j, t4 Q8 T6 O( k n6 Z
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked0 s* k- I! F; H" c! D" k. @% Z
1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
. X5 p' I B' Q( e9 ~' L- y( D1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
4 d, V8 r3 v+ U2 }1 m1166074 GRE CORE GRE crashes during planning phases& a" @! ~! k6 y& D3 z5 M) ~! x
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed' g `( V. k, d: j, P/ y* \* E
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
+ }% f# w( h# _' l1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move8 Z7 X4 h8 p. r. N# i; k4 c
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
$ J2 d+ ~, f6 q7 {1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
4 t4 L+ h2 `; l/ H4 `9 J9 E9 V1167887 F2B OTHER Improve message on symbol to schematic generation
4 Q5 c# a/ M6 g f" O# z! u1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.( {" x( f# k5 h) u* M0 i
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD( c' I3 E* t. Q# \- F
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
5 K* _4 o: n9 C8 X3 F1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
$ C- f0 n1 c2 x7 Q. p1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
- C3 J2 [& f) h6 c8 ~! ] Y5 J1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty+ m; H7 v, m" [+ |
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
) Y, n, T" G3 d- v% U1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
. a: w0 O% n, W( q1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule/ U( k, h% h' U. ~* E: P, F
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
% J. w1 \4 n- c+ z1 y1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
+ C# n2 O8 Z0 o& p$ N6 P; H1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
% \) V: H8 e! p$ D- k0 g1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing/ @/ \3 q& L6 _3 K6 t L! T
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via6 I0 r/ c$ N+ F/ t
1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.' V0 D8 V! C: g- U# ]( i
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
& }/ c# A2 C& G4 C2 [0 }1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm% A1 v. B% }! X; S( H
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific2 G: ^/ P$ o# O: e
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically
! ^# g& k8 K3 [) {) [0 }1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
% D- P& h5 }7 F4 e. p; T9 Z% U1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..& H4 R! ?& B! p( |5 [/ M
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl: D4 B! h. {1 L3 h" {
1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.8 G9 j' \9 m+ a) T* V
1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
/ O) X; _: g" i5 g0 y8 q1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
& d7 B* y* S% D4 ]& f1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
; ^9 |, f* \* L, z; z1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
# U: m9 W, Y+ }$ g: d1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
9 w" T# O* m' z0 p9 i1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.( k2 d- m! K" b* K; P
1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version7 S5 n4 ?. o( R6 \1 q# N: Q
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
% \4 B% B9 W0 i9 h4 w1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin- _2 O+ }# P4 |# n2 s" t
1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
# {( x' V* Z2 O+ b* p1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box& m( c" g0 ~- G1 P. `+ ~. S4 {
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".0 t" g5 B* n7 w5 ?; h' t
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!/ h# ]/ O5 i5 \3 w7 H+ P* m
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up$ p$ k$ E5 p o Z/ f* S2 `8 H
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash
- G; y6 V4 X: Z! E c1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA8 s. S2 e+ s# w* l' T; O1 w& B: y
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block1 f) g2 {. v" Y/ ]/ v
1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
6 R4 U# O% u" {" @1 g9 C9 i6 m1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks1 Y1 X \- w) d$ D7 Q
1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
3 C$ V" ~& i# p* q6 x' p3 p; X1 O6 u, J1 o7 o
DATE: 08-22-2013 HOTFIX VERSION: 0156 K. I( N5 ?/ S# x
===================================================================================================================================- y& L% ?' `& e3 X* z, {1 N
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 k5 b3 k5 x/ c
===================================================================================================================================
$ N: K. Y. D5 a: G4 T; n1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time1 w$ A+ J" t5 e {& ~' g
1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties/ d3 J! z/ m9 c! S
1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user4 O# s2 C( ?' d
1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number
% m3 g" z- ?6 L8 g" r1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module
4 l) K% C0 O/ }9 B9 L; T+ u1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp J1 B- ?' q9 O& w. f v
1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.) f# G5 r8 j9 y* s; Q X; P# e
1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash2 D7 C# a2 W8 H6 _
1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes
1 v% i$ E0 s( [" Y [1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
I" @- E# e- i4 W# r( O1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.
( c( s6 g0 c, y+ }/ \+ ~: o1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"- n A5 `5 j; B4 y F8 i) B
1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function
" l3 F+ A2 K I4 @5 b2 W" F: d M! \* N( @5 o& l7 c! f
DATE: 08-9-2013 HOTFIX VERSION: 014* d' e/ b1 a6 z- U, c) \4 \
===================================================================================================================================
3 F1 N+ B2 R( ?. Z9 l8 u8 J% PCCRID PRODUCT PRODUCTLEVEL2 TITLE
+ R, B0 M* H2 X# T7 O9 y===================================================================================================================================/ f6 C+ R7 y2 m5 q& b2 t- z
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
( i8 _6 g# d' `9 }/ B9 E1 T/ X1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted9 G: g! w* Q4 Q
1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
# x0 s) d, S: n1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
# `. c8 q1 D- L6 W4 Y; O1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract9 ^( K1 {" \. _/ H4 Y. n
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented
7 e2 ^" I/ M# {/ O }4 X1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.7 l$ z/ v5 k \/ y1 d6 B8 J
1165469 CONCEPT_HDL CORE Import Design loses design library name! i& b1 s7 q$ f
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's
W1 i5 P6 {* R) \: e6 U2 C: ^1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
6 T, S; Z# `' F/ r2 j! @. ?7 T1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.
* M! I* J/ k$ t6 u1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6
+ K1 i$ m# ~5 S& d. s* R3 S1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.& ~$ y( h. P, v; c8 m- I
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.) `6 O0 x0 Y: e; b. i% x' g: o
1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad) S2 h' p% C. S1 J" M
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board
! d$ p) R, ]1 H# u4 `% b! Z, ~1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
k9 y, Q6 h8 r/ w: d5 z1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.- g# r% t, R( H+ C* O- y1 b
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
9 l. F& n8 [; N6 i8 ]/ w3 r5 Y- ]1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes7 d" m, ?+ m+ \
1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013
# O: {8 U+ D+ ~9 O o$ a" R* ]' m
6 Z1 L' O% L2 g" T: f V5 i! P, GDATE: 07-26-2013 HOTFIX VERSION: 013. s5 Y, c+ X7 D* x- f$ _' M
===================================================================================================================================
; I; c1 H+ S) Q6 r) wCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 [ m" T8 w w9 D- t" @" V===================================================================================================================================
1 I6 `5 T: H4 ]: e- H: w% t111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0+ j1 j5 N. m: I( }
134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals
) f& }* {5 \0 J5 J6 W( P: j; Y& R186074 CIS EXPLORER refresh symbols from lib requires you to close CIS m% f3 p, E# ~! m) ^ G4 N
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock: g$ v$ S6 D- a0 D, A3 {9 A' z
591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line7 V+ Z- p) x4 k7 O6 D
801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus
1 [. C6 @9 g4 H" ?5 k: H1 d* F" j813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.
( D1 w+ L& Z9 q% N! t' Z0 Y881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button
7 Z, p) M! m7 z! r887191 CONCEPT_HDL CORE Cannot add/edit the locked property- t) m2 F) j, L, J" V7 U
911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately
( V& K5 j9 E4 U987766 APD SHAPE Void all command gets result as no voids being generated on specific env.( _: f5 z" r$ E( P1 G
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.
4 w% e; L! V3 O1 @7 Y: J1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro. ?# B- R5 f3 w9 f- V
1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user# W( n& Z+ a6 v# r% H
1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
, K# e0 o& A2 u3 j% W( k1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on
* F, ~7 m o( C9 _0 k1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.
: o7 k; B# [0 o5 X* }; D9 O1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via. {- Y8 n) q& A$ w
1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?: t( L0 b Z* e" R5 h' _
1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences8 n/ T6 n9 ]3 r. R/ S" A( R
1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button# e! H* F$ g2 t6 q' n1 i5 q l2 l
1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys
* A5 P- s3 @3 y9 W1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option
s7 i5 i# r/ w. c7 v1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
4 g* x0 D5 m" n+ w2 I: O: W1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file
7 p" @$ o8 T$ }( h6 M1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
4 c; s7 z) R6 {0 A4 y7 k; i1105473 PSPICE PROBE Getting error messages while running bias point analysis.. p- E$ z) e- V; X) b
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.
8 Q$ d6 {* x1 c0 J# x: l1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
& l+ y2 A1 Z8 q1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
k7 X D) T5 g ?6 M! k1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation. B+ k) J% o5 ]7 g" }+ e
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol, R. ~! x3 e. I2 @8 J( I/ l
1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing
6 m! H7 Q) i6 t, A" \5 _3 @0 }& j4 p1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
7 L! L% @; M. c" y1109024 CIS OTHER orcad performance issue from Asus.8 `3 }+ W. }. V% X+ x Q, H' G+ [
1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected/ s" N3 o5 [$ C3 n/ `* z
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet., c; G0 I& f2 K
1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.* q: N; m4 x. s& ?$ n# f. {6 W
1109926 CONCEPT_HDL CORE viewing a design disables console window5 Y5 P- Q$ c# e4 F) t
1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
6 Z& O! X+ w8 K8 F" C2 D) K; q z- [1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application8 r3 ^- w1 L& j& d7 j P
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.+ V6 {" d8 z5 Y7 x8 p3 ?. U5 K9 g% K
1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance( L7 c: H+ z" o i" z; q
1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut; d# p5 V, i. j8 |8 u5 p% R) ~
1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly
1 O: x, k. _, m# s2 x; f9 \1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release% z: M: A5 A, w3 R4 w- \" |- B
1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.
4 K4 w6 H7 O# ?7 R: f1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location
4 w$ n) [7 _) c" g0 E. S- o4 P1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine
8 E- }0 y3 ~! p& l1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
/ l5 u1 o) q% M1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic
0 e# G( `* U, B: o: Y& [7 W' S: g1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on
! a8 A' `7 ^8 U* d* l- x! y$ a" Y1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name, _( R! @. B3 n& Z1 W4 o
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor3 G E8 \8 [5 u% v
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
: _+ X. S7 Z, B3 R& T1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
9 Z3 Q% N p t" l4 ^' y# D' u' v1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?
7 Z, c5 L& Y9 A0 f1 v, e1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction5 J' q+ j/ n3 G$ N, K) L
1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts0 r2 @6 ~# n- x$ \& [' S' p: x6 X
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box8 W. X0 J3 B. K+ Y6 g
1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol
" M! e" k& Q. M6 y0 \! I" k/ A" _1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly
9 K2 D% `. T, O+ t; F9 j1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.8 u( M! Q" _2 X3 g8 u! v+ i
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.
- H- a6 [8 b [3 N$ j& y1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode3 \2 Q( t1 y, o+ F C
1120985 PSPICE MODELEDITOR Unable to import attached IBIS model
2 e( c3 H1 ^2 A5 e+ J) \; x1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic+ U) M4 Y) Z" J
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.$ Y: p" X6 K: _: q0 C# }% |! q
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design8 y8 z! U" [% B! F I
1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs& M0 ?2 L6 ?' G/ l% T
1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.
+ t: E+ V* _- K9 v# c' ?) R1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.
7 Q4 \( t8 @( [1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing
- T: R- p1 x( Z3 |2 |9 e1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design." K5 ^- Y2 S0 W# {
1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.
6 `* `7 e0 q, r, r7 q+ S5 b4 }: C$ A1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files
, ^' Q$ q* w- n) G1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
8 B6 E" B! ~ w; J* k0 I1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one7 g3 U) e6 H; [, s
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.7 j2 l$ D. ?8 h
1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)* x) Q% _6 ^$ R- m
1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname
$ p, g9 H9 J, G9 f5 {2 l/ ~1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.* \& L/ f6 O3 g% a3 c' s" p9 ]
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5( X4 n; w8 K l" V
1124570 APD IMPORT_DATA When importing Stream adding the option to change the point
1 x( G7 F. p* O/ e T1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add8 H' k$ L" ^- A
1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference$ ]2 J5 N3 n3 C% e
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
5 Q/ I& ?- l8 r2 @" ~0 Y( m1125628 CONCEPT_HDL CORE Crash on doing save hierarchy7 m! `- P& N% A1 K# e; X
1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.
+ I v: b0 E3 @. E1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar
* {. m" F3 p* X; \9 i( B1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window
1 Q& q) J3 t$ j1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.
# a# @) Q! h/ b7 w- u1 U1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.# X& S7 C) {" a) X& a
1131699 PSPICE PROBE Probe window crash on trying to view simulation message
$ P. G4 Q! X9 J( x1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.3 V) I7 Q4 @" v9 d1 a5 E& G
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
2 u" X5 i% T& y/ l- l/ [1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command/ V3 y1 T* T1 |- n# V# \+ i; a' Z2 |* E
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape
) d/ H; F# v% z1 } ?% U7 D1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
9 B$ T3 o# e- `- F% G1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.% y$ g0 m7 X! J4 k! f+ p* |: C
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
% @5 I, Z$ B- v1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.( j. J5 W- P. i/ r7 w$ r. N ^
1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path6 u; F* q- b1 o5 Y) i
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly
0 C# G! B0 W4 s5 i9 _1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page% [3 H7 E u7 h* g
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
+ Z9 h0 X: P# K' |$ e1 I1 [# C1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
% z- j3 h5 l! l# N% c1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.
2 D n# l* q3 H1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped& f5 H8 X5 L" N: H
1141723 ADW PURGE purge command crashes with an MFC application failure message
/ @) C9 N- G; d' Q- M j+ n1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS7 p2 C4 P4 E, ^# t, R# I2 t
1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release/ [# a; Z0 g1 P! M+ d
1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved.
! K+ W4 E* |) o5 n7 w6 G. ^ p$ b' O' ~6 {1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height* A$ g3 V% u0 @& N- u5 k* v- k C9 L
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
7 f2 j2 ?( \" K# x1 w7 }1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
; g7 z+ h+ q' U- S0 b1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape0 v8 P/ R* q- k" M5 R; ]
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
. i- `4 V8 I- E( z. }1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.# I4 i! g! l0 v' u- D! Z, }
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block7 U* ~, ]) a @" l, H' [. q! m
1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result1 V2 ?6 a1 ^" l+ c( A
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
5 l, ~3 q9 [+ L/ I9 p) j1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate# G# ], Z# m% D
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value9 U0 R# A* Y y, S# V
1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.
8 M6 z/ {5 I5 ~7 e9 u( w- H! {1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page
! t) p5 S; G5 _' c6 f4 z2 s1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
. _) L4 G' o/ y! a& c1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6! J& P1 L: F1 O, |0 `, y
1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date, s) J" ]: E0 U5 v; K) L' c
1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name; E p) M# k4 N7 L0 Z, X
1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment.
9 I9 \* c. x, c, }3 B4 W8 T1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend( N0 d2 J9 Z q: Y3 C
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation.
( o. ]+ V4 k$ F1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
! v& Z# f" l5 H( \+ N1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode
$ O5 Y8 p) p1 F% X) A: g1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong/ B# R2 p' j, Z" w6 O1 d7 ]& S
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
1 k0 Q/ n/ A; @' ]1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro7 r8 l ]' j/ k6 ~: v# J& f9 R% `3 R
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
7 \# g8 c9 x" W7 J: m4 P0 Y1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly
+ ^& i* q+ @8 W9 g1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken
9 m% |6 K& k; C( z, }6 f4 Q* K1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase." [# ~3 k1 {7 z
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.
6 _- i* I& b: |, B1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
, |; P3 F! q6 ]4 B9 l) m1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF$ m; i* X. f. u8 _/ r- u
1159285 APD DXF_IF DXF_OUT fails; some figures are not exported
3 G! l ]* ^) E T9 {1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website& h4 m3 @9 |- t$ [
1159483 PCB_LIBRARIAN SETUP part developer crashing with
6 J: f6 D, S3 b6 k3 \1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.3 @% I2 a) [, } v7 @) I4 ^) O" E& S
1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly
, x. c0 S2 }- S6 N, s+ C# A1160004 SCM UI The RMB->Paste does not insert signal names.2 Y/ h) g$ W, K( Q
1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading
4 G' b- s0 `0 t4 r: n1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure3 `. N. w x. I% v7 V
1160537 SPIF OTHER Cannot start PCB Router* s5 V2 f. D. d9 ]2 e* w6 M$ x
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol
0 v, v3 x5 |3 m2 h; o1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design6 `- l. L+ z. [7 T
1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12)
3 b' W6 a' O9 `& r. W1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die
S$ q! I- ^3 a4 i- {5 Y3 s1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets.
5 J: P: \" V" z/ {! G: H
9 t; N4 [5 Z, x; a! ^+ g$ zDATE: 06-28-2013 HOTFIX VERSION: 012
9 Q1 ` U ~) q. I===================================================================================================================================! w3 J# x) m- |* @- H9 t
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- T3 m2 i' W% Z+ p* [9 W===================================================================================================================================0 b# h: X# M, ^
914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
9 `9 i. d4 Y" W1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files4 d3 h% q& y5 w% x
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display6 x5 A- f1 d- e/ |. \* l4 H6 z/ O
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
|6 j7 B: c- y1 N% i1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
! a& r- L) Y( i7 d/ _6 A1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
4 B% j0 r& J5 ]" L1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.) M) p; V- d: b$ J1 W
1151458 GRE CORE GRE crashes on Plan Spatial
" I5 q( G2 \' ~8 g& {/ t1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
. K; P7 I8 B5 a D1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
) B z' t: u5 D& Z1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
5 `: Y! {7 P1 ?5 S+ ^: \& |1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger9 j4 @) j2 _( m O( w2 `+ e3 S
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
* x( D. n) Y' J% N% v& [# F& |9 K1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places C9 o" n" k- G' c3 z/ i
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
t( r9 S2 G, P1 y/ v# y4 h% V1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
& L2 y1 H* ^) ~3 B4 Z1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
4 r$ S$ v: ?: Y4 M) a
6 `; z( f- E; H+ l" I6 HDATE: 06-14-2013 HOTFIX VERSION: 0110 P$ a: C8 f2 O! q
===================================================================================================================================
7 w3 Z/ k' i9 oCCRID PRODUCT PRODUCTLEVEL2 TITLE6 g' B+ g6 k) T! p2 x
===================================================================================================================================6 i! r# q: ^ v [+ S/ F8 |8 N
982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf
9 Z, z+ h! r& T4 c1 \1 U1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
t% r, b. M* h2 g1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
/ J) \* ^* ?1 X1 @1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import
& g" ?' i: @- y/ y! C" g; A1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
# E5 t' W0 T) X" f1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting
h! L9 E) e1 e2 o3 P! h1110323 APD DXF_IF DXF out is offsetting square discrete pads.
) b# P7 x# c, G. v. k/ ^4 A1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
: k* ~# K7 ^+ E/ H% w1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.+ _. G1 J2 W1 r; L! B
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"
: G& W5 l1 f4 p/ [5 a7 |1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.1 i; _" G) V: `0 i% i1 c; ]6 h
1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide; `. ?' r) T: q% n2 P
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero" N2 o9 E; L X8 ?3 l
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
& S* f( C% s! \/ P' |; E& w7 P8 |1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output% v6 X# O3 B9 {
1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
- g2 U1 R1 O# [1 b& @% g1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
! U" K; ?+ W* N5 H9 q1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.+ N7 B# S" T) @- q: `+ z
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added" Y* h* Q) y& [
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
# i$ w; G% u' \1 ?* F5 ~1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol
7 N {4 F& O3 d, h1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.1 f( t, }! O: D8 \- Z# ^) e
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF0 h7 O: l6 ~7 J( J
1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid
- r+ [( D( P7 X9 y8 V t1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()6 Q' U% t G5 e+ M/ S
1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes) Q6 C' P4 h: H7 x: G
1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols2 J- |: @! [& {4 L, o
" b* m t- T- h( j, _
DATE: 05-25-2013 HOTFIX VERSION: 010
& ?9 E4 c8 |2 U===================================================================================================================================6 U: n% ]7 q; r3 X3 E( y9 v8 z! p L
CCRID PRODUCT PRODUCTLEVEL2 TITLE4 X; T* |# `; k* U
===================================================================================================================================
# z+ I* f1 @5 [) l( s1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
* t" \1 X" ]. h1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border0 ]$ J( u! R( }+ R* {* ^* ]
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files% h9 z! S: r/ F4 z
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor8 c2 ~9 V/ o S1 m% ]) M
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.62 W1 c; M. i: h
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
( S8 C& q0 V/ A1131775 ADW LRM LRM error with local libs & TDA
$ [+ c; W8 E3 i; @- A* L) b1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP49 O0 i& W M. D9 _$ W
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo" F0 H' j% [% g2 p, V: Q4 m5 N) o
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.% @0 q/ D8 r. _
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur S# v, R6 G Q' \' t9 g7 y: a4 C, i$ L
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?# u( M3 N. O/ [6 ]
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.* L- d" q3 ^6 u" R x
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
# `& b$ q$ h1 r/ F& X- v' P1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro$ U6 B. [. n& q [7 U" R
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode./ O; G7 J: H* _
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581." d# h; o4 P: R; F: @
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash- \* J5 {& N: w" v# x
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF5 Z& k5 ?1 v/ U& N3 E
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
- a) u! u8 R: j6 \1 ~, z7 x7 z1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor1 S- L& T. ~ `0 w
0 i3 h l# [7 u* E
DATE: 05-9-2013 HOTFIX VERSION: 009
7 {+ l9 Z% Y+ ]' `===================================================================================================================================" G# G- e. ]7 S1 o4 |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' ~4 {4 p$ f1 {, @===================================================================================================================================
+ D: j* _. H- \( w6 b961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp0 l5 @5 Y6 s. H$ d' F. Q
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function
) m. u- N+ u" x5 u0 Q1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da, T }& B9 Y% S7 R' r( [) b8 ?, K
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
) W" v- _5 i4 W1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
% M7 x- I N' @ W- e% j1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock4 r0 m- w9 y5 Q& S# \4 }" w
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
* ]. }. K% K( q/ t1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro. q U# H7 i6 ]% \5 N
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.! d0 I4 _) ?# x7 ]' A7 G( o) b
1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl
g; _4 Y: C" V% y1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.. o6 |# Z4 C' N2 x; A9 o' i
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager: @. `- u' V ~: F
1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent
, q7 e& U; f- h X& c1126096 SCM REPORTS Two nets missing in report8 O/ b! G9 M0 e# {6 u* h) N9 H( z
1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD ~6 n) j0 x M: ^# Y- Z
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
) y. x' _9 y( X$ S3 R1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
7 o0 r% F4 r$ T6 |! q5 P3 s, M( J4 k1130737 F2B PACKAGERXL Error - pxl.exe has stopped working
2 u. [7 e3 V3 `% }, e+ }1 J1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters3 ~ {6 n& S1 ?$ M- ^, x
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.
; y# H' d) H8 c9 z/ \: W9 v- G1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
& E1 G$ s7 d, y6 c( {' @1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
% I$ C# d# h- g3 H* H1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes4 k) a$ F) J" K5 A2 v# l
/ U7 ^' X7 [3 n1 H( z' M6 k
DATE: 04-26-2013 HOTFIX VERSION: 008
$ k$ F/ ?% h; V, q===================================================================================================================================9 \* ?+ j, a9 x2 l* S2 J$ d2 `' X2 V4 X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 o( k% @: C z5 m! H, W===================================================================================================================================* l$ R! ]. [9 Z& m- M6 C
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit+ [0 G2 x0 L& E) ?. G2 F
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation" D' E5 {; T: _( \# J, u( p
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device0 a$ ?" t8 f/ \" b
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
& d3 e% [" d; ?1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
9 q4 Q, m( g' E8 W$ t! ~1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running, C& |! _8 Y- V
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
# z5 C: R! S2 i5 Y) ]8 C2 o1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
" B4 f& P- G$ }- \7 k/ y4 f) d1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.- B6 u, [! f* h( S4 V
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason% W' K7 |# N% f# N
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.( Y4 v5 r' i& Z2 g' O- }; u& o: U: |
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
4 W' |6 ~. a) x r. L1120414 ADW LRM TDO Cache design issue# J- Y7 n% }( ?- R
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
: E- D) X+ ~3 ]8 Q. M' v6 C# ]1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
+ D: J3 {) K* |1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
( `3 O7 W) y' Z E$ j7 @% K8 f1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
3 l: }3 a3 n0 ?2 C* `1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced# U% N' }9 A3 ^
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.6 k7 n8 @$ |* @
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable% h o3 S( D' c3 N. W
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
! R9 s0 ?; Q9 a0 S6 I, N' M1123816 CAPTURE PART_EDITOR Movement of pin in part editor: M4 G! i( c' ~) a. p; p( o
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50% x5 e) J' x- u% c9 V
$ t6 o* N/ c; ADATE: 04-13-2013 HOTFIX VERSION: 0072 i5 \) d; x9 z4 t6 X1 p; q+ t# D; e
===================================================================================================================================( ~: _. Y% x& e
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 u1 c: i( |- p& w- S===================================================================================================================================
5 Q! p% b3 t$ s* R# W& b1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die+ p9 Z! ~: _: S' O3 ~0 p( @
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6& [% V9 F( k$ q5 }4 ~& o. h
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
0 I$ @8 H% @/ B( E) O3 v1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
4 X' S; X! f+ s1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
9 `2 } a5 Y* O5 ~1 O/ d1115491 ALLEGRO_EDITOR SKILL telskill freezes command window. L- W/ Q3 J3 |2 }, W6 j# V4 Q( C
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.$ |7 U1 w1 f; v1 S) H
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
) L/ P7 v3 L& d3 e& f% g8 t1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
: o8 B: n; }- ]' N9 A8 }4 C, y1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
& k9 m, v `2 S% ]1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?7 N; W; O) s5 P. B' d
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
9 @! {/ I5 |6 N* U9 d" h1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh6 S8 y! s# H' e1 o
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
1 T: s8 B. `, O7 c: H v ^" M1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6" l) K$ V& v) F. P' Y! a6 F0 G
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
! J4 h) {3 s: B' |* j1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps3 M# r7 A. P7 b0 o! _
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
" Q1 G4 x. {0 ~ ]9 [1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
) ~! \( j5 |; a0 B& v/ u( K+ j) a7 r z! A
DATE: 03-29-2013 HOTFIX VERSION: 006
}1 l$ O \: ~===================================================================================================================================
) q5 h. x6 Y/ f2 P( qCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 I. U4 a; R4 s& e===================================================================================================================================
6 E% g9 q9 n4 l U625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
4 b2 n) k n' p' j, l642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
, V j* T" B) W+ E) Y! s650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".( }4 J9 h+ G) q7 a5 y& X% Y4 M
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
0 Q- A$ }: S" W' x" ^687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect- l7 h' R9 o+ R& t4 K( O' r
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
0 l4 ?6 j' P* B- d825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
: x5 U; N: {& g2 V0 H- H834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
! i3 G* ^! }; h% n# F! A4 o835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
% z8 T5 W( I9 r+ W, j0 e$ {868981 SCM SETUP SCM responds slow when trying to browse signal integrity
( t+ A% J& q o/ O6 |6 x$ ~( l871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
4 s5 {9 z) X' c. h873917 CONCEPT_HDL CORE Markers dialog is not refreshed$ A9 `) F. v. Z$ K& i1 @- @
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
5 ]) h! n0 k4 i888290 APD DIE_GENERATOR Die Generation Improvement
, ^) m0 d% b6 `9 o* |% e0 l892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator* q- G. K6 V% j! [: d8 A2 ?
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
, |9 o8 `3 o# {2 ^* Y- B; M908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
c- N2 W; e% ^) ]. E* |- V' b922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols' y- A/ D% u8 h F! v+ z# g& r. s% ?
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
7 i7 [, u3 q; L1 ^$ E6 t935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
, {: u1 t" v; B7 m. p* C945393 FSP OTHER group contigous pin support enhancement
* N; J6 r& V. v6 n6 {; @969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database, @6 E" B# J: T3 H: K
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes! Z' k/ _! p( }& a# H
1005812 F2B BOM bomhdl fails on bigger SCM Projects+ v; a. J1 }: V! ?7 t* y, r
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture- d, x4 w" y+ |/ p0 e& t% h
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names/ R* s3 @. Y, {, B7 U8 ] G
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
% _" J4 f* G6 Y% S( N N: t1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
: P3 B+ I2 ^$ T- o2 y1032387 FSP OTHER Pointer to set Mapping file for project based library.! V* S- `/ G- u4 c3 t
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�2 f/ w8 U; f* M R" U, I
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart4 V3 ?/ g4 e1 m( l. K: Y; n
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
7 [5 I) v6 ?* L1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
1 G5 z; d5 R* G: ]3 a1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type1 J, S6 j0 m/ u9 n1 `, N
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll$ [& e3 {! k) ~
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
8 ~2 Q, D m! a2 m$ `$ ^1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
4 v& p7 x9 i! h# C! }" L0 V1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus0 |. ~- X( {: a9 j9 Q9 }3 F
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts, V! d0 t7 {# A0 A' v
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs3 b: S5 D) K# n$ G) p1 u2 U% X; \" {' ?
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
, \2 B" c9 \0 s# ^1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
2 t2 X5 p/ a. F% {# C" P1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary% n6 t; a/ w. y! ]- d+ ?
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
/ Q9 v$ j4 j' O1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic/ _0 i( s( ]& U# f2 Q/ x, l' u
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
- Y# }) _5 `" {0 U1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45, s! u3 V, ~$ P& Q& T' X' O7 g8 D
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal8 H# E! P! V, H- P
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
0 z' I: ~% i, P* m1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
# l) b# F- i6 m1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)# o% B5 ^/ U v' g% I% Y# o
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
$ S' E4 O0 f% z3 Z1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic0 m1 e5 `" P2 V
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut1 {& M+ N& L! z, B0 b
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
* c1 G- t; V" Z6 y {+ s1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format& `- w; Y5 Z9 t& |
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net9 T7 W& S6 S* c( t. H
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
}8 E/ n% D) ^. i6 y- c ]: x1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible5 a9 K8 V% A# ~6 D% x+ U3 z
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
! a4 D# {" _8 ?6 g# y* u* v, X1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.7 L; A( P q2 J" w, } d
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
: F1 U: f: j- Y6 N+ P1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
) f" k' c1 X C& Q1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition9 c4 h2 ?" \& t# b6 P% ~' A
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
7 J: L0 U3 Y3 U; o3 ^ ]' }) J7 @& O/ v1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options5 i; l! p+ X7 F8 S$ f/ H x
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.57 t$ X1 M( L- S2 c) I5 `8 D/ {
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
' b) Y& z3 @* q% Z5 ]/ ~# d1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate1 _+ |+ U) C4 z' g9 W4 J, \
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
% ~$ L) J! S% V- U8 b1078270 SCM UI Physical net is not unique or not valid
4 D( w( W ^ O- @+ K. l& E) m1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted$ n) t9 ~5 V" s7 K4 v1 E2 j: M9 z
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle& v4 d8 ^8 p; k( @2 a
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
6 ]0 w. |2 J& w4 ]1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
0 p$ p- o- J9 F$ R2 g3 L1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters& d8 j2 T% n( H' T! S( ?) h$ K# G
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
. l) H+ H! a3 x$ y% [3 h% n1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license2 a3 B# ]. r# b n/ N0 ^; l4 ^
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
: I* f7 z/ g% Q! u3 K1 }1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
0 Y; Y! w- U0 d1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
8 c' z" J: ~, i# O7 I" e) z4 i( M5 Q1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
4 k) M0 K: b1 h* b7 {" W1082220 FLOWS OTHER Error SPCOCV-353
3 i# y7 {7 ?' y1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
: _* }8 Y- V; e3 o8 m1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
! Y5 h# d3 z- K C* [+ L1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.5 d+ H$ T; m3 B1 E. d2 F/ d) ]
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name( l# a: S# X! a& H
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
. s! u% r, @( p' y6 }$ B8 Q& a& d: I1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
w8 m( ` b# K3 X& a1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI. Z- d" L4 o/ p/ t2 p4 l) J
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
5 @, t, Y+ W$ T: G# w) u1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.& E9 X; \( I' W" S: V/ h/ E0 l
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates* c/ P( z; g% |% Y; S8 t0 V4 G
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters% V. s3 E5 L5 m+ u1 S6 z( H
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
/ c# j2 O0 m& w0 {' h1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results; | _! t- M5 `1 L4 o% F+ x, v
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.# a/ }) ^$ V3 e3 C, k E
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
, J2 m' d7 V2 i: v) p A+ I B1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
6 a1 @4 b9 j. @, e6 b1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
$ v+ E! H, ]8 u5 p- ~% ~0 t1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
* a/ w$ R2 r" N% }% \" r1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
" B7 s6 q% |! B+ t" }4 O1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated4 K% Q- d: {0 s
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins' [% I( o1 d/ W
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity1 U' ^3 a7 o& j. S- d
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
4 V, [7 D/ W" p& ^1087221 CONCEPT_HDL OTHER Part manager could not update any parts.; `/ m5 y) ~1 a) `4 _ g
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space& p+ P; N& `* K
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too' E ?0 K. }) V3 t3 G- w
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice; ^6 o: X6 Z# W. ]6 R2 Q6 s) C" i! z7 b
1088231 F2B PACKAGERXL Design fails to package in 16.5
\7 J, R( ^6 C: n2 u1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.+ A% U- `7 W# `! a% ?
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
' T) A/ w/ {3 g/ [6 Z% b$ j: J# e1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
5 r4 O6 C# H$ n i1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
5 J- o; w9 A! O& k$ L1089259 SCM IMPORTS Cannot import block into ASA design4 t8 M& M% n, o: E; A
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form, g+ t& {2 H" X4 U! P( E3 n5 }
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project, G. j$ @+ d5 |2 {8 G$ n& L& \
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
3 ^6 M- }/ M: X0 {% A1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
0 }4 c% V/ s6 K+ a, J! ^1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
1 {% d% d: o2 \+ a1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
; ]# I/ q6 D I/ _9 S1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
7 V! ~0 k1 J9 G3 T, d1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
. l8 n5 a, K0 M/ k1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.; p2 ~& f: h6 E; d
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
0 h8 \0 m6 v7 U+ X2 ^4 x: T1091359 CAPTURE GENERAL Toolbar Customization missing description3 H, `! ?) U# |6 N
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
1 U1 [; s9 i4 _6 ]+ j1 r- E. Y1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time5 h6 j2 N7 w) m) A1 u
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
* R6 P+ `; o5 p. q3 @2 {& N) z1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
5 M2 n7 Q- x/ m+ y6 D# M1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled+ C4 a# a, @% C* C4 A, i, p
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters6 m& T6 E' ]! y8 \- H
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error8 L% x, o1 W5 n- R- |5 T
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
, p/ R, a' m; W# B. B1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor! R$ A+ R/ U3 `: K6 U! E. x% ]
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
A+ D/ ~# j# n/ g1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
8 ?( f! ?' ?/ C+ D" \" n6 B1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
* f. g N, c/ a) t+ p* Y- D1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?4 R, L5 g. V5 j& }' o; n( E
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
( y" B$ r- n/ X; v0 g/ U" j4 ]1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
- p8 ]8 B9 Q4 b1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
! b. j% d: ^$ E. A: }9 L2 M! ]: O1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
' Y+ g- x. V3 H Y+ }1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block& t. W8 s$ O" d; u0 _
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
" U S/ v3 t; n0 Y2 R1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
) f* [2 H: N3 z8 M1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import( d& @* k9 m3 U9 I5 m s$ p
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
; Y. i) w' P( }( x- F1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias3 a6 u" o/ D8 B$ a& y' {
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
6 P: m; K1 r+ n8 `* B- a1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
4 s P0 g6 D1 c5 a: X4 x1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL3 Y p0 u. F1 }. l# e4 [
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.3 ], h/ i% u& @+ s
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side0 b( G1 Q: K+ L, C
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command% q1 F% a2 K/ v7 U1 p- I
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
6 U$ l2 }) N ~3 S" @1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives' b0 k/ M( D2 b
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
$ L4 e/ C! f0 [' u7 Q0 t$ t* B' g1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts! R: o' G4 k1 U/ R, m
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy! p4 e5 j, e$ g" N0 D# a6 [6 f
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances., }- W2 _! |4 Y9 Q, y5 L
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
9 z5 T+ l( V* W n# I5 \& q) }1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
% [. x2 p4 I% M" G' A6 s! \1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad4 b6 |* u3 I1 b& _2 Y7 D
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
3 S8 l" m, {+ K" R/ I1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad" w8 y0 W) V' R# L5 G
1103703 F2B DESIGNSYNC Toolcrash with Design Differences2 c4 j( q5 r# n, P( `; I3 I8 ]$ G5 T
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view; g1 k7 Y5 w; y9 E
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
' N3 E0 T. W) [1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP
' O$ Z' I6 D; n* ?" Y" J G1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
% L& r. X9 H) G4 c0 W O4 @! N1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
6 b# ]0 f w. \1 f1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.' Q O" Z; D% `7 T
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
3 M+ s! d3 l% Q* W+ x0 J3 q1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
9 K, j5 @5 s/ B1 p2 @! r N/ P1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
0 _8 j! e1 d$ d/ R% Y! g9 D1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
- d& _9 w! _! w; |7 J& @1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
, W0 k3 k. s% ~' b$ w1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
1 A+ B. M+ M8 s2 T: F9 @1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
( o- g6 i% |1 W" `/ Q; T/ B) B+ @1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
1 e2 |+ [4 ^* @2 t2 [1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.6 l5 b2 @5 D& H: E1 {
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
' E( X% A* \0 g1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
. Q6 p7 F* F5 X# D& V1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).0 L. g2 i2 y6 G: j% ?$ Z0 W
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
5 i$ u6 i9 ^+ Y* o( T# I1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
( J/ M1 P4 ~& M/ F$ V4 X1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode; S9 y4 v/ f" ~2 e% v" f
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
% X H5 K0 L. x6 f# {. m2 s1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
+ | {; x1 |3 ]* a7 j* K. E* s7 b7 a1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
- ]. | w! P- \3 c2 r+ T9 i) k2 C1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON6 o7 q( u' _# S4 p
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
1 c2 |7 g0 x2 v: i1 n% k8 I4 n1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset# `7 ?* ^0 ^' n
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
4 d |6 W1 Q5 x' N1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
5 }& ~+ W6 @! b& W( H* o* Q$ h1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP9 V4 w, f1 |% A) I& P7 |
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint1 s* Y$ W* Q( v' R
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan5 K) ~9 f' U5 ^! Y. u4 Z/ P) i
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
5 t0 n5 c& _5 J, a( V1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file/ K, F& M1 }5 I* t/ `! ~) |# J
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6! R) I! z6 J# i( I0 X+ u0 k" j
6 N1 u% n6 a- r$ lDATE: 03-7-2013 HOTFIX VERSION: 005
2 _; e4 X! i4 i7 I) e8 j8 L===================================================================================================================================' x/ p$ c) Q4 a I$ t1 T
CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 k4 k3 I0 U" D, [===================================================================================================================================
! w- y }# o" H6 E) Z: z1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 11028 D* H. ?) k. ^
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed6 f; N7 r) u7 x" S
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently! i* B( v5 ~. Q% f* O
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind: w3 Y/ n9 M# m# g6 z4 d; W$ H
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
( s5 H6 T+ I* N4 w B- F6 \1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
$ [: U" O& j. U1 I1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
- y( _$ D+ s1 D, G; `2 W% h Z' P) `1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
/ C j4 n n( v. A1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
; S( C+ u m& ?. E- @% c! E3 ~1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
( l1 e5 `8 Y( T; B6 z1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
& Y P: |- J: ]# R
* P' N4 u/ ?% S- m5 k/ PDATE: 02-22-2013 HOTFIX VERSION: 004/ N' y0 W9 L1 }1 l5 V
===================================================================================================================================
: k5 W6 G+ j* LCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 F# A& O5 f# M5 ` \===================================================================================================================================- B: \+ v$ B) N! a& a4 `
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly0 u! d, K1 i$ x
1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing- U6 N$ S; }1 O( y- I! ?
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
' x5 Z6 }! i. D% u B+ i1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
: s$ x! ?8 D7 _4 ^7 }1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend R- j# ?: d7 E5 G! K; w5 B
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report5 E5 C, y; A" x0 g
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command
; h: ]* }- Z/ j" G/ Q4 C" b, \6 K1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
1 o" v1 L5 a/ P8 P1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat
( A# `5 x8 p& f) {1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated. Q+ P4 }0 v/ V* z2 O$ x+ }+ n
; O3 L5 w$ I* i( X7 T" xDATE: 02-8-2013 HOTFIX VERSION: 0031 V4 B4 |9 J4 p
===================================================================================================================================
) H. x# }8 M# v# n5 SCCRID PRODUCT PRODUCTLEVEL2 TITLE
~- @, _% P+ @) W' o( X% X+ K# V3 Z===================================================================================================================================
# m: Y6 [- k( g3 l4 \9 e4 \9 G1077728 APD EXTRACT Extracta.exe generate the incorrect result0 \ |2 Q# i& y9 J' Z
1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF
! L, L( [9 L+ O* M U# z7 w1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer6 I5 f1 S9 \% q
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
0 d7 h6 s, @" Q+ t4 g1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on
& z+ \8 J1 T1 q+ H n$ O1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
/ \7 g8 e( j3 i. L1094788 SIP_LAYOUT WIREBOND Wirebond edit move command5 e: _5 r! q0 s* K# m
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor0 Z* c/ E/ e& v; e1 ?
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
# T3 y9 c; Q8 e1 ]1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff$ E- a+ p3 V0 R9 n
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
9 D B; ?- k, s2 \4 Q1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
+ u4 ]0 Y& q6 u- \. C) P2 ?1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.* y6 _$ ]" R' p4 | D( g ?
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
" m/ } Q) y1 U5 |4 T/ m1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
# Z( ~7 K) p* w% K0 s5 K. t, c0 }+ a
DATE: 1-25-2013 HOTFIX VERSION: 0023 K _+ H% z, |+ z8 u& ^
===================================================================================================================================
7 U1 c) @) d' NCCRID PRODUCT PRODUCTLEVEL2 TITLE
( I( W. s( ^, C1 Y) J) P4 i===================================================================================================================================
1 f) C# ^6 J) V0 B. c# j( Q5 B491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
3 u, M" I. {. d% r863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"7 Y6 [/ B/ f2 T
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes M3 g* s( c5 F! d
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable, @/ Y+ T2 j3 n
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33" L2 r' z: R6 Q/ d
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
/ U8 {, _6 w2 W% C- T* c6 }5 d1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator* L8 g; x, a: ~. r$ e9 r5 ^- l
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command: R2 Z) |+ m% c8 D- m! ^+ d; l% M
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
0 q- V6 U$ ]) Z8 Z M1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
0 O! J5 [( A% d9 L1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.- m' x) C! g D
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
, ^2 X) F5 f, f7 k# Y% e1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0- h6 R$ U- w) v+ i! L
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
7 o4 j0 M6 U- j5 ^$ y& @0 ~: A+ @, S1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure5 |- T5 `$ q4 _' I+ i
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer8 O% R& ^2 x j. m
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.) {+ z/ Q; t: q: H2 g5 }
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
0 T2 N+ c3 q, s$ z1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.- v1 k$ \! [- X" V( e- A [
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.69 l& d5 l3 A8 _, I9 K) v% n; z& C$ k
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout$ X3 a1 f+ S+ }& q5 [
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
& @+ Y/ z1 z7 [3 y' _" B1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.
+ W% K7 S R5 X$ U+ T4 A# `1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
# ]0 N' C2 D% Z1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
+ i! V% G+ K8 y, y, ^1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
\0 L2 ]' B: ~( V8 L3 G1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
& w' L' A$ A$ ]" J; M% m' `1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.6 ]2 S9 _) c4 t3 \9 x' `
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue$ a/ d* k. q- g" H/ ]; V
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
0 b; d" }6 o0 e1 r' o' O1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
3 e3 n7 ?' S/ e$ s# L7 M1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
1 P! t! W0 N7 D: h6 e2 D1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
0 X( n$ {* @2 x, w& {5 m) [1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
4 E$ z: m' P* Z( L1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.+ L' f0 N- H# G: \& y; h z
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?2 J8 h8 {; l, y5 v
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group9 M( o) G$ N, ?6 k% ~" D9 n* u" A
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle, e$ {6 y3 d+ S) y+ _
1090689 ADW LRM LRM: Unable to select any Row regardless of Status# U5 e' W, P5 J" \3 @* ?
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle6 W6 d+ e6 Z" t5 I, H0 i
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.1 }- u" N! H' g' v0 Z
1091218 ADW LRM LRM is not worked for the block design of included project
# F3 C) R7 T' w$ \1 F. f w( x1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
8 |* g2 d# H; D. @7 G1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
7 }$ d: t Y7 g1092916 CAPTURE OTHER Capture crash6 k9 z: M, g; i5 M7 O& l! q. j6 o8 i0 U
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
" r& Z& H g% w7 Y( R- m1 _! t# H1 [. Q! A, `) O/ [
DATE: 12-18-2012 HOTFIX VERSION: 001
( |* u: e `& K* m: x0 k5 ?===================================================================================================================================% E6 T; j, z M' O, J* ?) L$ n
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 Y1 [" G' f e% K
===================================================================================================================================
- |8 M% M* f, h7 z+ _/ Y501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
3 {. a' `2 `. L3 a745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched* \7 ^ e+ U& m4 `) S
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted6 C: T- u' C3 I3 J- q
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash( e6 M$ ]3 [0 L% H
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments" t$ _ t9 x h" _' U: i4 r6 u
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore& i" w/ R5 y" b4 q: i8 X9 |
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
9 ~5 X7 L# Z4 I2 z938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
$ l/ d" z u5 \( U! V; i947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
* g0 D+ i; @; Z968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing: X- { m# i F/ s! ]+ j0 b- f
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
6 e7 Q2 p {+ G! f' V: w1 ~6 d981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected./ L: H7 [8 u: o+ g6 P
982273 SCM OTHER Package radio button is grayed out
& [, x9 V) C, j$ R3 n; }3 g& N( G988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
: c! S4 _0 m$ ` `2 Z6 ?+ j989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode
1 d- K |9 v! Y! e8 Y/ E; ~993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
& v% [, j( G( c o1 C996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections) O5 b' Q2 U, m8 F
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?4 B" n/ J6 Q7 H3 ?; I/ a) c
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
/ Y8 s& i/ D; L% j: A/ B1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs; q& S& u1 w5 {* H1 ]2 a
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg1 A+ m, X0 t2 Q& A: D9 w
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
" I6 P# Y1 h: W. M1 q1016859 SCM REPORTS dsreportgen exits with %errorlevel%
6 i) g! D0 {0 D* W: \6 A8 G1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
, v, [/ B2 V. l5 L3 T" R* _1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
2 N$ V1 v" ]/ A: x( f: ~1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts
! x" m; w" i H1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
; Z/ j, D- l6 [& X3 J C3 { S1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.3 b$ p% H% w# y/ E% A
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button8 T5 H2 b; t* ?) A7 v8 e: E7 \9 |# |
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
1 P' [2 g$ ^# K1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist: ]3 H' ?0 P1 r1 C* l
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
# D- E3 x$ W' y7 v. \' u1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
4 J1 g/ P# }0 G5 g1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly4 q2 ~% a. Y( u
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
+ E! c, ^& D( A% {) q1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file); x" }: V$ H/ }6 O7 c$ ~
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol {# `5 m. V1 T7 i) u0 O
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
# Y7 R8 w( ]- g' t* u7 u- _1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."0 L. B/ b& b. K2 w
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro& H+ h/ K& S( d8 A) }5 k
1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
0 E/ Q9 Y0 G6 s2 s7 w' ] U1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
8 J4 I& i- J% f$ d; K2 E& u2 j1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.5 j' q8 Y6 G0 v' E' K& f
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
! {: I l' p7 s0 a0 k1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu+ w. Y; T5 V9 b. P$ n, `
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
. v* a& w2 i1 D: M8 x1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
: v# I! K+ c1 j c k W& T- p& J: r1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
# P9 N" E& o( y. ]0 _1043903 GRE GLOBAL This design crashes during planning phases in GRE.
( {2 H/ s @: @. N4 K1044029 PSPICE ENCRYPTION Encrypted lib not working for attached& N6 I+ R- }# b. t7 C
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
9 k2 {7 H6 Q" U6 {& s$ F1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
, f/ @$ a7 d- x6 |1044577 GRE CORE Plan > Topological either crashes or hangs GRE
3 e8 u4 i+ B: `. s/ W1044687 TDA CORE tda does not get launched if java is not installed+ Q; j& z/ Q3 _9 @" L) R6 R# p
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die. }" L9 X8 Q2 N! h6 F7 B
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.. _$ H( C5 F; w3 f) v( u
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?2 _" h8 T; f% z" p3 _
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.( ?" @4 ^. A' [. L, i
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.* R/ m- \. L' y9 T5 G) G
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow* y1 r, ], R' r9 k- M, j3 F. y
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.% A. d( S5 A3 U. d: T) Q3 j1 ]
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill0 H2 I5 }7 H' L" W
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
# N3 _$ Z4 ~8 l# B( V$ o3 F5 z g1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
P8 z' x' Q" j& C8 a% m4 D4 V& v1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5% \1 b+ t, m; l" @4 k
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value9 l$ F7 e; J) f* a' @
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version+ T2 }% v! Q% e1 d: [. O0 @* c; l3 u
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.
& C# ~5 n( G' ]" Q; e" B: t4 X1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.6 ~, n- v" n/ _2 M
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.( Z+ `/ e+ o* N4 N0 l' i( D
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes- M8 Z6 P X, Q; @2 v
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.( Y3 l% }/ R! a! m# T
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3# Z$ q# L- p8 P- q' J
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
% v, ?& x* d3 c y5 v0 L1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors! w; l5 P0 }1 i1 \" }7 ^
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated., j2 j8 X" E5 z9 ?
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.7 R% ]2 J8 k2 f7 d4 Y$ c* p F
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
# [! S" c2 Z6 H1 W4 Q' ]3 m* s" m1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs& |& O+ ^. M$ q' b% t
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label9 l0 n& k5 s' B3 J+ r2 P0 B
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction./ i* y% E2 M9 ~: l. f7 i
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
5 E3 Q1 y9 O7 Y3 m1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down9 ~+ ?) {' v, U4 T b
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
) L& x/ i( r8 M! E' G) c1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
6 [" ]) u1 p, i4 }5 w5 x1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
' A0 s' ?! L# _1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
$ U) s: F; B7 A$ @1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.1 b7 b( q$ j. _; n2 |/ V2 e f8 h
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created., l H: }7 U* O; O& `
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move' M* T% ^' x, K) k, J
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
# e9 I* `) V2 Q8 o R4 }1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer- h3 N) t% v9 y# b+ ~% |3 ?5 Q
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
2 J9 W7 K8 d" S6 I, x( h1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.+ d1 U1 ]# Y5 P4 v
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
8 G `- i7 f6 K# C8 y/ }9 r1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.9 T4 e! i! @1 r, h7 f( Q0 ~6 h
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
- O3 p. N" T- l7 G" O$ ?8 G6 _9 J1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?* B- h' I: d1 y
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
: R- n. Z5 J8 W1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
' P2 c, v; T3 k% W1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
- E; Y% @3 k' L. a1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
: ^! z1 N, ]2 b/ z9 P4 y1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.1 V( C- h/ L0 ]/ U/ [5 `" p
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
$ r _- s/ h2 L1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs8 j' {# u8 K7 S; d+ u* g
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals., `9 N2 g: x9 j" d/ m
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.* s0 l l) o3 `6 K! @' S
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
1 l0 I& y: z4 a1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV) X( t1 Y/ C1 h9 p' r
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.
% N1 q2 Q I1 C; a# {1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X Y& I$ s8 o" B+ B
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application1 a4 c1 {2 ^4 u/ E7 [' O" u
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report1 D2 z3 N2 m6 a: a% Q; n
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC5 Z- O' z/ x4 s( q% c2 ]2 k
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
+ m- k# ]9 Y& W' {$ X9 c6 }1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.5 z6 ]: ^" E" U9 Y' j" _4 m
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file( G. A: {' v" }, x& t4 P! C) [9 X
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
[9 c+ P6 t7 C! Z( u# a1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended. g1 C+ B1 I6 U( r6 _/ Q9 M* T( `
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067' |$ Z( s& z" }
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design) ?) z: n6 Q4 W+ p# y$ M: R, B
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
. U9 [8 m: q( A, G1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
6 h! j4 P- p0 E* B8 r. ~. m0 Z. p H9 }1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes0 w4 B6 H9 f. w! N
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
n3 d8 r0 [+ |) @1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal- Y0 P* E$ x3 S/ s7 U
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.' R# D! z! c |1 o, C! T
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6& d( d8 K4 x5 b' @
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5) D- ?* t: B; B( ~
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
4 [/ x+ o3 O' N% Z* x1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.% M( F; k9 |- j9 ]3 D
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor! D- I! B {7 }* G' W4 d/ @
1073464 SCM SCHGEN Schgen never completes.
8 Q+ ~; O' c. T1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory D7 `) b4 c! }2 a# |
1073745 CONCEPT_HDL CORE Import design fails' C4 n5 x" Q( D5 D# T( `6 b
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
% W1 x; Z! P4 p, r5 G8 s' b1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE4 G! O! `" p) w! q# F
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
' d: w: v1 m5 u6 Z1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter+ U- ^. y; H( A7 v9 B+ g. w$ }
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
! h! o1 F& g8 `; ^1 n5 V5 ]1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
) q4 y/ s& q$ ^/ W% R6 t1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
2 T+ p2 U7 y k$ t5 P6 g1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
: u ^& w% [2 W: m1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
. u6 s, P9 d1 h* H3 v/ z% K' h! a0 W1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
4 c4 w+ U# z3 U5 F4 o" S" z4 A1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2; }3 H/ H: i! j
1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix* |* p: L& t9 ~! f, R$ B
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes8 ?- j7 a5 T# Z
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top8 Y* S3 [* P; d! V9 d) c
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.1 }; {* ~# r9 n8 t
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
! c4 D x+ y9 z# h1 s/ |1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
3 C8 F3 I- h2 `$ b8 T1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
& L. H' R9 \1 H2 _3 a1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database, g' W( i4 x( `8 B
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset) a! ^% [+ p( \% m- B
1077169 APD SHAPE Shape > Check is producing bogus results.# [5 X k6 D8 p
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
4 g' k) C( e) ? }+ m1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
1 _" {6 q+ S* ^4 l1 F3 @& X7 L S1078380 SCM OTHER Custom template works in Windows but not Linux
8 @5 [; ~9 Y+ _- J$ c1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
. B: p1 T- }7 E6 g) x9 ?9 M1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
$ y% F6 f5 G4 S+ l0 _1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
8 _& M- ]$ o9 B+ S6 c9 c4 F1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
% A0 x- e- {$ ?/ ~5 @" C1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text( ]7 q3 Z* |" J/ Q/ X3 n2 A
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
- ^, |% Y$ [! ~1 j- Z1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
, T! U! E& }0 ]" r/ k1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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发表于 2014-7-31 09:06
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