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DATE: 07-25-2014 HOTFIX VERSION: 032
5 e& O w# I' w! Y" n3 Q+ U8 ]' J===================================================================================================================================
- m$ i4 G! H, _" ?/ C* zCCRID PRODUCT PRODUCTLEVEL2 TITLE! P/ `6 e) b7 j
===================================================================================================================================
+ `: v* ~1 @6 D9 ~" }# `2 B3 R1 T381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
4 r% w; A' I% w% K616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.
; S) e4 i ]4 s* @0 `: w) A& E. Z982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibilitywindow
" D8 U# t; A% A& B! L5 X982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols% b" Q1 L" n# t7 D+ U( j
1024832 Pspice PROBE Shows wrong data & header whenexporting trace to .txt# {$ h; h" ^6 I9 k) V# x, M
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: outof range of data4 e A4 a3 c8 ?/ m4 u9 i X
1112360 PSPICE AA_OPT Advacne analysis gives runtime error whileusing Optimizer in attached design
( X, e. ^. v! @! S2 m. a: |2 c% Q1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitivefrom Chips file and failing FTB Checks
6 {5 Y2 Q l% R5 ^% a1184690 concept_HDL CORE Weird behavior of genview forsplit hierarchical blocks; l: F, X; R5 o0 G# V; a+ s
1212577 PSPICE MODELEDITOR IBIS translation fails without anyinformation in log file' P4 R$ k% q5 z1 e
1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed netbehaving incorrectly
5 G) X. M% n c. p1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temphighlight does not display on the last layer of the stack.
$ k. _0 `& ^; f/ r% y8 s% P1216519 SPECCTRA ROUTE Autorouter will not add BB viabetween uvia within the BGA area
0 v( p8 G1 h3 B# _. E1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Powersource and Ground Node for Globals inDEHDL PSpice netlisting/ T0 s+ D6 s9 u8 p' D
1223018 CAPTURE OTHER Diff pair Auto Setup not workingfor the buses.
- u3 A7 D9 s1 g: x/ v- x1225689 PSPICE AA_SMOKE Smoke analysis crashes with attachedtestcase! s$ ?/ u+ i' G5 a' x
1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file infirst go
% n9 z+ o' D) u3 C1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV
5 p2 ^3 l- B: f8 l; R1238815 CAPTURE OTHER Capture doesn?t retain more than191 library in add part/capture.ini under part selector configured libraries
7 U" O8 t0 _" H1 l5 s `1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace withcorrect via but right padstack name.& Z3 B+ G2 i5 i: i6 Z/ J# k& Q
1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turnsGreen
1 F) H5 F6 W0 \1 I% _% f1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for thesecond run
( L2 ?0 B! J' {; `- Y1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangsallegro after running update drc
. }% f; y& x$ B! g1243267 ADW TDA URL to TDO-SharePoint should bedefined in CPM File1 O! J# w! _& |9 H
1244857 ADW TDA Policy File Variables not workingcorrectly in policy file. F) K* L. j1 r" \2 p
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM4 B2 _$ _* O: A. t( i& I
1246811 CIS EXPLORER Option to keep the part type tree inCIS explorer expanded on every invoke& K- E3 l; u- ]3 M0 [1 ^
1246964 PSPICE PROBE Simulation Crashes in 16.6 butrunning successfully in 16.57 s7 S( v% i0 f. m/ \
1248782 CONCEPT_HDL CORE Display winning physical bus names(occurrence mode) in the the lower block of an Hierarchical design
6 a G/ ?4 l8 R5 ^, j7 i) H1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters textaround sch page; ^. e8 G/ A! X( N8 `1 f ^9 ?& Y
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing itswindow.3 Y, d1 s s/ D8 g
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip RouteKeepin to Shape DRC is created& G. Y, ^8 E/ U8 R! z3 X
1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from userpreferences.. z6 u" j2 Z6 F" y) F; c! k! |
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete aprevious path entry for library paths- r( U8 g3 R `
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when closeto shape in center of design0 _ C+ Q2 q! B
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3DModel color for more realistic view4 ~5 P5 [8 N* L
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that existonly on classes Package Keepout, Package Keepin and Route Keepin.
5 g; C& ]2 q2 w; p) J o6 q8 I1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should reportthe specific corrupt directive in the .cpm file( i% y$ d+ |, L3 \4 g. @- D# K
1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same netvia and smd pad overlaps
2 r" x% o1 X* u1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
- `+ _+ o0 D; f1258165 F2B DESIGNVARI changing visibility of Probe_number invariant schematic changes it to $Porbe_number% [+ e9 T1 P9 q
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification orerror message
- K" [- ~5 {% O3 n3 E1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File)filters characters from Text
) _2 n; t/ @0 n1 D9 {) z) X0 e1258872 CONCEPT_HDL CORE Objects are copied (instead ofmoved) when moved from sheet to sheet
1 M" Y& S% L3 ]* y3 a1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does notget transferred to the published pdf
1 w4 N: }9 l1 f3 K1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs tobe changed! e3 W0 D1 K. [: N. ^! p
1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not displayasymmetrical pad correctly when the footprint is attached to cursor.
% L" [& x$ h( A6 f! ] d1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when usingEdit > Move > Mirror7 a) I0 y: H. o5 k) B' X7 u7 j* B4 t
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue" w$ _8 D+ ?/ |
1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICCcommand on few Diff Pair traces.
( y7 w% B' B& v. E1260763 CONCEPT_HDL CORE Export Physical fails with $TEMPentry in Setup-Tools- S% A+ x5 |+ I; }' N- i' t3 D" }
1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen astriangles.9 Q5 w' j6 h0 b
1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting tovia of a different net at layer 4 & 5 in this design, ^, _( C" Y/ Q, k( b
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/Definition on available to use with Quickplace by Property
* j) j: C) A) e7 E5 i1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate routekeepout which specified for the all layers.4 V+ r6 `+ H" i3 G
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost fromthe nets after upreving the design
2 R* s* _6 n7 K/ s" F: v/ d! q1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due topc.db file9 |( s5 m0 H. W: e
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero tozero allegro gives warning- Value must be greater or greater to zero( @* _# G$ l0 O2 }" v# O* `
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind viasand do reroutes.
8 p( \9 d# U H1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes touse pad value7 h, y y, V( O9 Z7 @# }* \. D9 Z
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing theModels all Physical and Spacing NetClass associations are lost
% f, W _2 J) Y1265633 PSPICE SIMULATOR Bias point result is different inconsecutive simulation run of the attached project8 j P: l& a7 \0 Q" U
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement showwrong angle of rotation than the placed angle when Angle is set in DesignParameter* j$ @$ `& F4 N
1267541 PSPICE PROBE pspice.exe does not exit when runfrom command line
% V9 a- w! c8 ~! z- z1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselectbug with general edit mode! r7 ]! c# }- s& W" f
1268299 PSPICE STABILITY Pspice crash on attached design+ b9 k: \1 x/ z8 j" B+ x
1270879 ALLEGRO_EDITOR COLOR Color view save creates .color fileusing older extension9 m" Q' g0 \7 d$ g! c! M
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor supportneeded for large variant combination designs.7 d1 f- ^7 Y+ y0 j N: x' T
1271385 CONCEPT_HDL CORE Locked property can still be added
% W- ~# ` c5 L4 z2 g( j1271853 APD OTHER When using the beta "shape tocline" command, add improved messages and partial completion of individualsegs in error.
% r' h/ W" z0 Q5 a+ D- i1272197 CONCEPT_HDL CORE concepthdl_menu.txt containsinvalid Variants menu
: N3 c3 Q& U0 w% _* _1272318 CAPTURE GEN_BOM BOM_IGNORE not working for CaptureBOM on hierarchical designs.$ |: p& b! `. _) x
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not openthe Options dialog window.
3 k; J4 \; x2 o5 ]1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object notfound in database
1 S% B/ H s1 O! y1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed
\$ j& h3 V' P1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes nexttime using this command9 g; ?* _* Y7 v( R. n1 n- t6 v: g
1274697 PSPICE AA_MC pspiceaa crashes when runningAdvanced analysis monte carlo for the attached design
4 g! V' \7 y, \6 o- \* y3 i1275154 CONCEPT_HDL CORE Hierarchical Blocks lose refdesignators when moved to another page
/ I8 y: e* }5 E8 }7 u* @1275724 GRE CORE AiDT delete another clines
( i# C* G8 }. N$ `( m1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when usingmulti-thread DRC check
2 I4 D# ^& Q" Q, L, h# e1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
; r8 h' Y2 L$ R) F, t1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem withoutlines' Z" T' [/ R* S: O
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottomOrientation changes; C6 d* J3 }% K c% R3 r: Y
1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allowsplace_bound_top in 0 spacing has drc in 16.6 version.: |) \: Q5 ^4 M. j2 g7 c
1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes2 J, a7 n# s( D! b4 \" _
1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons goneaway5 u" F4 o J+ Y6 S4 L! t ?" g% Q3 [5 g
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inheritSpacing Cset
+ ~7 d/ N% q* ^; J7 M1279815 CONCEPT_HDL CORE Text > Change and RMB Editordoes not allow multiple text edits$ w: m8 R1 ?! z2 l7 n8 x
1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Filletsresults in a pad to shape DRC& t& \! [( G. h. }+ t: _4 i
1280435 F2B BOM BOMHDL with variant repeats thePART_NUMBER value/ F2 t5 U v# @0 n
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in ComponentBrowser didn't work.
i1 {9 Z M+ B7 p7 H1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design causethe DRC count to change on every update6 y4 m! ?. p# M0 k
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needsto be updated indicating that it is a User Defined Property
/ K6 B" O1 V" ~& ~1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted orphantom lines+ g+ ]7 T+ o( n) k8 F
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single ViaReplace Mode" is changing netname of the vias with the latest hotfix ofAllegro 16.6% z. E' w( K$ G0 S% d+ }
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysisresult when add rectangle test bead in Clines.
* J4 F; f/ K. j1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in thedesign after running the Delete Plating Bar command6 t# U' u; D5 g
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does notsupport constraint regions
, P" {5 R& A% n2 n+ X6 I( z: \1288808 APD LOGIC Derive Assignment stalls out orwon?t finish and appears to run out of database room.
* d8 }( J! @% ]8 k# c' R1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) notinheriting new net name from a pin with a new net name.
; w( V& M9 ]2 l7 {7 n% c1289293 F2B DESIGNVARI Warning 04: Cannot merge the variantproperties on variant instance C119 component with same canonical path notpresent
* M. n9 H3 U$ v1289809 SCM VERILOG_IMPORT User not able to import a verilog netlistinto SCM
) z4 j! |4 `& A! l$ p1290696 CONCEPT_HDL CORE Copying a net name repeatedlycauses it to go off grid
3 g7 `" z6 x6 O7 a* V: B1291162 CONCEPT_HDL CREFER crefer crashes when selectinggenerate cross refernece for all nets selected
( J7 P0 e3 x* G. O/ F1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text inWizard causes some Clines to Shift, creating new DRCs.
6 X8 ]- x# g/ d6 v1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
2 ~% _5 }+ f( e% F1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performingquery contents of "Maximum_Cavity_Size" with the skill command'axlDBGetPropDictEntry'
7 q7 T1 i# a, n" V1292210 CONCEPT_HDL CORE DEHDL crash if design wasopened with -nonetlistuprev option.
4 P; ^0 b) N" @# P6 r1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing aWirebond File, (wbt) the wirebonds are not on the correct Die layer
' ^) ?) ]0 Y8 R1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the WirebondImport is open and we select outside the command GUI.) n! [" V- j- I# L! A
1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error
/ X6 Z( {3 [2 d1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted bynetassembler
7 w( R2 q' l) V$ ]0 M' v1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants todisappear the grids in the display window when zoom-out function executes inthe allegr8 d2 i( A8 a. R
1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error thatbreak Thales automatic tape out, f! J' ~1 t8 m g( }
1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEPresult |
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