|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 dsws 于 2013-7-1 20:32 编辑
0 e5 M0 x2 y# ?; Y
; \& @' e/ k5 F$ y% V+ F% ]DATE: HOTFIX VERSION: 012# N) X" n0 [0 d( ~1 g* V. }
===================================================================================================================================3 n! j3 H4 Z M& i, R4 X
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ L3 M) D& L' O
===================================================================================================================================
$ s) k2 k& f: f9 n8 J9 v914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
2 i/ e8 I1 r$ F1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
5 O9 d% l8 G& E; ]* \( H1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
" Y/ }; ~; e v5 j/ ?2 w1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.* C8 m8 S4 G' m' y J" @4 N+ s
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line1 E. C: w1 o# Z2 q5 _" S, l3 X4 |
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.- \" O/ u' g$ E
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.) L' {" Z3 d: S7 Y. m
1151458 GRE CORE GRE crashes on Plan Spatial
" x* r$ e+ t8 d' L P2 g- G, T1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
) \. o( B2 ?6 y, N( g1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
5 M0 z5 m3 b$ \' f, p1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design6 c$ I2 i$ k8 m6 R
1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
8 l4 b" h) ?( }1 u6 k* _: C1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
% x% Q* K$ |2 H0 @! @2 U1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
t) p5 | \) o8 t6 u, I1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
' y/ J% S4 @; t D3 L3 p9 F1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.0 J, v1 f8 c7 }3 w0 F) c4 W
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
8 Z+ F! i1 Q- q3 x0 _4 C @8 A K$ I5 F$ C
" I! _* V3 B" ~http://pan.baidu.com/share/link? ... 0&uk=3826038294& w1 q: {% Z/ p, Y- a
& a% ?9 J/ j3 ?/ q. o# r
3 W, B# a' V" u0 ^ `, _; n
2 v- E* W3 \, E) Z7 I |
|
[复制链接]
/1 
发表于 2013-7-1 12:00
收藏
淘帖
支持！
反对！
