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本帖最后由 dsws 于 2013-7-1 20:32 编辑 , f& D! o2 H2 o- K# y/ v) E
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DATE: HOTFIX VERSION: 012
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914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
- o% ^$ U5 K: y/ q7 E. ]1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files' O9 d+ o# i; A
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display7 O- x) I# L- j6 V
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
0 ]/ ~3 s5 E1 Z2 p9 |9 ?1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
2 L/ S3 y+ m1 k1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
. Y ^& ?" @5 U( y% M1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.6 K5 Q: p; x4 x3 ?7 [0 k4 p
1151458 GRE CORE GRE crashes on Plan Spatial
0 m3 Z) u. Q: x+ @* H3 ^) z) P, W1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
! \. E% S& M4 Z3 h; I1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]& ]+ d9 a! l: ?+ i
1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
. o. H. H2 [' S! N4 g$ S5 a$ U1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
' j/ c8 y: W5 j; C1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.1 C2 Z% M6 j, u. |( Y e
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
) C: K0 n9 ^7 a9 T5 v1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
+ ^, K3 ?( ?3 F8 _1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.( ]6 D, e1 Y8 [6 m" h# T- @0 _
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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0 Y9 S1 U! C8 Qhttp://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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