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本帖最后由 dsws 于 2013-7-1 20:32 编辑 " G- Q9 _9 Z- H& O" B
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DATE: HOTFIX VERSION: 012% Y6 G4 S1 ~+ {* j8 X1 o
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
" j" F0 L O3 u: `/ q! Y/ o1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
) p2 [& A+ t- |1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
5 x1 z' X* S4 y% e1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.2 V& _2 M+ g% p0 ]6 e* G' D
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
# t. s$ S7 F! K1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.% u; ]; Z+ h% r% R) l- ?; w& ^1 T" P
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
) ^( q6 \" v/ N" V3 I( o1151458 GRE CORE GRE crashes on Plan Spatial
I% P- M! ~" `2 S: ]1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
; }# f- Z5 q6 j* T1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]4 ?0 D, J& P3 y* u& R! ]2 l
1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
$ U: u# z; K2 n' m1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
+ b! T `; Y) }1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
- a, K# J* l9 J8 @! S1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places" @" }4 d; U6 J7 |1 B
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail4 Z' E, U4 I! n! E u( K
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
0 b. t: m3 J" J- X: T1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer2 ?* M D" Y% a8 Z' V
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. g( N( X8 Z5 khttp://pan.baidu.com/share/link? ... 0&uk=3826038294: X, W1 I7 j' ?( Q* G
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