|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 dsws 于 2013-7-1 20:32 编辑
3 U6 B) ] @/ m( `) q+ O; d8 T, |& ]7 \- M" q
DATE: HOTFIX VERSION: 012. ~/ s' R1 t, P, n( a' h- A2 }. A
===================================================================================================================================
0 h0 p- u- y/ a8 |CCRID PRODUCT PRODUCTLEVEL2 TITLE
) ]* E9 J2 i3 V4 l9 F* I O; A===================================================================================================================================
; s' i/ P4 @- O914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
( ]! ~9 G2 i8 N1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
1 Y, U) n5 @. U( Y$ G3 G$ g1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
* k A9 V5 A0 [ t1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.( b5 K- `$ o8 W1 T, H1 U( b' x. k% ^
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
+ I p- X. Q( ^1 h* I+ i1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.' c3 h8 C j" y( x0 K
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
5 e) `, {6 K& T3 k2 n7 \1 _5 q% J1151458 GRE CORE GRE crashes on Plan Spatial* a. q0 g+ a' T9 C3 W# G) _) A* z
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
3 e; G1 U0 e. j; l5 y: M( k, F A$ O1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
7 s4 S% N+ }, u" x1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
5 _# B4 ^: J* f& U3 j1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
5 q+ v+ d$ L6 U6 ~1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6./ s: V5 i$ @1 L3 M! b
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
' y! J3 l+ E' p+ x v5 n! Z0 m1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
3 w4 ~4 _! s- U' N1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.; }2 x) u* j P3 d M2 g
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer: f: _6 `6 D% _0 L- y9 j5 J. L r3 A0 C
7 a* |. J2 l1 j# S( g2 p) H+ e% [- r# p+ ?: _1 U W2 z
http://pan.baidu.com/share/link? ... 0&uk=3826038294
! b# H8 K" q2 h/ b* b. ^) y
3 T) D+ v3 L. x1 p, G4 D! `: w5 o' J# i1 ]
, p! F5 K3 z0 u5 T: t" i2 O8 L |
|
[复制链接]
/1 
发表于 2013-7-1 12:00
收藏
淘帖
支持！
反对！
