|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
cadence SPB 16.5下载地址（Hotfix更新至044）
" _# |+ Q, Q8 ]5 y! H2 P Z- q
' D M$ Y9 Z2 T( q/ TCadence最新版软件SPB 16.5及其Hotfix下载链接如下：1 b: A2 n# l6 v! O6 R/ ~
http://dl.vmall.com/c0sfvdb4yy
1 A ?& W$ E8 j( i% D4 b( f7 H c8 M3 N/ `
Hotfix中只需要安装最新的版本即可。: v1 i5 _" f% |) v/ P+ C
5 f" C- g6 b' o- c8 yDATE: 06-7-2013 HOTFIX VERSION: 044
6 [% E2 E# H* e/ v& M) L===================================================================================================================================9 y' P: J8 y; |4 N4 r
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 }. I' @' Z: R& Y
===================================================================================================================================& c6 x7 T1 `" s0 ]4 ]+ [
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
9 N1 Q" s3 X, M+ j1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
2 F# q b' {2 H8 q1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB8 {/ W0 q3 _1 q2 z
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr." N7 X {2 `' h+ f
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT2 ?9 |/ j( c! B$ o
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
9 a7 }( I- K# w* W1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files1 b3 L7 e. ~' o2 T, g
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
, X$ R8 }% l: q5 ?7 b% I, T1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
- d/ q3 k% y1 M \' }' [1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
! U$ ?. i! _( l) a) S7 l9 Y1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
! E) u, i9 p3 @ z1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
, ]* V$ q" E8 }1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
; p, r$ J( y6 [1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux" P4 L0 y* `" d1 [6 [' _) F
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy0 q& L1 [3 ]0 n1 [8 A/ [
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
" z4 h: z3 {: E/ S# ~) w& w1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library/ a: l+ Y2 J* ~4 y
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.' h3 W, o: y: F* S- m
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
; p' E% I' @' O* W& Z1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
* B, g E. ]; m( Q# ?$ |- S1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
7 w# K5 p$ V* a8 T" K( E2 p9 v# K/ v1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
$ G4 ^0 N8 x8 @. j$ p1 E1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.1 Q* q) F, d$ `# h9 R$ p
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
2 D' H, c: ~: }# \. F7 j1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
+ a/ w5 H& B' M) y- H6 v8 e1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.5 Q& Y6 E' I* k4 U2 l- [1 M6 Z2 d
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
- }4 a; \3 |' k+ \1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs! y! Z: v( i( ^9 v
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness9 _' o, E/ U. c; c. i5 z
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped. m$ w0 A1 ~0 l
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
9 l/ Y6 w; ]. A1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF2 H, E5 s5 \/ V: F3 r7 O
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed+ {- Y) R# G% P! M2 B
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
1 v( ~" h/ R! i2 t$ O. D2 Q1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case% l) |7 B$ r( \) ]
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL Q5 d5 x9 m& R" Z) P
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
1 d; r0 ^5 `& f$ l7 S1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
4 d- {7 |8 m8 `" ?+ w; e6 z1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps1 u8 j6 O4 J9 ^+ t5 Q9 {$ Q
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail$ Q# L. G$ D* I$ m: {
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
|
/1 
发表于 2013-6-17 17:16
收藏
淘帖
支持！
反对！
