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cadence SPB 16.5下载地址（Hotfix更新至044）2 Z8 V$ s1 m* u( v7 E) j
( w3 ~( @) f8 t( _8 I$ c: fCadence最新版软件SPB 16.5及其Hotfix下载链接如下：1 ^; q* O, D8 s( \' @6 s, T6 }: J; X
http://dl.vmall.com/c0sfvdb4yy' f+ T& ?6 [( a: U
. f4 \. N2 E3 }Hotfix中只需要安装最新的版本即可。1 k# c: s0 p" O
4 A& V K$ @# V
DATE: 06-7-2013 HOTFIX VERSION: 044& f/ T3 Z f" E& E; N
===================================================================================================================================. i) k K: |8 m+ k- O; N
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 i# T' x* Q) g9 Z. M( w# _
===================================================================================================================================; D* J. X7 j* c% ~
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers+ w: w9 ~* A5 C9 I& K3 E# C
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer, Q& `3 f4 k9 `( d' J- y
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB8 E* ~* l1 i4 c0 v
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.7 h. T) V9 w' t
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT( g1 m# d9 s( Z J( S( i
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
1 P6 a# c+ C* U9 O. l1 A1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
$ |, Z C6 T& S/ s1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor# e6 N6 a$ ]: x# E
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.) f% P2 ^2 r9 Z4 R: c0 \
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically( A5 [' j, M. ]5 H/ f* ^0 b/ y
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
- l g7 ~* b- ^$ H! h: d1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board/ q ?% `% Q# K0 ?2 X
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5; u( e7 {5 J3 j. v% b) t
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux* J' v8 C4 `, H7 W! S
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy. I2 T( ]- U, L! c! C
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
$ ^, e; o- S( m1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library. E: K H6 E' y; P; K: k
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
6 ~$ X7 c. k- b7 @1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters u8 ^: H+ U. u+ K' T9 R
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4# H8 T. X: ?7 P3 s3 P1 }
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
/ e c3 e7 P% x, s) |$ O7 }1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.9 v, f5 y/ g4 l5 _6 |7 T& e
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder. [5 J/ a3 }& z9 [8 W! `
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
/ ?" ^9 Y$ _6 Y# F1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
2 }% @0 r, R& O' G# X y, \1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
g3 l4 K* ^( ]. `% M1 o' N. m T1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property* W M, N& P4 D0 _
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
% z9 x4 h9 n2 o. z0 ^% g3 I) `. m/ ^6 s1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness4 C/ R. _. H4 @
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
% I: k, @1 t7 H# l1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
3 h8 R# m8 @; X1 z1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF! q& g+ S" S* T3 q9 g8 p
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed9 R2 R1 _/ g0 G
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
$ q0 _' x) R; y0 R ?1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case; [! u9 E) G( j7 p0 c
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL5 ~* T$ q7 P V3 S" B
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
$ A' A1 R$ C( j' O( u+ w, d1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
( x0 n8 a0 @& c' e) J1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
+ N& k1 C+ g& B' A1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail- F! p! f1 s2 {- @# e
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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