|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
更新内容及模块：
; x% \" N8 {0 _/ C, tDATE: 06-14-2013 HOTFIX VERSION: 011# ^) j% ~ }2 c3 B7 Q" m
===================================================================================================================================
6 s0 a# Q$ M8 D% g: oCCRID PRODUCT PRODUCTLEVEL2 TITLE" Y% C: G: t: l3 }& |
===================================================================================================================================
0 s2 `0 y7 K# X# _: C S `. P982306 concept_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf
, P3 c9 ^& b* g1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
3 O- E7 T0 V u8 V' H* U. u1093375 allegro_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
7 K/ J6 v Y( L) \2 m) F1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import
7 G; Q2 ^! A5 ~' ~1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT7 ]6 U9 n5 Z, l; y, E9 X
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting
1 ^7 }- q2 f! n" n% k& D8 D% m7 M1110323 APD DXF_IF DXF out is offsetting square discrete pads.
, r3 |; ?% j* _: p4 z1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board) E A) f6 ~! D8 o
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
, x% z( p# @( w: ^1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"
" ]9 e% }+ R7 Z$ g7 U: h. Z1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.6 l* M- Z+ f k7 ?5 {
1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide! N( ~' q' S* D; j1 F" [
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero/ I: X) Z/ E) P: A2 i) F, ]
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP3 `3 G% q# v, }" o; e$ P1 N" [3 [
1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output0 o, M) t& j+ v( O: F/ y
1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
- y. o% e6 B: ], K% j* \4 o% S1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL- X+ b6 E/ g s! G3 P
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
/ `4 r& _; A9 w/ Y: p1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added* J4 R+ e! D- S' g+ v# T7 s& t
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
2 a i0 d0 E* d1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol
+ U0 M) X# v( ?* W1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.; M1 p7 T" }7 [- ?' R
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF- ]! M1 Q: v) U1 ]8 c- J: {
1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid# c4 O# r& R+ ]) g$ S1 H0 S
1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
1 M1 |) ~! M+ ^( H8 b- t7 Y1 ~1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes4 [- c: |) y+ e I% | a( Y
1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols
+ B# l* N" P; l7 o; n/ t
9 Y* j. P9 R! _, s) @6 M8 `0 } Q
( f3 K$ Y2 H f下载链接：
; ^& g" |/ E& l0 H1 p8 E, Ehttp://pan.baidu.com/share/link? ... 5&uk=38260382948 b+ F( Z" }5 K: j
|
评分
-
查看全部评分
|
/1 
发表于 2013-6-16 15:39
收藏
淘帖
支持！
反对！
期待16.7.。。。。。。。。
