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更新内容及模块：: k' R# A0 Y6 S5 y4 `
DATE: 06-14-2013 HOTFIX VERSION: 011
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) f# p1 `6 g S7 m: |; @$ l
===================================================================================================================================* b N+ i1 l, x }
982306 concept_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf7 M3 {9 ]- n1 j/ K2 v/ q- o
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers, U5 r1 v0 P& v r! S
1093375 allegro_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
/ s$ z0 N5 [; y2 F7 P! y `, Z5 o1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import
# F) f9 t/ M* X9 q1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT5 E+ S6 A9 F9 g0 }+ h0 N8 m4 q' j
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting
8 U0 x& m" X& S& Y$ v, I; ^1110323 APD DXF_IF DXF out is offsetting square discrete pads.5 E- C; k u7 \: w
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board7 a7 w- s, Q g7 o1 P0 l1 J
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.: I2 z0 L5 e( Z' ^; e4 q
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"
5 u# o7 y! y/ w$ O: X: u1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.& |% o2 _* p3 {- c4 ^
1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide: _" o$ L! w( D& B+ o, u+ i$ U
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero( W1 ~( v% |- E2 d# }& p
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP+ a5 ~+ u7 \) H5 c$ u1 G3 R H
1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output
) j" X! K# { T1 B$ L% Q( _: f1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
" M- X9 y* p3 {/ f {4 F1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL5 ~7 A/ j/ c7 _* M
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
4 O/ K9 ^3 ]/ ~, [1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
. A8 `( @# z$ c7 A1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
7 \0 Q D( m8 v/ d% B1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol* [& F( r3 s9 O" G' ]
1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.* k- G6 ]7 X1 ~7 d2 v8 f( e
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF
- i; T3 S3 i. M# g1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid
- ~1 }: l: n1 P! v1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()5 y/ Y5 u$ ^; G4 [/ Q" @
1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes
1 e5 J5 t* y! O1 F, g6 Y3 U; s- ^1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols
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9 H: S9 D3 `; L1 z, v$ h下载链接：
1 |, M! Z5 n1 ^/ c+ Z8 ?' s/ mhttp://pan.baidu.com/share/link? ... 5&uk=3826038294
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发表于 2013-6-16 15:39
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支持！
反对！
期待16.7.。。。。。。。。
