|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至038）4 O0 m/ z4 y2 k/ p
; s* ^ S) H/ G$ s* k3 m( W; X7 Z% S5 v6 A/ P& {
% q/ G3 o7 L1 b/ I& u
下载地址：http://dl.vmall.com/c05sb7i5ed
( I" _$ [0 p" r, a2 w9 u, O! c4 c1 Q& g. H" [
! @9 r' i+ S( h# ?1 T' I( _
Hotfix中只需要安装最新的版本即可。
0 n' {, ~+ J& e" t' ^' [5 |+ S5 q5 |8 ?7 ]1 {
Hotfix038对以下项目做了修正：0 Z0 a2 o! y, a3 X& J1 {# [5 p
DATE: 02-15-2013 HOTFIX VERSION: 038$ ~- l' W2 L* @3 p8 y M
===================================================================================================================================- ^4 q( ]5 n0 R4 ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE' V+ J/ t9 [; a3 ]' W4 O* E3 i# d
===================================================================================================================================, R7 u& O, D# N# I+ Y3 Y
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics" f2 b7 k# O* Q5 V, x3 n& d3 n
911292 concept_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately* K$ H& A( H0 P# l. I+ J
995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.; I, E/ O" \7 C, G- _/ u: b# s
1005812 F2B BOM bomhdl fails on bigger SCM Projects
/ i. t4 S6 o9 C9 ~, o/ S1 v1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
" m# n0 x3 K8 x* ^1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer
( g% z5 W2 ^& X) N. @4 e1065636 CONCEPT_HDL OTHER Text not visible in published pdf' N) _* e2 l+ q! o W
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts, G) Z* t0 D. J& z/ p
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
" B/ l; k, Q( W' u4 ]1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
& W4 ^, o5 Q& L* H% E+ A" B1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher' G" h0 {! S4 M! S9 }4 }3 j1 }
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
! }' B0 I9 g9 E1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
( W0 V0 m4 ~; a/ W1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
; i o& k: u7 a, |' p1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3/ }2 V- q: F( Z: V' [, Q; j; B7 H
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor q" e& d; H. }- u) d
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
- X% V+ k* g. ^, M* Z1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.; J( W6 S$ w5 N% w+ k( w7 Q
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff$ |( B F: }2 l- L O* w
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible' J; `5 j% O7 }; W/ X
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35: b% V# w. \( }! H/ E5 m
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.5 O; I! f R8 u9 L8 [8 Y0 k
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
7 r5 {' X+ L+ F l8 i1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.: `& R, |! c) _( y+ j" a9 v
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend( L3 Q0 {/ K2 S
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors0 H2 _4 w$ U4 w& E
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
. m. v; H+ K# ]; T8 O. [1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
|
[复制链接]
/1 
发表于 2013-2-24 21:41
收藏
淘帖
支持！
反对！
顶起啊 好家伙前几天才看到28的 现在都有38的了