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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 + P+ k: g! [7 p
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下面链接是cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！
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Hotfix057更新的内容如下所示：; ?" {+ x- W, Q! t( `
DATE: 12-19-2012 HOTFIX VERSION: 057
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
# X& w4 I d+ L===================================================================================================================================' z3 r* H0 a0 C+ ~% K7 r& K
1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
4 ^4 `% m/ [7 N g' S1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.( V) W0 x5 i3 u9 e3 Y8 e/ c
+ X. S( Y4 x& N. xDATE: 12-7-2012 HOTFIX VERSION: 056
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CCRID PRODUCT PRODUCTLEVEL2 TITLE7 w) _* x, H$ c
===================================================================================================================================
" a5 N+ U6 X3 l' ?0 v825813 concept_HDL CORE HDL crashes when copying a property from one H block to other
! k% Q1 t/ N1 T: s- _) L9 U871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash* y, T( Q2 B# B/ _. A6 l
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide* e2 f( W3 \! S2 o: M& E$ N5 T
873917 CONCEPT_HDL CORE Markers dialog is not refreshed$ r5 S( A5 a0 t3 E1 }0 y8 W* ]0 p
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License+ P H1 Y# p" s# F! h7 H3 O
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
! ` d( g4 i Y; O& l6 H- l: y1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
5 T3 B7 b4 q/ N c x! O1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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