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cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
) }# c( s3 m9 i4 g1 qhttp://dl.vmall.com/c0t5v9lbyp
" K. D( p5 ?+ Q) n$ G9 r- @Hotfix中只需要安装最新的版本即可。
p- r' ?( W% E: D( ~9 q+ J; |9 m
4 p4 g; U) h& V- q5 _& ]& y" NHotfix033对以下项目做了修正：& M$ i9 F; s+ r* `& N: ^5 I9 X
DATE: 10-31-2012 HOTFIX VERSION: 033( c* {0 B6 s" O1 |
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) b" V- X0 u* ]* ]. ~- N- FCCRID PRODUCT PRODUCTLEVEL2 TITLE: G" [7 \* H" Q& i
===================================================================================================================================
5 u9 f- {$ c( Y- k5 j+ i103395 COBALT-COMPILE COMPILE et3compile fails if compile for 3 boards in 32bit mode
0 Z, i6 [: D, n$ O1 b Q715653 Pspice MODELEDITOR Change in pin number assignment with model import for capture symbol
# m) m* }$ }3 A( j745682 concept_HDL CORE Attributes window requires resizing each time DEHDL is launched
' a' C3 U- D g4 G) u+ V( q825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
3 @% d) }5 M% P846658 CONCEPT_HDL CORE About Change the NOTE with DE-HDL' @# @1 t# g, B- W- \, |& f( N& o
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
; f# o( C8 d# N942044 CONCEPT_HDL CORE ConceptHDL crashes while opening the AMS project
7 A) n0 i5 P/ h( _946640 CONCEPT_HDL CORE Import Design should inherit module order defined in the imported block
$ R! U9 r1 ?0 @' S: g' z968646 allegro_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing2 i/ Z. v* }) D( \# `) v& S
969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
4 F4 w' i6 L$ Z# X0 q976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
/ O' G' t9 \) h% l2 O981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
3 H6 l9 b% j7 F6 X988355 PCB_LIBRARIAN CORE PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
& w, G6 v5 I" A; M' H0 I; R988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
4 q7 q; a6 m6 h$ N6 L993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).+ \2 q- E. g; Z# v
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
& F! W; W+ Y3 ~+ k# c3 D8 @997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1 D8 M: T+ l* Q( d1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model0 g$ B: [0 Y; t' ~7 E
1006400 SCM OTHER Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
2 W5 y+ w. M+ \" t6 [- X1011502 CONCEPT_HDL CORE Undo has an error on circle in DE-HDL during create a schematic symbol* `. o$ _$ O W% B1 ?4 Y6 l, s
1011798 ADW LIBDISTRIBUTION generate a differential report on parts in DB vs parts in PTF while running lib_dist
# w! P8 Z: g5 _( d1012685 SIG_EXPLORER INTERACTIV SigXP: traceEtchFactor value is not used.
" ]3 M5 d4 ?7 @& {8 I9 ?1 u, p1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg# o- f7 C3 t9 s! M) D2 |+ t
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
& U! o; p7 s3 O8 ]5 n8 f/ R1014319 CONCEPT_HDL CORE renaming HBlocks leads to crash
# ?/ A6 o. [ o1017724 ADW TDA TDO update should force the schematic to re-read data from disk
n+ v/ R6 X% y' Z* Z* _* m1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin2 Q2 f# o! _' `4 w0 N/ M9 T
1019979 SIG_INTEGRITY LICENSING extracta batch command result is incorrect) @$ K3 ?4 i9 z7 x# ^" _( q
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
+ |, u* ^) Q) O2 X# o+ a+ k$ F' z1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140. Y- @. d1 u: `0 t0 ?
1023057 CONCEPT_HDL CORE Strange message when opening DE-HDL - INFO(SPCOCN-2055). D$ S" x2 Y3 D: D# m) V/ v0 ]
1023281 PSPICE AA_PPLOT Bug spice advance analysis parARMetric plotter stops after 6000+ runs
# P# D! q4 A5 `* _' Q# ^* L& s8 `8 e1023702 CAPTURE GENERAL orcad Capture/CIS copy and past page to other design Issue
8 G" i ~* E: Y2 ~1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
5 r8 i; g% k7 S1024890 PCB_LIBRARIAN METADATA con2con -metadataonly does not find footprints, r% Z/ @8 V/ D( {0 B" `7 J
1024899 PCB_LIBRARIAN CORE PDV symbol pins grid select all does not respect the filtering
; V" V# k; ?* }$ ?& n8 Z3 V0 ]1027147 CIS UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist) k `7 \" _' {! Y* ^ s4 p, i
1028432 SIP_LAYOUT DIE_ABSTRACT_IF Support pin numbers in die abstract flow8 [" G- w# B) u& O% B7 d
1029369 PDN_ANALYSIS EMVIEWER EMViewer: Unit of Current Density.
; M! ?7 B; E& n# Q c1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
# k" J- l) z- J% G1031474 CONCEPT_HDL ARCHIVER Uisng Gtar as the compression utility causes the 'delete archive' to fail, c9 x. X4 o" p. u" p9 D4 O
1031765 PCB_LIBRARIAN OTHER librarian_expert feature is kept checked out for two hours* ~# _. F5 A( v; M& Q
1032703 F2B DESIGNVARI Enhancement Replace Variant Component form needs to be resizeable( Q+ n* \$ w: N: [$ O. w% q! r
1033607 CAPTURE NETGROUPS Capture crash if netgroup instance name has square bracket 縖�
- ^$ T: e- g; w, ^1033853 SIG_INTEGRITY OTHER netrev crashes when importing logic) r; [7 f) U m7 P& e
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product- y! l m5 `$ B- P
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
. j3 T4 v" a3 d. `& T# v4 {1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)% W2 s0 \, q; ?6 `8 u9 U3 ?
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol7 V ^5 q q4 \- {. M/ p/ [. d
1038285 SCM UI Restore the option to launch DE-HDL after schgen.: ?# ?! p' _( B6 u% d' x
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing$ ~% z; n% k+ `
1040257 CONCEPT_HDL INFRA New license files causing slow tool peRFormance5 v) r+ d- C; h* B- F0 z+ q2 E
1040575 CIS CONFIGURATION SQL database views are not visible in CIS configuration step 2.& ` V% p a8 U- d1 ~
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
+ J" h2 I' h4 {6 A+ ]3 d1040869 CONCEPT_HDL INFRA About uprev problems to SPB16.5 from 15.7+ H* q! b' l, _
1040976 PCB_LIBRARIAN CORE PDV replace pinshape on Linux shows very slow performance compared to Windows/ M) ^( v8 K# C) g' q
1042603 PSPICE SLPS About SLPS simulation interrupt
' e& |) Y; {- v" d1042695 CIS CONFIGURATION Can't see database views of an SQL database in CIS configuration! {/ w+ a; F0 R# f+ ?/ K& V. W0 p
1043339 CONCEPT_HDL PAGE_MGMT The .con and .xcon files aren't being updated.
X6 q' e- K5 o1044029 PSPICE ENCRYPTION Encrypted lib not working for attached/ A9 `; [! k# L5 H7 C+ z t8 u
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
0 G2 R' H2 O% d/ w/ M! x0 ^8 L1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
' _( G7 l5 d1 `8 G2 Y1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
1 ^" Z2 }( }) c% B8 ]( t% a5 S) W1045609 ALLEGRO_EDITOR PLACEMENT Statement in the Viewlog for Update Symbol needs correction
+ a- }0 E6 W" V" N& G) U4 ~4 S' C1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?# a. T9 v W8 K3 S- R
1045734 ALLEGRO_EDITOR OTHER Missing padstacks and layers information in cross section chart2 B+ _8 V, N3 B% d$ L
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
3 n6 C L0 }$ w& O' [3 O) E1047361 CONSTRAINT_MGR OTHER CM fails to convert static phase tolerance value to database units.$ j: Y5 j) G8 Q* K) O, M+ I
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll7 u" D: d! o* b1 R" h
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.+ V3 U9 `+ F) [& I4 c- O _( r
1047869 CONCEPT_HDL CORE How do I define a custom pwr/gnd symbol for correct Verilog syntax?$ @2 \# l9 Y: ?- {3 G
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
5 s, Q. [! m" P& M) @9 D( J- m1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5- {3 _7 t) p1 f& y8 M3 e# O
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value8 U$ p8 T, i. L& z3 {9 M
1049993 ALLEGRO_EDITOR EDIT_ETCH Loss of Y axis when adding via in manual group routing& h8 z$ b6 x5 m4 |* d+ E
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
. H/ }. E2 m6 b3 o6 o; z1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes5 L. m, ~+ O" K, P+ a7 c
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
! z' n0 K& J: `7 k0 n1052056 ALLEGRO_EDITOR PADS_IN Pads to Allegro translator fails with error message " ARSE ERROR: Wrong label format:Translation aborted."
* F8 Y! `+ D3 \! b+ I9 o1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
+ V4 W+ e' U+ T8 T8 ?1052479 PSPICE PROBE Cursor2 (Y2) displays the same value for all traces5 B% u7 g4 t% x+ U1 S0 d% c
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
Z ~( E7 y& S2 |1052817 CONCEPT_HDL CORE Getting packager error after renaming nets+ p: y7 |7 x- U; i; \1 ?4 T9 f( K
1053319 CONCEPT_HDL INFRA Change in property scope in windows mode is not retained! p/ x; n* w" [
1053602 CONCEPT_HDL OTHER Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.2 r, {8 t! v& q' R1 w: }4 x
1053660 CAPTURE PROJECT_MANAGER Find Part Pin name or number is not working7 W- k% X8 r1 }% Y
1054010 CONCEPT_HDL CORE MAKE_BASE2 ?. }2 e9 M9 ~1 N! D
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.9 t, `) b7 w! s
1054846 CAPTURE PROJECT_MANAGER Crash on pressing Esc key& u7 a/ p( p9 B5 ]: m7 P
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
; s9 V: l5 a2 K Z2 B- `1 E1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
" X1 p- g1 I8 L1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.. ^$ c) x! [8 u$ J4 e" U
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline) I& A5 R! |: @
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
& I4 `6 \' \9 d S1058364 ALLEGRO_EDITOR skill axlTransformObject() is moving refdes text when only symbol pin is selected for move
7 ^3 |1 f6 C, G1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value* F3 V, K) ?! E" ^
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.) h+ i2 Q$ Q% U9 k5 s: R
1060428 CONCEPT_HDL CORE ADW Flow Manager Copy Project fails to complete" b1 ]3 h) ]' j% P
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
! `7 K1 O; _$ |! c# v% i% r1061172 CONCEPT_HDL CORE Unable to delete Voltage' a! n' e! o9 v7 o0 [6 u7 Y
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
! ?2 S; N) u2 j8 B& A9 X1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00. a" o q" I! M& [
1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.8 T X }+ ?2 w, e7 f! D
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
2 k5 C/ C1 N+ e+ H4 q" P1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
; J Y; s% D( n8 k8 ]1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV' V" v+ h$ F$ Z( }; g
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application/ X8 U- ?( q l
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
' x9 y5 U, u! J. H( d/ z1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC+ ]4 R8 }6 D* N# _1 g
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic3 Q% M" b g! A3 M# P( X. K k! q
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
$ [' r$ _3 l" ^* a# y; ^ |1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
; z4 ]5 P" c7 s' A" Y5 p' [, z [1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
0 t) `% A$ Y7 i. ~2 J1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
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发表于 2012-11-12 09:17
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发表于 2012-11-14 00:38