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大家好!有人知道这是什么问题吗?,我仿真PLL的时候编译通过啦,起动仿真的时候调用(ModelSim-Altera)错误提示如下:
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, D7 y* G, O+ x" Q' s$ W( ` m# Loading work.PLL_test( v2 {1 ^( n# r- ~
# ** Error: (vsim-3033) E:/FPGA/mypllexample/PLL/simulation/modelsim/PLL.vt(22): Instantiation of 'PLL' failed. The design unit was not found.2 V9 @8 w+ Q8 R! C6 F
# Region: /PLL_test& t% l* W% w& ?
# Searched libraries:
' @# O# i+ m, K+ o0 r$ }+ |3 u# d:\altera\11.1\modelsim_ae\altera\verilog\altera# K9 a* t& y, j- c
# d:\altera\11.1\modelsim_ae\altera\verilog\220model
' V0 l0 H& |2 r+ c2 _& E, X# d:\altera\11.1\modelsim_ae\altera\verilog\sgate
0 X9 A7 ~* ~! @0 R0 ]+ x7 s6 I# d:\altera\11.1\modelsim_ae\altera\verilog\altera_mf4 N8 h5 ]7 \1 ~% X2 t" p
# d:\altera\11.1\modelsim_ae\altera\verilog\altera_lnsim
/ d) A! @6 q5 A7 z4 `# d:\altera\11.1\modelsim_ae\altera\verilog\cycloneii
* h4 O8 n. A5 U: ?% o. ~+ a* |# E:\FPGA\mypllexample\PLL\simulation\modelsim\rtl_work2 O' Z& Y5 [- j0 \5 t1 s7 k0 E! n
# E:\FPGA\mypllexample\PLL\simulation\modelsim\rtl_work
, i; l& V* d$ _( @$ F# E:\FPGA\mypllexample\PLL\simulation\modelsim\rtl_work& ]7 b% R& v, k* N/ |
# Error loading design3 W3 k; P& w0 f& c) V6 E, q' e
# Error: Error loading design / P! i) ]* i9 z* K* H
# Pausing macro execution 3 B+ T" i- {2 `2 i$ J; e& ?
# MACRO ./PLL_run_msim_rtl_verilog.do PAUSED at line 12 |