modelsim仿真错误的问题

MrL1

最近在学习quartus ii 的ddr2的ip核，编写了一个程序，在程序中实例化了DDR2的ip和，想用modelsim仿真看看波形，仅仅是功能仿真（RTL仿真），但是仿真出现了很多一样的错误，如下，请问各位大神遇到过这种情况吗？是怎么解决的？

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_MEM_IF_CS_WIDTH' not found for override.
#
/ K% y' g0 O8 ^4 W8 o) ]2 f#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
6 T; F) N8 |% ~7 l, S+ t' R* w# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_RANK_tiMER_OUTPUT_REG' not found for override.
2 `/ b7 b  t4 U# V#
7 Z4 I. P. o( ~" e7 z9 R* x& ^#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
8 p& @& x- r. ]  q' ~7 [# t) h# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2328): Module parameter 'CFG_RANK_TIMER_OUTPUT_REG' not found for override.
#
2 t. p  _3 n7 U. H4 E5 }  Q#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2508): Module parameter 'CFG_CTL_ARBITER_TYPE' not found for override.
#
. x/ d- N7 Q' q" y* b, m#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
, e' i( R! o7 [5 R8 f# Loading a0.alt_mem_ddrx_mm_st_converter
* h9 Y. G7 H4 ]# Loading oct0.altera_mem_if_oct_cyclonev
# Loading dll0.altera_mem_if_dll_cyclonev
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./ddr2_ceshi_run_msim_rtl_verilog.do PAUSED at line 214

rergr

没在modelsim里添加仿真文件，你可以添加一下，解决了的话给个反馈，没解决的话截图看一下

芦根苏木

是你的参数在仿真中没有设置好吧
: C( ^) D0 E3 E9 j0 T