CPLD警告求解！！！

cskgj4

Warning (10631): VHDL Process Statement warning at my_latch.vhd(37): inferring latch(es) for signal or variable "out_0", which holds its previous value in one or more paths through the process；
( @3 N. |0 J. c+ w7 K7 |, `Warning: Found combinational loop of 1 nodes
! n% [. G: p0 x, H        Warning: Node "my_latch:inst14|out_3~16"；
$ D/ d" c) D9 M这两个警告如何消除啊？？
8 r6 q( i' _, ]
Warning (10631): VHDL Process Statement warning at my_latch.vhd(37): inferring latch(es) for signal or variable "out_0", which holds its previous value in one or more paths through the process；
" H; p  T0 f( b9 s% P. j- o这个警告的话，是因为编写VHDL语言时，用了不完整的IF语句，产生了锁存器，为什么很多资料中提到在VHDL语言中尽量避免使用不完整的IF语句，也就是说尽量不要使用锁存器？？但在实际使用中确实需要实现输出锁存，该如何解决啊？谢谢啊！！！

suxiaoli2000

语句不完整，如果是if加else  如果是case加default