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画完原理图后,导入LAYOUT时,弹出arsii.err文本文件提示以下内容:8 b. d$ [* Q7 c% b5 C
. q, Z6 p& o5 v5 N3 ] r
Reading file -- C:\pads Projects\padsnet.asc. r$ E) Z6 w& M* o
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C5' m. a) P0 a. x* K1 d7 D& q
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C4
( v8 z1 r+ n3 c6 l. V*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C33 g) x( P7 {0 f# G& g/ E
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C2' K8 u) J) d1 [- `
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C1% M5 l! J n# r/ ?
Warning: deleting signal C5
# h4 \/ [ u' g6 r6 u3 hWarning: deleting signal C4
) ~6 k! k9 _) x; Z1 u" Y* qWarning: deleting signal C3& ^/ ^2 [0 c+ Z+ e
Warning: deleting signal C2
9 B" Q K8 ^" y, A3 E( OWarning: deleting signal C1
' |6 z' q' \$ K6 F! _**INPUT WARNINGS FOUND**
8 ~7 S3 x* q0 R, ^4 k8 k! {
! }2 |# D7 \' U. Z' ] @ g. E我检查了下,封装和连线应该是没有问题的,并且在这个原理图中,除了以上所提示的C1~C5之外,同时从库里调出的这个电容也用在了其他位置,却没有提示出错。. W' r2 h+ g& T% A+ e
想请教下各位看官,这是个什么情况? |
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