讨论下CPCI问题

yuzengshu

# |( C, o& ?, tCPCI 分为系统板，背板，外围板，对于外围板有死规范，但是对于，系统板，和背板的规范
，见的不多，就是对于系统板，时钟线和数据线的长度有没有限定，还有背板，时钟和数据长度的限定怎么
计算，希望做过的朋友，给点经验，我的是PCI TO PCI桥出来，在到CPCI接口的，谢谢
* L) Y# H. F! `1 K6 G% Y1 w, d大家看看这段怎么理解
4 c" v5 L( J, f- X% g1 The System Slot clock distribution circuitry shall be designed to accommodate
6 N$ ?  U! H, j: f5 eup to 200 ps of backplane and peripheral board skew. The following design rules
5 y: m$ i& Z4 K' A  f  oapply to clock distribution to backplane peripherals and local (onboard) PCI
peripherals
2 Any onboard PCI peripherals connected to the CompactPCI bus, including
PCI to PCI bridges, shall be provided a clock that is delayed to
accommodate the maximum propagation delay of the backplane clocks and
still meet the 1 ns overall skew requirement. Up to 800 ps of skew is
7 `1 |/ }% ?2 i$ x9 C" j, \( J+ Rallowed for onboard clock distribution (including the clock buffer internal
skew). The onboard clock signals shall be delayed beyond the clocks routed
3 i% |4 O  p6 \4 K# x2 a3 l7 kto the backplane (Section 3.5.5.1) to accommodate best and worst case
$ U( V  {( D1 Y: m# d' Zbackplane delays and the 63.5mm wire delay on the peripheral board.