求救—谁能帮忙改一改

zhong0985

library ieee;
+ l# s8 ~( a4 y, e" w8 O2 s7 \/ Uuse ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
( M! \! _6 i" ?: @& a& H0 L8 z  hset:in std_logic;
1 }" f1 z# S& [6 A  sig_h:in std_logic_vector(2 downto 0);
  din_h1ut std_logic_vector(3 downto 0);
3 ^. H, E1 ~3 s0 S  din_h0ut std_logic_vector(3 downto 0);
  pmut std_logic;
9 b6 {6 w# q2 F. ?0 z4 v4 @% `  cp_h:out std_logic);
3 s, g) ^- B: |) e, X  
end hour;
architecture behav of hour is
signal clk:std_logic;
4 g' T8 Q- P6 M$ Tbegin
) R9 b0 n  c# v* C/ @* [    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
$ ?3 |- V% `; ^: D& k3 l     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
     variable co1:std_logic;
, ^6 K$ G( S6 h" d! h5 r9 t& p( s     variable co2: std_logic_vector(7 downto 0) ;
   begin
    if sig_h="001"and tp_h='1' then clk<=clk_t;
   else clk<=clk_h;
   end if;
/ Z* ?: B: q. i( V2 h1 }* D    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
            if  cq2="0010" and cq1="0100" then
* o( ~+ d+ H1 V" N  `9 C! Q; l    cq1:="0000";cq2:="0000";
    co1:='1';
  [% z  R! B5 G. E* w! }8 ]" h% |   else co1:='0';
      end if;
      if cq3="1010" then
) u1 j; m2 O1 l. [7 c      cq4:=cq4+1;
      cq3:="0000";
    end if;
8 N( i* {- U' b; J0 v6 J8 A; u   if cq4="0001" and cq3="0010" then
2 [, w8 a' @% c+ Y         cq3:="0000";cq4:="0000";co2:=co2+1;
      end if;
    end if;
  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
         else
9 m4 H& c8 h5 W. x5 c, c           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
             end if;
1 A3 I$ B) F7 M' x8 Y$ g; y             pm<='1';
. H# E) {& h" ]- y            else pm<='0';
+ J8 R( e: P0 f" D- |            end if;
            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
              else cp_h<='0';
             end if;
4 O: C- z. _) {$ m           din_h1<=cq4;din_h0<=cq3;  
" O  m' k$ z& I4 J5 T        end if;  --12/24转换
  
3 `$ [) {* s; I4 `) z) A     end process;
end behav;

zhong0985

报错：
& Q# x+ m$ k) NInfo: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
' E7 a% T6 C& u' G: u! b2 \        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
% a4 q  K7 T- z; G) l; T        Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
" g, l/ ], e; F! k6 a* t. n) O6 K1 eInfo: Found 2 design units, including 1 entities, in source file hour.vhd
        Info: Found design unit 1: hour-behav
( o: ]2 m) {( ^: D. ~        Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
# m$ E. s( f% EWarning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
: V$ F) K  c$ _5 k: [6 OInfo (10041): Inferred latch for "pm" at hour.vhd(20)
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
1 A* j) w' u  VError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
' i3 z, Q" p0 N8 Y2 n$ I$ @Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
) S- C$ m( c; A. mError: Can't elaborate top-level user hierarchy
+ h& O' Z! K' ?' X$ pError: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
        Error: Peak virtual memory: 184 megabytes
6 `3 y% ]' A- k0 [2 F; `  A5 ?1 T        Error: Processing ended: Sat Oct 31 17:04:04 2009
        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
. H( l; v2 ^8 OError: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings