问点Quartus II 的问题

sutee7907

为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
4 g9 ~8 K$ K& |5 TError: Verilog HDL syntax error at mult_tp.v(3) near text "'";  expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
1 |7 n# [5 a* ~Error: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
5 s, Z  S. c2 t2 t9 Y( E9 ?7 Y源程序是这样的，
) u  h+ t. }/ S, [4 S7 z# n'timescale 10ns/1ns
module mult_tp;
reg[7:0] a,b;
wire[15:0] out;
# [2 O9 [! X/ [9 `% Einteger i,j;
3 _+ W- E* _9 x* R# P7 ]mult8 m1(out,a,b);
, B2 f5 Z" r9 einitial begin
        a=0;b=0;
        for(i=1;i<255;i=i+1) #10 a=i;
end
* R- j. t4 i& P9 {7 G; t( f. I2 Xinitial begin
; |% d! a  p' M$ V  \        for(j=i;j<255;j=j+1) #10 b=j;
( D% r  W5 e3 S                end
initial begin
* W+ ^! a* w, {7 u% Q/ j7 E9 i        $monitor($time,,,"%d*%d=%d",a,b,out);
        #2560 $finish;
        end
" L1 z. n7 c' \endmodule
" I/ K( Z' T4 q% Qmodule mult8(out,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] out;
assign out=a*b;
' n& C* l2 J6 _( m( z5 g( b, bendmodule
5 n- @# `5 \" _请问还需要设置什么吗？时序和功能仿真都有错。

maochencw

是`timescale，注意那个点，不是'是而是`

sghgfmu

回复 1# sutee7907


   就是二楼所说的问题呀，那个·是跟~一个键的那个点