我用cadence16.5 conceptHDL设计原理图,完成后道pCB,我使用的Top-down式原理图设计方式 - V* @& v4 _' A! l5 s. g* h导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL"5 c0 Q: ?. P& b& W2 D
* h/ l" S) ]! E+ i' g这个是由什么问题导致的?6 M6 x8 Q, a( Z) M$ N) e, d