我用cadence16.5 conceptHDL设计原理图,完成后道pCB,我使用的Top-down式原理图设计方式 : L) N" y/ x) |* \2 e导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL" ; F3 Q1 u8 H8 T' V! u" m/ M7 f7 ~& Q6 u" |
这个是由什么问题导致的? 1 G, O6 H6 P5 l. g& c