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PCIe Gen 3, DisplayPort 1.2, USB 3.0, and SATA 6 Gbit/s PCB Layout General Rule6 I" x6 v; e# f5 X
2 p3 H# a& Z/ _- Maintains 50 Ω ± 15 % single-ended and 100 Ω ± 20 % differential impedance.
- The differential pair must be routed symmetrically.
- The length mismatching within the differential pair should be less than 5 mils (0.127 mm).
- Do not route high speed signals over any plane split; avoid any discontinuities in the reference plane.
- Avoid any discontinuity for signal integrity.
- Differential pairs should be routed on the same layer.
- The number of vias on the differential traces should be minimized.
- Test points should be placed in series and symmetrically.
- Stubs should not be introduced on the differential pairs.4 I1 B& y& N# _6 R- H4 K
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