|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 zgyzgy 于 2015-10-10 11:35 编辑 9 @3 I. p' U' s6 E- g
8 V1 X! I, p- e( w- A. I, z S
昨天刚出来的。。。。。。5 ^+ w6 J% D- B' j, g1 j) k( U
+ T- K" I) W; tDATE: 09-31-2015 HOTFIX VERSION: 059, S. B6 ]7 @" v
===================================================================================================================================8 `5 v- ?: E' X0 M! H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
]$ f6 P D+ T" A p: G===================================================================================================================================
$ F* }: U( f5 m$ A* `0 M4 D* S# @! Z. q1181942 SIP_LAYOUT ASSY_RULE_CHECK ADRC reports different results from the spacing set-up
9 z6 f+ A8 H% b, {1 [2 F9 R0 @1328452 allegro_EDITOR INTERACTIV When changing the shape type, Right-click - Next does not work for subsequent changes) }1 U2 j6 \0 O1 K h
1441502 GRE IFP_INTERACTIVE Design partition cannot be imported.
( u1 S5 O6 T* T, L1457920 SIP_LAYOUT OTHER Wire Bond Import is not working correctly with discrete parts2 s0 r- `! Z3 N. O; a
1464865 concept_HDL CONSTRAINT_MGR For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM1 m# t" ]0 d& `/ P" z- }/ D
1467365 ALLEGRO_EDITOR OTHER cadence cshrc for LINUX has an extra space in it.
: [# E, b2 I. g1473744 ALLEGRO_EDITOR INTERACTIV The 'Chamfer' function does not work correctly if the second Trim Segment value is specified instead of the first.$ y9 O( r6 i1 M# I! A$ |
1475599 SIP_LAYOUT SYMB_EDIT_APPMOD Refresh co-design die of an enlarged die is not placed correctly9 m$ ]1 S/ J7 u9 M: Z, f9 D& x
1476284 CONSTRAINT_MGR OTHER Changes with Tpoint pairing not being propagated to the brd file% r9 d1 d3 y2 B9 L
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown" H( S% Y; j; @* t
1476855 ALLEGRO_EDITOR DATABASE Trying to import Netlist, getting SPMHNI-194 error6 f6 t" V" k8 a. `) \: j$ m
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
- n. L7 W4 z5 w$ |1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release6 b7 d8 `; l: j" I3 t! n* k: E7 [
1478225 SIP_LAYOUT DIE_EDITOR IOP incorrectly rotates pins at a co-design die
' w: Z' {2 ]4 J! ?& V- X1478465 SIP_LAYOUT WIREBOND Ability to set default bond wire option to on for wirebond import/export commands
1 m7 r6 l! W' Y0 u9 [, v6 l1478994 SIP_LAYOUT skill axlUIMenuChange does not work on Linux
: d( Q" j8 M/ A- u! i7 @# F# G: j1479023 CONSTRAINT_MGR OTHER The cmDiff reports different data when files are reversed in UI
0 @# E$ h4 e t9 L% |# O1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO) Q0 C1 {6 g" k7 Q$ ?4 o0 C
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'
6 Z7 ?( t7 N( x* i ^3 p1480538 SIP_LAYOUT DIE_EDITOR CTE compensation is limited to 3 decimal places, can that be increased6 w3 F$ T. _7 R+ i& T' i
1481109 APD MANUFACTURING control Package Design Integrity for snapping the via to pin
( y8 C6 R, `' w7 y/ _* h+ O1482771 SIP_LAYOUT WIREBOND Fingers and wires cross when moving the guide path
. _* ]1 A: q; z7 C. t9 |7 A: n. r I' L. Q
正在下载文件中，稍后分享链接。。。。。。0 a1 \3 L6 k- o+ F. k
7 [6 k/ d3 U/ J5 h$ L' P
3 k% Q- Z& P; K9 e6 r: B- \1 A" r
( ]; E' x, _2 S/ x+ s( C: }
( \% @1 n* G) _: }" x# B: B! `
* J# g+ G: x6 h' q) k' S" J" e2 y
( I# q/ D0 x7 H7 P) M
; l; `- z4 F4 D# k" h0 q9 o# F8 }$ M& z9 E" r
6 O- k. K/ t# e1 t `4 Shttp://pan.baidu.com/s/1gdnouNx. }9 k9 k Y6 Y' L4 s; o' m
8 E7 K& l* e. A& d* q0 R
* S+ Q% S# c, J2 I6 {. B0 v3 K- u" w" D
! l2 i7 ]9 p1 |9 x- S0 _* ]6 o7 }% ]9 W. h
7 h' n! a) y# m* b6 e |
评分
-
查看全部评分
|
/1 
发表于 2015-10-10 09:07
收藏
淘帖
支持！
反对！
楼主
