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本帖最后由 zgyzgy 于 2015-9-1 14:13 编辑
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7 F3 {' X6 g5 _) f2 R$ I* F6 I9 cDATE: 08-28-2015 HOTFIX VERSION: 0567 ~, g; O* {4 N, L/ c
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1134412 allegro_EDITOR PLACEMENT Place replicate creates redundant vias and shapes- option required to prevent that. `4 Q9 s( U/ O, D. s# |
1431136 ALLEGRO_EDITOR OTHER Cannot z-copy board outline with Contract
* h! X2 G b7 ~% M1432392 ORBITIO INTERFACES SiP db import is 鈥渃rashing鈥� if no xda inside( m# I c% X0 T- b
1444820 CONSTRAINT_MGR concept_HDL Exporting TCF file from Constraint Manager does not output physical and spacing constraints' Z! ~- L M. }7 {, I' C; t
1447986 F2B DESIGNVARI All the DNI parts not available after saving the variant file
9 S5 K7 _) W# k$ c* p3 Z1455901 CONCEPT_HDL CORE Need the ability for the front end tool license to have the High Speed option selected by default
4 y/ e$ m$ X# p5 Z6 i$ n1456280 ALLEGRO_EDITOR DRC_CONSTR DRC not shown even when the constraint is violated
. e9 K1 U' ^ S% `1458272 SIP_LAYOUT ASSY_RULE_CHECK File size increases by factor 4 after ADRC check on a specific customer design% S* m- d+ ]. w8 B7 Z5 `8 Q/ K7 [
1458960 CONCEPT_HDL OTHER Getting packaging error when SEC_TYPE and PACK_TYPE properties go out of sync due to a manual name change in chips.prt
& r0 {/ N) {: b% A% F; F( `8 i1459961 CONCEPT_HDL PDF Publish PDF command issues: Logo (.gif file) not rotated, font changed in the published file8 |( n( e- D* u) s9 v2 f* X; ]
1460178 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor crashes on deleting vias or nets3 _, t4 k( p5 ^" u
1460204 SIP_LAYOUT IMPORT_DATA BGA Text In wizard ignores the primary pad layer set in text file6 O- m" V7 C, U8 c% l5 U( s
1460246 APD OTHER axlDeleteObject() command is not removing the die from the design
7 T! U7 z6 ]; q1461387 SIP_LAYOUT skill axlDBRefreshID(nil) removes ID from assigned variable
6 r7 _5 v* V( F0 K v$ q1461625 SIP_LAYOUT ASSY_RULE_CHECK Core polygon routines are not creating proper polygons; ADRCs reported: "acute angle", "exposed metal to exposed metal") E- |' }, M/ U: Q4 \
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发表于 2015-8-31 18:20
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