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DATE: 07-31-2015 HOTFIX VERSION: 054+ S4 a) [. w0 z' A1 H6 F
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694479 concept_HDL OTHER Need version control of symbols in DE-HDL8 l7 `, h4 J3 t; o! ?; v5 {6 \
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions! \5 {( w# A$ b) I3 O
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List7 N6 T. c- p" y% u8 ?2 b, f5 o
1357843 allegro_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate
+ Z& u- g( A5 u3 E- Z! j1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees' @6 s3 k' J, C
1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias
2 D! A! c& S" Y' Y! E% F1412635 APD DATABASE APD crashes on saving design5 _$ | `% k. ~- Z3 x) x7 i
1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices
^, w1 s2 A) [1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation3 L# G6 V$ S$ R8 f L
1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.
, H0 |6 { D' b* T9 r: N1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50
+ }' U* X# n+ G1 m4 X: c1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"0 m9 B1 G& H' l- R' q& w) W
1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
/ r* a Q# l( q7 L) o9 F. y1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated
- f T+ A+ T/ v4 u4 H; J1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
7 j' ` N& T T! v8 f1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification
& u( B" ]/ N2 ]% a( `/ ^1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.4 ~6 {# M5 h# t+ L8 j
1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets
3 F W/ r7 E6 y1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor! j# s+ C8 s( m
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow
$ ~% p5 `$ s: j5 S( m J. t- x1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed# m- v/ D# |; a% \2 ~: E
1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board# @6 ~2 E* V6 p
1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks: g+ f9 O2 ]" y# Z% A& |( V8 d0 B
1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports
4 Y3 y1 y* K* o: @2 c! a1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC
# s7 j! ~, n4 _7 c: e; n% M1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary) U! o& v3 H5 ~/ C# J C2 H
1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.0 ~5 Q! w* A# W6 f
1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1
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发表于 2015-8-3 11:54
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